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Version 2.10
PRELIMINARY
THC63LVDM63A/THC63LVDF64A
85MHz LVDS 18 Bit COLOR
HOST-LCD PANEL INTERFACE
General Description
Features
The THC63LVDM63A transmitter converts 21
bits of CMOS/TTL data into LVDS(Low
Voltage Differential Signaling) data stream. A
phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth
LVDS link. The THC63LVDM63A can be
programmed for rising edge or falling edge
clocks through a dedicated pin.
The THC63LVDF64A receiver convert the
LVDS data streams back into 21 bits of
CMOS/TTL data with falling edge clock. At a
transmit clock frequency of 85MHz, 18 bits of
RGB data and 3 bits of LCD timing and control
data (HSYNC, VSYNC, CNTL1) are
transmitted at a rate of 595 Mbps per LVDS data
channel.
21:3 Data channel compression at up to
223 Megabytes per sec throughput
Wide Frequency Range: 20 - 85 MHz
suited for VGA,SVGA,XGA and SXGA
Narrow bus (8 lines) reduces cable size
345mV swing LVDS devices for
Low EMI
Supports Spread Spectrum Clock Generator
On chip Input Jitter Filtering
PLL requires No External Components
Single 3.3V supply with 110mW(TYP)
Low Power CMOS Design
Power-Down Mode
Low profile 48 Lead TSSOP Package
Clock Edge Programmable for Transmitter
Improved Replacement for the National
DS90CF363/364
THC63LVDM63A
TA0-6
CMOS/TTL
INPUTS
TB0-6
TC0-6
7
7
7
THC63LVDF64A
TA+/-
RA+/-
TB+/-
RB+/-
DATA
TC+/- (LVDS)
RC+/-
7
7
7
RA0-6
RB0-6
CMOS/TTL
OUTPUTS
RC0-6
(140 To 595 Mbit/ On Each
LVDS Channel)
TRANSMITTER
CLK IN
(20 To 85MHz)
PLL
R/F
/PDWN
TCLK+/RCLK+/CLOCK
(LVDS)
(20 To 85MHz)
RECEIVER
CLOCK OUT
(20 To 85MHz)
PLL
/PDWN
OPTIONS
CLOCK
TRIGGERING
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Falling Edge
Rising Edge
TRANSMITTER
DEVICE
RECEIVER
DEVICE
THC63LVDM63A(R/F pin=GND)
THC63LVDF64A
THC63LVDM63A(R/F pin=Vcc)
----
-1-
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PIN OUT
TRANSMITTER DEVICE
RECEIVER DEVICE
THC63LVDM63A
THC63LVDF64A
TA4
VCC
TA5
TA6
GND
TB0
TB1
VCC
TB2
TB3
GND
TB4
TB5
R/F
TB6
TC0
GND
TC1
TC2
TC3
VCC
TC4
TC5
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
RC3
RC4
GND
RC5
RC6
N/C
LVDS GND
RARA+
RBRB+
LVDS VCC
LVDS GND
RCRC+
RCLKRCLK+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLKOUT
RA0
TA3
TA2
GND
TA1
TA0
N/C
LVDS GND
TATA+
TBTB+
LVDS VCC
LVDS GND
TCTC+
TCLKTCLK+
LVDS GND
PLL GND
PLL VCC
PLL GND
/PDWN
CLK IN
TC6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VCC
RC2
RC1
RC0
GND
RB6
VCC
RB5
RB4
RB3
GND
RB2
VCC
RB1
RB0
RA6
GND
RA5
RA4
RA3
VCC
RA2
RA1
GND
PACKAGE
48 Lead Molded Thin Shrink Small Outline Package, JEDEC
Unit: millimeters
12.5 ± 0.1
48
25
8.1 ± 0.1
6.1 ± 0.1
4.05
24
1
(1.0)
1.2 MAX
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0.5 TYP
0.20 TYP
-2-
0.10 ± 0.05
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Electrical Characteristics
Vcc = 3.0 - 3.6V, Ta = -10 - +70 ˚C
SYMBOL
PARAMETER
CONDITIONS
CMOS/TTL DC SPECIFICATIONS
VIH High Level Input Voltage
VIL Low Level Input Voltage
VOH High Level output Voltage
VOL Low Level Output Voltage
IIN
Input Current
IPD Pull Down Current
IOS Output Short Circuit Current
IOH=-4mA
IOL=4mA
0V VIN Vcc
R/F pin,VIH=Vcc
VOUT=0V
MIN
TYP
2.0
GND
2.4
MAX
Vcc
0.8
UNITS
0.4
± 10
100
-50
V
V
V
V
µA
µA
µA
350
450
35
mV
mV
1.125 1.25
1.375
35
V
mV
-24
±10
mA
µA
+100
mV
mV
µA
LVDS DRIVER DC SPECIFICATIONS
VOD
∆VOD
VOC
∆VOC
IOS
IOZ
Differential Output Voltage
Change in VOD between
Complimentary Output States
Common Mode Voltage
Change in VOC between
Complimentary Output States
Output Short Circuit Current
Output TRI-STATE Current
RL=100Ω
250
VOUT=0V,RL=100Ω
/PDWN=0V,
VOUT=0V to Vcc
LVDS RECEIVER DC SPECIFICATIONS
VTH
VTL
IIN
Differential Input High Threshold
Differential Input low Threshold
Input Current
VOC=+1.2V
-100
VIN=+2.4V/ 0V
Vcc=3.6V
Absolute Maximum Ratings (Note 1)
Supply Voltage (Vcc)
-0.3 to +4V
CMOS/TTL Input Voltage
-0.3V to (Vcc + 0.3V)
CMOS/TTL Output Voltage
-0.3V to (Vcc + 0.3V)
LVDS Receiver Input Voltage
-0.3V to (Vcc + 0.3V)
LVDS Driver Output Voltage
-0.3V to (Vcc + 0.3V)
Output Short Circuit Duration
continuous
Junction Temperature
+150˚C
Storage Temperature Range
-65˚C to 150˚C
Lead Temperature(Soldering, 4 sec.)
+260˚C
Maximum Power Dissipation @25˚C
1.4W
Note 1:"Absolute Maximum Ratings" are those values beyond which the safety of the
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device cannot be guaranteed. They are not ment to imply that the device should
be operated at these limits. The tables of "Electrical Characteristics"
specify conditions for device operation.
-3-
±10
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Supply Current
Vcc = 3.0 - 3.6V, Ta = -10 - +70 ˚C
SYMBOL
PARAMETER
CONDITIONS
TYP MAX
UNITS
ITCCG
RL=100Ω,CL=5pF,
Transmitter Supply Current Vcc=3.3V,
16 Grayscale Pattern
f=65MHz
33
41
mA
f=85MHz
37
45
mA
ITCCW
RL=100Ω,CL=5pF,
Transmitter Supply Current Vcc=3.3V,
Worst Case Pattern
f=65MHz
35
43
mA
f=85MHz
39
47
mA
ITCCS
Transmitter Power Down
Supply Current
/PDWN =0 V
10
µA
IRCCG
Receiver Supply Current
CL=8pF, Vcc=3.3V,
16 Grayscale Pattern
f=65MHz
33
43
mA
f=85MHz
44
54
mA
CL=8pF, Vcc=3.3V,
Worst Case Pattern
f=65MHz
58
75
mA
f=85MHz
70
87
mA
10
µA
IRCCW Receiver Supply Current
IRCCS
Receiver Power Down
Supply Current
/PDWN =0 V
16 Grayscale Pattern
CLK IN
Tx0/Rx0
Tx1/Rx1
Tx2/Rx2
Tx3/Rx3
Tx4/Rx4
Tx5/Rx5
Tx6/Rx6
Worst Case Pattern
CLK IN
EVEN TxIN/RxIN
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ODD TxIN/RxIN
-4-
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Switching Characteristics
Vcc = 3.0 - 3.6V, Ta = -10 - +70 ˚C
SYMBOL
PARAMETER
MIN
TRANSMITTER
t TCIT
CLK IN Transition Time
t TCP
CLK IN Period
t TCH
CLK IN High Time
t TCL
CLK IN Low Time
t TCD
CLK IN to TCLK+/- Delay
t TS
TTL Data Setup to CLK IN
t TH
TTL Data Hold from CLK IN
t LVT
LVDS Transition Time
t TOP1
Output Data Position 0 (T=11.76ns)
t TOP0
Output Data Position 1 (T=11.76ns)
t TOP6
Output Data Position 2 (T=11.76ns)
t TOP5
Output Data Position 3 (T=11.76ns)
t TOP4
Output Data Position 4 (T=11.76ns)
t TOP3
Output Data Position 5 (T=11.76ns)
t TOP2
Output Data Position 6 (T=11.76ns)
t TPLL
Phase Lock Loop Set
RECEIVER
t RCP
CLK OUT Period
t RCH
CLK OUT High Time
t RCL
CLK OUT Low Time
t RCD
RCLK+/- to CLK OUT Delay
t RS
TTL Data Setup to CLK OUT
t RH
TTL Data Hold from CLK OUT
t TLH
TTL Low to High Transition Time
t THL
TTL High to Low Transition Time
t RIP1
Input Data Position 0 (T=11.76ns)
t RIP0
Input Data Position 1 (T=11.76ns)
t RIP6
Input Data Position 2 (T=11.76ns)
t RIP5
Input Data Position 3 (T=11.76ns)
t RIP4
Input Data Position 4 (T=11.76ns)
t RIP3
Input Data Position 5 (T=11.76ns)
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t RIP2
Input Data Position 6 (T=11.76ns)
t RPLL
Phase Lock Loop Set
-5-
TYP
MAX
UNITS
5.0
ns
11.76
T
50.0
ns
0.35T
0.5T
0.65T
ns
0.35T
0.5T
0.65T
ns
2T/7
ns
2.5
ns
2.5
ns
0.6
1.5
ns
-0.2
0.0
0.2
ns
T/7-0.2
T/7
T/7+0.2
ns
2T/7-0.2
2T/7
2T/7+0.2
ns
3T/7-0.2
3T/7
3T/7+0.2
ns
4T/7-0.2
4T/7
4T/7+0.2
ns
5T/7-0.2
5T/7
5T/7+0.2
ns
6T/7-0.2
6T/7
6T/7+0.2
ns
10.0
ms
50.0
ns
11.76
T
4T/7
ns
3T/7
ns
5T/7
ns
3T/7-2.5
ns
4T/7-3.5
ns
3.0
5.0
ns
3.0
5.0
ns
-0.4
0.0
0.4
ns
T/7-0.4
T/7
T/7+0.4
ns
2T/7-0.4
2T/7
2T/7+0.4
ns
3T/7-0.4
3T/7
3T/7+0.4
ns
4T/7-0.4
4T/7
4T/7+0.4
ns
5T/7-0.4
5T/7
5T/7+0.4
ns
6T/7-0.4
6T/7
6T/7+0.4
ns
10
ms
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AC TIMING DIAGRAMS
TRANSMITTER DEVICE
t TCP
t TCH
t TCL
2.0V
0.8V
2.0V
CLK IN
t TH
t TS
2.0V
0.8V
Tx0-Tx6
2.0V
0.8V
2.0V
0.8V
DATA VALID
2.0V
0.8V
t TCD
Tx+/-
Tx6
TCLK+
Tx5
Tx4
Tx3
Tx2
Tx1
Vdiff=0V
t TOP1
t TOP0
t TOP6
t TOP5
t TOP4
t TOP3
t TOP2
Note:
1) CLK IN:
for THC63LVDM63A(R/F=GND), denoted as solid line,
for THC63LVDM63A(R/F=Vcc), denoted as dashed line
2) Vdiff = (TA+) - (TA-), .... (TCLK+) - (TCLK-)
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-6-
Tx0
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AC TIMING DIAGRAMS
RECEIVER DEVICE
t RIP2
t RIP3
t RIP4
t RIP5
t RIP6
t RIP0
t RIP1
Rx+/-
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
Rx0
Vdiff=0V
RCLK+
t RCD
t RCL
t RCH
CLK OUT
2.0V
2.0V
2.0V
0.8V
t RCP
t RS
2.0V
Rx0-Rx6
0.8V
Note:
1) Vdiff = (RA+) - (RA-), .... (RCLK+) - (RCLK-)
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-7-
DATA VALID
0.8V
t RH
2.0V
0.8V
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AC TIMING DIAGRAMS
TRANSMITTER DEVICE TRANSITION TIMES
90%
TTL Input
CLK IN
90%
t TCIT
10%
10%
t TCIT
LVDS Output
Vdiff = (TA+)-(TA-)
TA+
5pF
100Ω
80%
Vdiff
80%
t LVT
20%
20%
t LVT
TALVDS output load
RECEIVER DEVICE TRANSITION TIMES
TTL Output
TTL Output
8pF
80%
TTL Output
20%
80%
t TLH
20%
t THL
TTL output load
PHASE LOCK LOOP SET TIME
TRANSMITTER DEVICE
/PDWN
VCC
2V
3.6V
3.0V
t TPLL
CLK IN
Vdiff=0V
TCLK+/RECEIVER DEVICE
/PDWN
VCC
2V
3.6V
3.0V
t RPLL
RCLK+/-
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2V
CLK OUT
-8-
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TOPShine Electronics Corp.
5th. FI.,No. 68, Chou-Tze St.,Nei Hu Dist.,
Taipei 114, Taiwan, R. O. C.
Tel: 02-8797-3667
Fax: 02-8797-3677
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