16th Microelectronics Workshop
Oct 22-24, 2003
(MEWS-16)
Tsukuba Space Center
JAXA
1
The proposed presentation explores the use of commercial
processes, including deep-sub micron process technology,
package technology, and COTS products in satellite and
satellite launch vehicle applications.
To support Aeroflex aggressive product development plans a
fab independent business model was selected along with a
mind set to leverage leading edge commercial technology in the
development of products targeted for satellite applications.
jose.martins@aeroflex.com
2
Aeroflex Fabless Business Model
Technology
Requirements Definition
Foundry Relationships
Device Characterization
Library Development
Customer Design
Circuit Design / Chip Layout
Wafer Fabrication
Inventory for:
Standard Parts
Generic Parts
Foundry for:
New / Future Parts
ASICs
Die Packaging and Test
Reliability, Failure Analysis
Customer Support
Circuit Card Assembly
3
Aeroflex Technology Roadmap
Former UTMC Foundry
UTB --- UTD/R --- UTE/R
3µ
1.5µ
1.2µ
UTMC’s GA/SA Architecture,
Design Library, CAD System
3.3/5V Digital CMOS
Mixed Signal (3.3/5V)
NV (Floating Gate)
Inherent
RadHard
Process
AMI / Hyundai
Commercial Foundry
3.0µ, 1.2µ, 0.6µ, 0.35µ
UTMC’s SA/SC Architecture,
Design Library, CAD System
1.8/2.5/3.3V Digital CMOS
Dense Embedded SRAM
Mixed Signal (2.5/3.3V)
NV (Flash, Anti-Fuse)
TSMC/WaferTech, Hyundai,
NSA/SPL (Nat'l Semi)
Commercial Foundry 0.25µ
UTMC’s SA/SC Architecture,
Design Library, CAD System
1.8/2.5/3.3V Digital CMOS
Dense Embedded SRAM
GA - Gate Array
SA - Structured Array
SC - Standard Cell
Commercial /
Strategic
RadHard™
Module
&
RHbyDesign™
TSMC/WaferTech, Hyundai
Commercial Foundry 0.18µ
4
Commercial RadHard™ Module
Standard Commercial Process
Bulk
Wafer
Start
OP 62
OP 63
Standard
Acceptance
Tests
OP 64
Module Insertion Point
Commercial RadHard™
RadHard™ Process
Epi
Wafer
Start
OP 62
Epi Starting
Wafers
OP 63
OP 64
MOD OP 1
MOD OP 2
Standard
Acceptance
Tests
Standard Wafer
Acceptance
Testing
Non-Invasive
Process Module
5
Commercial RadHard™Passes > 300 krad(Si)
Standard AMI Lot 62283.1
20X0.6 µ m N-Channel Transistor
Leakage Limit
0 krad
3 krad
10 krad
20 krad
30 krad
PASS
1.0
2.0
Vg (V)
3.0
Standard Transistor Fails
~3 krad(Si)
1.0E-01
1.0E-02
1.0E-03
4.0 1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
1.0E-12
Commercial RadHardTM Lot 78485.1,
20X0.6 mm N-Channel Transistor
0 krad
50 krad
Id (A)
Id (A)
1.0E-01
1.0E-02
FAIL
1.0E-03
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
1.0E-12
-1.0
0.0
FAIL
Leakage Limit
100 krad
150 krad
200 krad
300 krad
PASS
400 krad
-1
0
1
Vg (V)
2
3
4
With Commercial RadHard,
Transistor Passes > 300 krad(Si)
6
Aeroflex UT0.6µm RadHard SEU
1.00E-05
-2
Error X-Section / Bit (cm )
DFF
1.00E-06
LDFF
1.00E-07
SDFF
Adams 90% Worst Case Geo Error Rate
1.00E-08
Updated August 1999
DFF 5.0E-8 errors/bit-day
LDFF 5.0E-9 errors/bit-day
SDFF 1.0E-10 errors/bit-day
SEL immune > 128MeV
1.00E-09
1.00E-10
1.00E-11
0
20
40
60
80
100
120
140
2
LET (MeV-cm /mg)
7
Aeroflex UT0.25µm RadHard SEU
SEU Results
1.0E-05
-2
Error Cross-Section Per Bit (cm )
2.25V, Room Temperature
1.0E-06
LDFF
1.0E-07
SDFF
DFF
1.0E-08
EDFF
Adams 90% Worst Case Geo Error Rate:
1.0E-09
DFF 1.65E-8 errors/bit-day
LDFF 6.74E-9 errors/bit-day
SDFF 2.18E-9 errors/bit-day
EDFF 1.59E-11 errors/bit-day
1.0E-10
1.0E-11
0
20
40
60
80
100
120
140
2
LET (MeV-cm /mg)
8
0.25µm Fabless Business Model In Practice
Test: Two Technology Characterization Vehicles (TCVs)
Classified ASICs: 1.8M Gates, 1.95M Gates, 300K Gates
Aeroflex
Classified Services
Radiation Hardness
IC Design Expertise
Assembly/Test
Quality Assurance
Advance EHF
Program
Wafer
Personalization
(metal layers)
@ NSA/SPL
National Semiconductor
TSMC 0.25µ Process
Underlayers
Test: Two Technology Characterization Vehicles (TCVs)
ASICs: 500K Gates
NPOESS
Program
Aeroflex
Radiation Hardness
IC Design Expertise
Assembly/Test
Quality Assurance
TSMC 0.25µ Process
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UT8R512K8 / UT8R128K32 SRAM - 0.18µm Bulk
CMOS

4Mbit SRAM
– Aeroflex design for low power, high speed,
and SEU performance
– Organized as 512K x 8 and 128K x 32

15ns access time, asynchronous operation
– Both read and write


Commercial architecture and compatible pin-out
-55oC to +125oC
– LVCMOS inputs and outputs


I/O Voltage: 2.5 to 3.3 volts
Memory core: 1.8 volts
10
UT8R512K8 / UT8R128K32 SRAM - 0.18µm Bulk
CMOS

Design Approach
Full custom layout
Spatial design rules added to the base process to
mitigate Single Event Latch-up and improve Dose
Rate Response

Single Event Upset
12T Memory Cell
Redundant latches and flip-flops

Total Ionizing Dose
CRH Module (“edged transistor design” due to the
required packing density)

Fast Access Time and Low Power Consumption
Commercial architecture and layout techniques
Pulsed architecture along with 1.8 volt core
11
Aeroflex RadHard LVDS Family
12
UT54LVDS031 Quad Driver

LVDS driver consists of a current source
output which drives a closely-coupled (closelyspaced) differential pair of conductors
– 340mV nominal differential signals
DIN 1
DOU T1+
D1
DOU T1-
DIN1
1
16
VCC
DOUT1+
2
15
DIN4
DOUT1-
3
14
DOUT4+-
EN
4
13
DOUT4-
UT54LVDS031
5
12
DRIVER
6
11
DOUT2DOUT2+
DIN 2
DOU T2-
EN
DIN 3
DOUT3-
DIN2
7
10
DOUT3+
GND
8
9
DIN3
DOU T2+
D2
DOU T3+
D3
DOU T3-
DIN 4
DOU T4+
D4
DOU T4-
EN
EN
13
UT54LVDS217/218 Serializer and Deserializer
UT54LVDS217 converts 21 bits of CMOS data
into three LVDS data streams
– A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link
– Every cycle of the transmit clock, 21 bits of input data
are sampled and transmitted
– UT54LVDS218 receiver converts the LVDS data
streams back into 21 bits of CMOS data
CMOS
Input (21)
Transmit
Clock
D1
PLL
D4
+
R1
-
D2
+
(140 to 280
Mbps on each
LVDS Channel)
R1
-
+
D3
R1
-
UT54LVDS217
CLOCK (LVDS)
(20 to 40 MHz)
+
R1
LVDS to CMOS Parallel
DATA (LVDS)
CMOS Parallel to LVDS

CMOS
Ouput (21)
PLL
Receiver
Clock
-
UT54LVDS218
14
Microcontrollers
15
UT80CRH196KDS
16-bit Rad-Hard CMOS microcontroller
– Built using Commercial RadHardTM process
technology
• Total dose greater than 100Krads(Si)
• Single Event Latch-up Immune
– LET Threshold around 25MeV-cm2/mg
– Saturated Cross Section is 6.0-7 cm2/bit
•
Feature
Addressable Memory Space
Internal RAM (including SFRs)
One Time Programmable ROM
Maximum Operating Frequency
UT80CRH196
64K Kbytes
1024 bytes
0 bytes
20 MHz
16
UT80CRH196KDS
 System Block Diagram
1553/1773
UT80CRH196
Serial Port
Logic
Volatile
Memory
Non
Volatile
Memory
17
UT54ACS162245S Multipurpose Transceiver
18
UT54ACS162245S Multipurpose Transceiver

Functional description
– 16 bit wide bi-directional bus driver

Dual bus architecture
– Separate power and control for Port A and Port B
– Word (16 bits) and byte (8 bits) control
– Control signals are 2.5 Volt compatible, 3.3 Volt tolerant

Total dose irradiation testing to MIL-STD-883
Method 1019
– Intrinsic total dose: 1M rad(Si) nominal (wafer lot
specific)
– Latchup immune (LET > 100 MeV-cm2/mg)

Packaging
– 48-lead flatpack


3.3V bus to 2.5V bus
2.5V bus to 3.3V bus
19
UT54ACS162245S Multipurpose Transceiver
System Block Diagram
VDD
ON
VDD
ON
Back-plane
Interface
Logic
3.3
Volt System
Processor
System
Clock
Voltage
Translator
(Low Noise)
(3.3V/2.5V)
(2.5V/3.3V)
2.5 Volt
Memory
System
20
Aeroflex QCOTS™ Program
Program Goal
The Aeroflex QCOTS program aims to bring leading
edge, high performance commercial products (COTS)
into the space community. By quantifying specific
attributes of COTS products, building the product form
a homogenous wafer lot of material, and performing
in-depth electrical, structural, and radiation hardness
assurance analyses, Aeroflex can offer a commercially
designed and fabricated product with a quality on par
with traditional “S” level components.
21
Aeroflex QCOTS™ Program
The Approach
Quantify (Q) specific attributes of Commercial Off-The-Shelf Product
(COTS) for use in spaceborne electronics.
Build product out of a homogenous wafer lot of material
Guarantee immunity to charge particle induced latchup (>100MeVcm2/mg) and quantify charge particle induced upset LET and crosssection on every wafer lot.
Guarantee a minimum of 90/90 survival probability to ionizing dose
on every wafer lot.
Demonstrate reliability for space mission applications (requirement
of <10FITs with <1FITs possible). Wafer lot specific life testing,
same as QML V (0% PDA, Better than QML V)
22
Aeroflex QCOTS™ Program

Benefits of Aeroflex’s QCOTS™ Approach
– Single Event Latchup Immunity: Guaranteed and
tested (on every wafer lot) by Aeroflex
– Single Event Upset: Quantified cross section and
on-set LET evaluation, tested for every wafer lot
– Total Dose: Wafer lot qualification performed by
Aeroflex
– Reliability: Wafer lot FIT rate evaluation using
proven accelerated life-test techniques, 0% PDA
allowed for shippable units
– Manufacturing Flow: Built by Aeroflex, an industry
leader in QML manufacturing techniques
– Standard Product: Sold to an Standard Microcircuit
Drawing (SMD)
23
UTXQ512 4M SRAM

4Mbit density
– Organized 512K x 8
– 100ns (X=7) and 25ns (X=8 or X=9) access time, asynchronous
operation

Commercial architecture and compatible pin-out
– TTL inputs and outputs (100ns, X=7)
– TTL inputs and outputs (25ns, X=8 or X=9)

CMOS outputs (i.e., low and high current specifications)
– 5 volt operation (100ns product, X=7) - SMD 5962-99606

Inputs are not 3.3 volt compatible
– 3.3 volt operation (25ns product, X=8) - SMD 5962-99607

Inputs are not 5 volt tolerant
– 5 volt operation (25ns product, X=9) - SMD 5962-00536


Inputs are not 3.3 volt tolerant
Available in military and industrial temperature ranges
24
UTXQ512 4M SRAM
25
UT9Q512 4M SRAM

Total dose irradiation testing to MIL-STD-883
Method 1019
– Intrinsic total-dose: 50K rad(Si) nominal (wafer lot
specific)
– Space environment shields to greater than
100Krad(Si)
 36-lead surface mount patented UTMC shielded
package only

SEL Immune >80 MeV-cm2/mg (3 per lot
testing)
– LETTH (0.25) ~10 MeV-cm2/mg
– Saturated Cross Section (cm2) per bit ~5.0E-9
– <1E-8 error per bit-day (Adams 90% worst case,
geosynchronous)
26
UT8Q1024K8 8M SRAM
27
UT8Q1024K8 8M SRAM

Packaging
– 44-lead dual cavity ceramic flatpack


4.6 grams
Single 3.3+/-10% volt supply (25ns)
– Average Operating Current, 100% duty cycle, 1MHz
 Read/Write cycle < 125mA
– Average Operating Current, 100% duty cycle,
40MHz
 Read/Write cycle < 180mA
– CMOS Stand-By Current (Post-Rad, nominal
conditions)
 < 6mA
28
UTXQ512K32 16M SRAM MCM
29
UTXQ512K32 SRAM MCM

MCM contains four (4) 512K x 8 industrystandard asynchronous SRAMs; the control
architecture allows operation as 8, 16, 24, or
32-bit data width
– TTL inputs and outputs (25ns, X=8 or X=9)

CMOS outputs (i.e., low and high current
specifications)
– 3.3 volt operation (25ns product, X=8)

Inputs are not 5 volt tolerant
– 5 volt operation (25ns product, X=9)


Inputs are not 3.3 volt tolerant
Available in MIL-TEMP and Industrial
temperature ranges
30
Technology Summary

Aeroflex continues to meet our customer’s RadHard
requirements through commercial foundry technology
– 6th year of QML production using our minimally invasive process
changes for Commercial and Strategic RadHard environments (0.6µ
- AMIS) – FIT rates now below 2
– RHbyDesign™, taking advantage of the inherently radiation
hardened characteristics present in commercial submicron
processes today
(0.25µ – TSMC)
– Exploring 0.13µ RHbyDesign using third party standard cell
libraries and commercial foundries

Aeroflex’s Fab Independent Business Model:
– Continues to supply needed technologies - mitigating
“last-time-buy” decisions (3.0m, 1.5m, 1.2m, 0.8m; 5V & 3.3V)
– while delivering Leading-edge, Deep Submicron, Rad-Hard
Technology without significant capital equipment investments
31