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1
A Capacitor Charge Pump DC-DC Converter
for Physics Instrumentation
Peter Denes, Member, IEEE, Robert Ely, Maurice Garcia-Sciveres,
Abstract—We have prototyped a switched capacitor DC-DC
converter aimed at powering low voltage integrated circuits in
particle physics instrumentation. The ideal output current is 4
times the input current. The prototype was built using a CMOS
integrated circuit containing all switches and switch driver
circuitry, with external capacitors and clocks. We present
measurements of performance with and without irradiation.
Index Terms—DC-DC converter, switched capacitor, charge
pump, high voltage CMOS, LDMOSFET.
I. INTRODUCTION
T
HE silicon tracking detectors of the ATLAS [1] and CMS
[2] experiments at the Large Hadron Collider (LHC) [3]
incur a performance penalty due to power distribution to the
on-detector electronics. The performance degradation is due to
the mass of the conductors needed to carry the large operating
current with acceptable voltage drop [4]. The impact of this
added mass is felt by the calorimeters at large radius in
addition to the tracking detectors. Future silicon detectors will
necessarily use lower voltage electronics, thus aggravating the
problem, which can be characterized by the power distribution
efficiency. Already for the present ATLAS pixel detector [5]
the power distribution efficiency is just over 20%. The well
known solution to this problem, to distribute power at higher
voltage, will be a requirement for future silicon detectors. This
paper explores a possible implementation of higher voltage
distribution based on switched capacitor DC-DC converters.
To be compatible with silicon detectors at the LHC, a DCDC converter must be radiation tolerant, low mass, and must
operate in a magnetic field of up to 4T. Whereas commercial
DC-DC converters for power applications are inductive
because higher efficiency can be achieved, this advantage is
eliminated in a strong magnetic field where ferrites saturate
and only air core inductors can be used. We therefore chose to
explore the potential of capacitors, which are naturally
compatible with magnetic fields and benefit from an industrial
Manuscript received April ??, 2008. This work was supported by the U.S.
Department of Energy Office of Science under Contract Nos. DE-AC0205CH11231.
All authors are with the E. O. Lawrence Berkeley National Laboratory,
Berkeley, CA 94720, USA (corresponding author e-mail: MGarciaSciveres@lbl.gov).
trend of increasing stored energy density (and therefore
decreasing mass), while air core inductors are at the physical
limit. Radiation tolerance is a potential issue for the switch
technology used.
II. DESIGN
The use of switched capacitors for DC-DC conversion has
been known for over a century [6]. Different capacitor
configurations are possible for a given conversion ratio,
offering trade-offs between number of capacitors and switches,
theoretical efficiency limit, and switch voltage specifications
[7]. We chose to prototype a divide-by-4 “stack” configuration
because it is simple to analyze, compact, and tests a range of
conditions for the switches. The basic circuit uses 3 “flying”
capacitors plus input and output capacitors, as shown in Fig. 1.
A total of 10 switches are needed, 7 of which must hold off a
voltage higher than the output, ranging up to the full input
voltage. A 0.35µm feature size CMOS process with lateral
diffusion MOSFET transistors as well as substrate-isolated
devices was chosen to implement all the switches on a single
Phase A
+
Vd
+
1
+
+
2
3
4
+
Load
Phase B
Vd
5
+
6
+
8
7
+
9
+
+
10
Load
Fig. 1. Diagram of divide-by-4 stack capacitor configuration shown in the
two alternating phases. The numbered solid circles represent closed
switches. All the switches closed in Phase A are open in Phase B and viceversa.
TABLE I
SWITCH PROPERTIES
Switch
Type
1
2,3,4
5-10
LDPMOS
I-NMOS
LDNMOS
Max.
Vds (V)
50
3.3
50
W/L
(cm/um)
11.2 / 1.0
2.4 / 0.35
5.0 / 0.5
Layout
area
(mm2)
1.34
0.18
0.66
Nominal on
resistance
(Ω)
0.33±.05
0.25±.04
0.42±.08
In all cases the maximum Vgs is 3.3V. I-NMOS stands for substrate-isolated
NOMS. The rated isolation is up to 50V.
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integrated circuit (IC). The characteristics of the switches used
are summarized in Table I.
While the switches and driver circuits were implemented as
a single IC, all the capacitors were discrete. Although the
charge-in-series,
discharge-in-parallel
approach
is
conceptually simple, it imposes certain constraints on the
design. Figure 2 shows a block diagram of the IC. The series
switches consist of an entrance PMOS, followed by 3 NMOS
transistors. As the entrance PMOS sees the full input voltage
at startup (when all of the capacitors are discharged) this must
be a high voltage device. The series NMOS, however, can be
low voltage devices. Conversely, the parallel NMOS switches
generally have drain-source voltages greater than those
allowed for low voltage devices, and thus must be high voltage
devices.
2
and that requires generation of intermediate VDDLV supply
rails relative to the sources of the switching NMOS transistors.
These intermediate voltages are developed by the blocks
labeled “∆V = VDD” in Figure 2, and the voltage difference
(relative to the NMOS source) is stored on external capacitors.
For the ideal case of linear (dis)charging of all capacitors
and perfect current efficiency, every switch conducts, when
closed, a constant current equal to half the output current, IO/2
(for this particular topology). Since any switch is only closed
in one phase (i.e. half of the time), the average power
dissipated in any given switch is ½(IO/2)2R and so the total
power loss is ⅛IO2ΣR. From this it follows that the expected
output resistance in the limit of ideal operation is ⅛ΣR, or in
this case 0.45±.08 Ω (from Table I, assuming the all errors are
100% correlated).
VIN
A
∆V = VDD
∆V = VDD
Ro
x4
A
Rs
out
L
∆V = VDD
V
in
∆V = VDD
Fig. 3. Equivalent circuit for prototype device (dashed box) and test setup.
∆V = VDD
III. PROTOTYPE TEST RESULTS
Load
CHG
I/O Pad
DIS
Level Shift
Gate Driver
Bulk Driver
Fig. 2. Circuit schematic of the DC-DC converter IC.
Three principal modules had to be developed for this
circuit: the switch drivers, their power supplies, and a lowpower level shifter. In this circuit, the voltage swings on the
charge-storing capacitors illustrated in Figure 1 can be much
more than VDDLV, the low voltage supply value for the
process. Consider the NMOS switch following the entrance
PMOS switch: in the charging (CHG) phase, its drain and
source voltages are (nominally) VIN – VOUT. In the
discharging phase (DIS), its “drain” voltage is ground,
whereas its “source” voltage is VOUT, i.e. drain and source
swap terminals between the two phases. The NMOS bulk
must therefore be actively driven in order to avoid drain-bulk
breakdown.
In driving the high-capacitance nodes represented by the
switches, both analog (op amps or op amp comparator
combinations) and digital (inverter chains) techniques are
commonly used. For this circuit, inverter chains were selected,
A prototype board was prepared using 0402 package size
capacitors for all except the input and output, which were
0603. The values used were 1µF for the input and the flying
capacitors, and 10µF for the output. The equivalent circuit for
the DC-DC converter and test setup are shown in Fig. 3. The
converter is modeled as a perfect x4 converter plus output and
shunt resistances to be determined experimentally. For the
perfect converter the output current is exactly 4x the input
current and the output voltage is exactly ¼ the input voltage.
The output resistance was determined by measuring the load
current IO, vs. the supply voltage, VDD, for different loads and
at different frequencies. The device was always operated with
a constant clock of 50% duty cycle. The shunt resistance has
no effect on the output resistance measurement. The VDD, IO
data for 1.5µs clock period, as well as the best fit VDD/IO
slopes vs. load for 1.5, 3.1, and 4.5µs period are shown in Fig.
4. The output resistances (from the intercept of the VDD/IO
slope vs. load) are summarized in Table II.
The shunt resistance was determined by fitting 4IDD-IO vs.
the voltage at the ideal converter output (equal to VDD/4) for
different load resistors, where IDD is the input current. The
data for 1.5us clock period is shown in Fig. 5. There is
reasonable agreement for loads greater than 2.7Ω. For the
2.7Ω load there is clearly additional shunt current in the
device, which is thought to arise from overheating. A fancooled heat sink was used, but nevertheless over-heating is
suspected because the chip is not thinned and is mounted on a
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Fig. 4: Results of output resistance measurement. The slope of each of the
lines on the left panel is shown as a function of load on the right panel (plus
symbols). The two other lines on the right plot show the results for 3.1 and
4.5µs period. In each case the points fit a line of unit slope. The zero load
intercept of this line gives the output resistance.
printed circuit board. Note that the heating seems to affect the
substrate isolation, but not the switch resistance (since the
output resistance shows no effect). The shunt resistance values
determined from the average slope, ignoring the 2.7Ω load, are
also summarized in Table II.
The circuit was simulated with SPICE using the vendor
supplied transistor models. The Output and Shunt resistances
were determined from simulation currents and voltages in the
same way as for data. The simulation results are given along
side the measurement results in Table II.
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The prototype boards were designed with a compact
footprint using small package external components in order to
estimate the mass one can expect for such devices. A board
footprint of 1.5 x 1.5 cm2 was achieved, housing the prototype
IC plus 11 surface mount capacitors needed for operation
(several auxiliary capacitors are needed for the gate and bulk
drivers). The calculated radiation thickness of this package
(averaging the material over the footprint) is 0.33% of a
radiation length (RL), of which 65% is due to capacitors and
solder. A useful figure of merit is the radiation thickness times
unit area output resistance (RO), which in this case is
RO = 0.9 %RL.Ω.cm2 (at 0 dose and 2µs period). This allows
one to easily assess the “material penalty” to use these devices
in the active region of a particle detector of given load
resistance times unit area (RA). For example, each layer of the
present ATLAS pixel detector has RA ~ 8 Ω.cm2, so the
material penalty to use our prototype DC-DC converters with
~70% efficiency would be 3RO/RA = 0.34%RL per layer
(output resistance of 1/3 the load resistance yields 75% voltage
efficiency). The present ATLAS silicon strip tracker layers [8],
on the other hand, have RA ~ 160 Ω.cm2, so 3RO/RA =
0.02%RL.
TABLE II
MEASUREMENT AND SPICE SIMULATION RESULTS
Clock
period
(µs)
1.5
3.1
4.5
.
Output resistance (Ω)
Shunt resistance (Ω)
Measurement
Simulation
Measurement
Simulation
1.13
1.55
2.03
0.64
0.81
1.00
55
105
134
55
104
125
IV. IRRADIATION AND MASS
One device was continually operated while exposed to 40KeV
x-rays at an approximate dose rate of 2MRad/hr. The exposure
was done in 3 runs of 10MRad each with measurements of
shunt and output resistances in between. Figure 5 shows the
relative change of the resistances with dose. All measurements
were done with 2µs clock, 7Ω load, and input voltages
between 7 and 12V. The markedly different behavior of the
shunt and output resistances is not unexpected. The output
resistance is simply given by the switch on resistance and is
not affected by threshold shifts due to gate oxide charging,
since switches are turned fully on or fully off. It is reasonable
to expect that the on resistance of the LDMOSFETs might
degrade linearly with dose, as observed. In contrast, shunt
current to ground is due to support circuitry (gate and bulk
drivers and bias generators), which were not implemented
using any special provisions to make them radiation tolerant.
Threshold shifts of the transistors in these analog circuits will
lead to degraded performance and non-uniform behavior. This
is just what we observe as indicated by the large “error” bars,
which do not indicate any statistical uncertainty, but rather the
variation with input voltage of the values obtained.
Fig. 5. Change in output and shunt resistances with ionizing radiation
dose. The error bars indicate the variation with input voltage (RMS), not
any statistical uncertainty.
V. CONCLUSIONS
A proof of principle prototype device has been tested to
demonstrate the feasibility of custom-made switched capacitor
DC-DC converters for power distribution in particle physics
instrumentation. Further development would be needed to turn
this prototype into a production device, including re-design of
the control circuitry for radiation hardness, selection of
capacitor topology and packaging to optimize the radiation
thickness times unit area output resistance figure of merit
(RO), and system testing with the target load devices to
determine operating frequency and output noise requirements.
For not very high power density applications such as silicon
strip detectors the prototype performance is already adequate
in terms of material penalty. However, for high power density
pixel detectors the material penalty appears too severe. Even if
zero-dose RO can by halved by topology and packaging
optimization (this seems achievable since we have not used the
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lowest output resistance topology or the smallest available
package for auxiliary capacitors), one must design for “end of
life” RO taking into account output resistance degradation.
Therefore, we conclude that a substantially better (lower
specific output resistance) switch technology is needed in
order to achieve adequate performance for pixel detector
applications.
We have not addressed here questions of output ripple,
noise spectrum, and EMI, as these are system specific. The
output ripple is well understood function of the capacitor
values and operating frequency. Noise spectrum and EMI will
depend on board layout, shielding, etc., and one needs to
understand the requirements of the load device before trying to
optimize them. If needed, it is possible to add a low dropout
linear regulator to the output, which will introduce an
efficiency penalty that can be absorbed into the RO figure of
merit.
ACKNOWLEDGMENT
We thank CERN for the use of the x-ray irradiation facility.
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[4]
[5]
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URL: http://atlas.ch
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