Curriculum Vitae of Felice Crupi
GENERAL DATA
Birth
Position held
Address
Phone
E-mail
Skype name
Website
21 Dec. 1972, Lamezia Terme (CZ), Italy
Associate Professor of Electronics
Dipartimento di Ingegneria Informatica, Modellistica,
Elettronica e Sistemistica (DIMES)
Università della Calabria
Via P. Bucci, 42C I-87036, Rende (CS), Italy
+39-0984-494766
felice.crupi@unical.it
crupife
http://www.felice.crupi.it
OBJECTIVES
1. Developing ideas in the Nanoelectronics area, ranging from atom-level to applied system-level
2. Initiating young students into the fascinating realm of Nanoelectronics research
3. Contributing to the internationalization process of the University of Calabria
EDUCATION
Mar. 2001
Ph.D. degree in “Engineering of the Electronic Systems” from the University of Firenze, Italy.
Thesis’s title: “On the conduction mechanisms in thin SiO2 films” (in english). Scientific
Supervisor: Prof. Bruno Neri (University of Pisa, Italy).
The research activity has been carried out at the Dipartimento di Ingegneria dell’Informazione
of the University of Pisa, Italy.
Mar. 1997
M.S. degree in Electronic Engineering cum Laude from the University of Messina, Italy.
Thesis’s title: “Electrical and structural characterization of thin oxide in poly-silicon gate MOS
structures” (in italian).
Advisors: Prof. Bruno Neri (University of Pisa, Italy) and Prof. Raffaello Girlanda (University of
Messina, Italy); Co-Advisors: Dr. Salvatore Lombardo (National Council of Research, Catania,
Italy), Dr. Antonio Terrasi (National Council of Research, Catania, Italy) and Dr. Giovanni
Franco (ST-Microelectronics, Catania, Italy).
July 1991
“Diploma di maturità classica” with full grade (60/60) from the “Liceo Classico Pitagora” of
Crotone, Italy.
PROFESSIONAL EXPERIENCE
Dec. 2002 - present
Oct. 2008 – Nov. 2008
Oct. 2007
Oct. 2005 – Nov. 2005
Aug. 2004
Aug. 2003 – Sep. 2003
Aug. 2002 – Sep. 2002
Aug. 2001 – Sep. 2001
Aug. 1998 – Nov. 1998
Nov. 1997- Mar. 1998
UNIVERSITY OF CALABRIA
Associate Professor of Electronics at the University of Calabria, Rende, Italy.
IMEC
Visiting Scientist at the Interuniversity MicroElectronics Center (IMEC), Leuven, Belgium.
Research subject: reliability of advanced CMOS devices.
Scientific contact: Prof. Guido Groeseneken.
Oct. 2006 – Nov. 2006
AUTONOMOUS UNIVERSITY OF BARCELONA
Visiting Scientist at the Department of Electronic Engineering of the Autonomous University of
Barcelona, Bellaterra, Spain.
Research subject: performance and reliability of CMOS devices and circuits under forward body
bias.
Scientific contact: Prof. Montserrat Nafría.
Mar. 2000 – Dec. 2002
UNIVERSITY OF MESSINA
Research contract at the Dipartimento di Fisica della Materia e Tecnologie Fisiche Avanzate of
the University of Messina, Italy.
Research subject: electrical characterization of thin oxide layers for VLSI circuits.
Scientific Supervisor: Prof. Carmine Ciofi.
July 2000 – Sep. 2000
IBM THOMAS J. WATSON RESEARCH CENTER
Visiting Scientist at IBM Thomas J. Watson Research Center in Yorktown Heights, New York.
Research subject: characterization of breakdown in ultra thin oxide.
Scientific contacts: Dr. James H. Stathis and Dr. Donelli J. DiMaria.
June 1997 – Oct. 1997
ST-MICROELECTRONICS
NATIONAL COUNCIL OF RESEARCH
Contract with ST-Microelectronics in collaboration with the National Council of Research,
Catania, Italy.
Research subject: electrical and structural characterization of oxide layers in MOS structures.
Scientific Supervisor: Dr. Salvatore Lombardo.
PROJECT MANAGEMENT AND RESEARCH GRANTS
Mar. 2012 – Feb. 2014
Italian Coordinator of the project Power Electronic Systems based on GaN on Si Technology
Option (PEGASO) funded by the Italian Ministry of Foreign Affairs. Project aim: assessment of
the GaN on Si technology for high efficiency power applications. 3 research groups from
industry and academia are involved in the project. Total project budget: 440 kEuro.
Jan. 2010 – Jun. 2011
Local Coordinator of the University of Calabria in the project RAd-hard Memories for Storage
Embedded Systems (RAMSES) funded by the Italian Ministry of Foreign Affairs. Project aim:
design and realization of a radiation tolerant embedded SRAM for power management
platformns actually used to handle general purpose high voltage funcitons. 5 research groups
from industry and academia are involved in the project. Total project budget: 600 kEuro.
Apr. 2008 – Dec. 2009
Italian Coordinator of the project Radiation Immune FLASH Memory (RIFLASH) funded by the
Italian Ministry of Foreign Affairs. Project aim: design and realization of a radiation immune
flash memory. 6 research groups from industry and academia are involved in the project. Total
project budget: 600 kEuro.
2008
Two one-year grants for Indian researchers from the Italian Ministry of University and Research
(MIUR). Research activities in the area of “Nanoscience and nanotechnology” in collaboration
with the Indian Institute of Technology (IIT), Bombay, India. Total budget: 30 kEuro.
2007
Two one-year grants for Indian researchers from the Italian Ministry of University and Research
(MIUR). Research activities in the area of “Nanoscience and nanotechnology” in collaboration
with the Indian Institute of Technology (IIT), Bombay, India. Total budget: 30 kEuro.
2002
Coordinator of the “Progetto Giovani Ricercatori” (“Project for Young Researchers”) funded by
University of Messina. Project aim: design and realization of a high sensitivity, wide bandwidth
current noise measurement system.
TEACHING
2010/11 - 2014/15
Course Title: “Principi di Elettronica Analogica Integrata” (“Principles of Integrated Analog
Electronics”)
Master Degree in Electronic Engineering, University of Calabria
University Credits: 6
2010/11 - 2013/14
Course Title: “Dispositivi Elettronici Avanzati” (“Advanced Electronic Devices”)
Master Degree in Electronic Engineering, University of Calabria
University Credits: 9
2011/12
Course Title: “Sistemi Elettronici” (“Electronic Systems”)
Master Degree in Management Engineering, University of Calabria
University Credits: 6
2010/11
Course Title: “Elettrotecnica” (“Electrotechnics”)
Bachelor Degree in Computer Science Engineering, University of Calabria
University Credits: 6
2004/05 – 2010/11
Course Title: “Elettronica Analogica Integrata” (“Integrated Analog Electronics”)
Master Degree in Electronic Engineering, University of Calabria
University Credits: 6
2003/04 – 2009/10
Course Title: “Caratterizzazione di Dispositivi a Semiconduttore” (“Characterization of
Semiconductor Devices”)
Master Degree in Electronic Engineering, University of Calabria
University Credits: 4 (2003-2004), 5 (from 2004-2005 to 2009-2010)
2003/04 – 2009/10
Course Title: “Elettronica” (“Electronics”)
Master Degree in Management Engineering, University of Calabria
University Credits: 5
2002/03 – 2003/04
Course Title: “Elettronica Digitale” (“Digital Electronics”)
Bachelor Degree in Computer Science Engineering, University of Calabria
University Credits: 5
2002/03
Course Title: “Elettronica” (“Electronics”)
Bachelor Degree in Management Engineering, University of Calabria
University Credits: 4
Total number of courses: 35 (31 Master, 4 Bachelor)
Total university credits: 203
COURSES ABROAD, INVITED LECTURES, TUTORIALS AND SCHOOLS
Aug. 2014
Invited Lecture Title: "Reliability models: from basic theory to application to CMOS
nanodevices"”
PhD course with EURODOTS label
University Residential Centre of Bertinoro (CEUB), Bertinoro, Italy
Apr. 2012
Course Title: “Nanoelectronic Devices”
Undergraduate in Electrical and Electronic Engineering
Universidad San Francisco de Quito, Quito, Ecuador
Nov. 2010 – Dec. 2010
Course Title: “Nanoelectronic Devices”
Bachelor Degree in Electrical Engineering
Satakunta University of Applied Sciences, Pori, Finland
Nov. 2008
Invited Lecture Title: “Low Frequency Noise in Advanced CMOS Devices”
Jointly with IEEE AP/ED Bombay Chapter and IIT Bombay
IIT Bombay, Powai, India
Oct. 2007
Course Title: “Low Frequency Noise: Theory, Instrumentation and Measurement”
PhD course
Katholieke Universiteit Leuven, Leuven, Belgium
Nov. 2006
Course Title: “Reliability and Low Frequency Noise Measurements in Advanced CMOS
Devices”
Master Degree in Micro and Nanoelectronic Engineering
Autonomous University of Barcelona, Barcelona, Spain
ORGANIZATION/SESSION CHAIR CONFERENCES-SYMPOSIA-WORKSHOPS-SCHOOLS
2014
Director of the 6th SINANO Summer School on “Reliability and variability of electron devices”
PhD course with EURODOTS label
Bertinoro, Italy
2011-2012
Technical program committee member of the International Electron Devices Meeting (IEDM) for
the Characterization, Reliability and Yield session
2011
Session chair of the International Electron Devices Meeting (IEDM) for the Characterization,
Reliability and Yield session
2008 – 2010, 2012, 2015
Technical program committee member of the International Reliability Physics Symposium
(IRPS) for the Transistor session
2007
Technical program committee member of the International Reliability Physics Symposium
(IRPS) for the High-k session
2006
Session chair of the Workshop on Dielectrics in Microelectronics (WODIM)
2004 – 2005
Technical program committee member of the International Reliability Physics Symposium
(IRPS) for the Dielectrics session
EDITOR
2011 – present
Dec. 2013
Associate Editor of IEEE Transactions on Device and Materials Reliability
Guest Editor for the Special Section of IEEE Transactions on Device and Materials Reliability
on “Reliability of High-Mobility Channel Materials”
REVIEWER
IEEE Journals
Transactions on Electron Devices, Electron Device Letters, Transactions on VLSI Systems,
Journal of Solid-State Circuits, Transactions on Instrumentation and Measurement
Other Journals
Solid-State Electronics, Microelectronic Engineering, Microelectronics Reliability, Journal of
Applied Physics, Journal of Vacuum Science and Technology B, Microelectronics Journal,
Fluctuation and Noise Letters
MEMBERSHIPS
2014
2011 – 2014
IEEE Senior Member
IEEE Member
AWARDS
2008
Best paper award at the IEEE International Conference on Microelectronics, Nis 2008 for oral
paper “Progressive breakdown dynamics in HfSiON/SiON gate stacks” by E. Miranda, P. Falbo,
M. Nafría, F. Crupi
1995
First ranked in the “Opera Universitaria Scholarships” among all students of Electronic
Engineering of University of Messina, Italy
1985
“Rotari Award” for the best student of the “Scuola Media Corrado Alvaro” of Crotone, Italy
MISCELLANEOUS INFORMATION
He served as an external Ph.D. examiner at:
-­‐ Autonomous University of Barcelona, Spain (4 times)
-­‐ Indian Institute of Technology Bombay, India
-­‐ Nanyang Technological University, Singapore
-­‐ University of Twente, Netherlands
-­‐ Institut National des Sciences Appliquées (INSA) de Toulouse, France.
He has been the Advisor of 26 B.S., 74 M.S. and 2 Ph.D. students in the area of Electronic Engineering.
Since 2010 he is the Representative of the University of Calabria in the Assembly of the Inter-University Nanoelectronics
Team (IUNET).
Since 2004 he is the Erasmus coordinator in the area of Electronic Engineering at the University of Calabria.
In 1999 he served in the civil service at the “Soprintendenza ai Beni Ambientali Architettonici Artistici e Storici” in Pisa, Italy.
RESEARCH ACTIVITY
The research activity of Felice Crupi encompasses the following main areas:
A1. reliability of VLSI CMOS devices
A2. electrical characterization techniques for VLSI CMOS devices
A3. modeling and simulation of VLSI CMOS devices
A4. design of ultra-low noise electronic instrumentation
A5. early assessment of emerging technologies for VLSI logic circuits
A6. design of ultra-low power subthreshold CMOS analog circuits
A1. Reliability of VLSI CMOS devices
This research activity, developed in tight collaboration with the IMEC (Leuven) research center, aims to the physical
understanding of the main failure mechanisms observed in VLSI CMOS devices (time-dependent dielectric breakdown,
stress-induced leakage current, bias temperature instability, hot carrier) and to estimating the VLSI CMOS system
lifetime from accelerated tests on elementary CMOS devices. In addition to reliability studies on conventional CMOS
devices, we extended our investigation to CMOS devices with alternative materials (high-k dielectrics, metal gate,
strained silicon, germanium substrates) and architectures (FinFETs, multiple-gate structures).
In one of the pioneering works on the soft-breakdown in ultrathin oxide layers, we reported the main properties of this
failure mechanism [J2]. We have proposed a physically based model for the soft-breakdown in nMOSFET based on a
localized reduction of the energy barrier for electrons and holes [J22]. We have investigated the impact of the channel
hot carrier on the gate-oxide time to breakdown in short-channel nMOSFETs [C16, J18]. We have studied the correlation
between stress-induced leakage current and the HFO2 bulk trap density [C20]. We reported how the positive-bias
temperature instability in nMOSFETs with HfSiON gate dielectrics can pose a severe constraint to the lifetime for CMOS
applications in the case of Hafnium-rich layers [J25]. It has been shown that in most cases, strain engineering, when
properly characterized and implemented has only a marginal impact on the oxide quality and does not compromise the
long-term reliability aspects [J30, J53, C35]. The reliability of multiple-gate FET nanodevices has been thoroughly
investigated [J34, C37, J63]. In particular, it has been reported that fin width scaling causes a higher hot carrier
degradation in nFinFETs owing to the higher charge carrier temperature [J63]. An optimization study of hot carrier
reliability in germanium-on-silicon pMOSFETs has been presented [J57]. It has been reported that forward body bias in
nMOSFETs improves the lifetime associated with channel hot carrier stress, while it does not alter the time dependent
dielectric breakdown process [J43].
A2. Electrical characterization techniques for VLSI CMOS devices
Electrical characterization of CMOS devices presents great challenges due to the continuous reduction of the device
dimensions and the introduction of new materials and architectures in the CMOS process.
A technique for extracting the MOSFET threshold voltage based on the measurement of the channel thermal noise
has been developed [J24]. We proposed a methodology for sensing the breakdown location along the MOSFET channel
length [J26]. We presented a procedure to extract the energy profile of the dielectric trap density from 1/ f noise
measurements of the tunneling current through metal-oxide-semiconductor structures [J61]. We proposed a technique to
extract doping profiles along the height of the fin in FinFET devices from ID-VG measurements as a function of the back
gate voltages [J63].
A3. Modeling and simulation of VLSI CMOS devices
Analytical modeling and numerical simulations are fundamental to the design of CMOS nanodevices with alternative
materials and architectures.
We have developed a trap-assisted tunneling model for the stress-induced leakage currents able to reproduce their
DC and noise properties [J8, J9, J19, J23]. In particular, the proposed model is able to explain the observed reduction of
the shot noise component. An analytical model for the 1/f noise of the tunneling current through metal-oxidesemiconductor structures has been proposed [J61]. It ascribes the observed gate current 1/ f noise to the
superimposition of random telegraph signals due to elastic electron tunneling from the inversion layer to oxide traps and
vice versa.
By comparing electrical characterization and detailed quantum simulations of the capacitance–voltage and current–
voltage characteristics, we have obtained information on the nature of localized states (energy and capture cross
section) in the Hafnium based dielectrics responsible for the degradation of the device performance and reliability [J37].
A4. Design of ultra-low noise electronic instrumentation
The commercial noise instrumentation is often inadequate for the noise characterization of advanced nanodevices
and therefore it is mandatory to design dedicated electronic instrumentation with improved noise performance.
Several high-sensitivity instruments for the measurement of the voltage noise [J32, J35, J55] and of the current noise
[J28, J60] have been proposed and validated through experimental measurements. These circuit configurations allow the
suppression of the background noise of the measurement system without the a-priori knowledge of the device under test
impedance. Moreover, we developed a noise model for operational amplifiers [J56]. General issues regarding the low
noise design have been faced with particular regard to the characterization of CMOS devices and non-volatile memories
[C28, J48]. The self-developed high-sensitivity instrumentation allowed also the study of the transients in the
programming currents of nano-crystal memories, revealing single electron jumps [J27, J48]. A procedure to separate the
RTS component from the background flicker noise has been reported [J49]. This a very important result because in
practical cases, the background flicker noise can be masked from the RTS component in ultra-scaled devices. We have
proposed a new topology for a transimpedance amplifier with an improved trade-off between noise and bandwidth [J31,
J45]. We have designed a very low-noise, high accuracy programmable voltage reference that is intended as an
alternative to batteries for the realization of automated low-frequency noise measurement systems [J20].
A5. Early assessment of emerging technologies for VLSI logic circuits
We proposed a novel methodology that aims at filling the gap between device measurements and circuit level
analysis. More specifically, appropriate figures of merit have been introduced to express VLSI circuit- and system-level
features as a function of proper parameters, which in turn are evaluated from experimental measurements. This permits
to perform an early assessment of the technology that provides useful information well before having a complete design
kit.
This methodology has been applied to Ge and SiGe pMOSFETs for VLSI logic circuits. The comparative analysis
between Ge and Si devices showed how the drawback of higher off state drain current in Ge devices can be alleviated
by the application of back biasing and stack effect techniques which are intrinsically more effective in Ge devices [C44,
J72]. The comparative analysis between SiGe and Si devices showed that the SiGe technology has more efficient
leakage-delay and dynamic energy-delay trade offs at nominal supply [C48, C52]. These advantages of SiGe VLSI
circuits are further emphasized at low voltages due to the greater SiGe mobility enhancement at low longitudinal fields.
This demonstrates that SiGe VLSI circuits benefit from aggressive voltage scaling significantly more than Si circuits
A6. Design of ultra-low power subthreshold CMOS analog circuits
Subthreshold CMOS circuits are becoming increasingly popular in low-power low-voltage design. Thanks to the
power savings offered, they are particularly attractive in portable scenarios, such as wearable medical devices or passive
RFIDs, where energy optimization is of utmost importance.
We have proposed a subthreshold-operated voltage reference circuit fabricated in UMC 0.18-mm CMOS process
[J73]. The proposed solution represents a significant advance in low power low voltage reference circuit design: the
power dissipation is only 2.6 nW, which is about one order of magnitude lower than that of best results found in literature,
and the minimum supply voltage for correct operation falls to 0.45V. In addition, we have presented and demonstrated a
temperature compensation technique and a simple model for line sensitivity prediction in subthreshold-operated voltage
reference circuits.
PUBLICATIONS
Journals: 98 (1 INVITED, 1 REVIEW)
Ø IEEE Transactions on Electron Devices: 16
Ø IEEE Electron Device Letters: 10
Ø Microelectronic Engineering: 10
Ø Applied Physics Letters: 9
Ø IEEE Transactions on Instrumentation and Measurement: 7
Ø Microelectronics Reliability: 6
Ø Journal of Applied Physics: 5
Ø International Journal of Circuit Theory and Applications: 5
Ø Review of Scientific Instruments: 4
Ø IEEE Transactions on Device and Materials Reliability: 3 (1 INVITED)
Ø IEEE Transactions on VLSI Systems: 3
Ø Solid-State Electronics: 3 (1 REVIEW)
Ø Fluctuation and Noise Letters: 3
Ø IEEE Journal of Solid-State Circuits: 1
Ø IEEE Transactions on Circuits and Systems I: 1
Ø IEEE Transactions on Circuits and Systems II: 1
Ø IEEE Transactions on Nanotechnology: 1
Ø IEEE Journal of Photovoltaics: 1
Ø IEEE Jurnal of Electron Devices Society: 1
Ø IEEE Transactions on Nuclear Science: 1
Ø Journal of Nanoscience and Nanotechnology: 1
Ø Journal of Vacuum Science and Technology B: 1
Ø Semiconductor Science and Technology: 1
Ø Japanese Journal of Applied Physics: 1
Ø Materials Science in Semiconductor Processing: 1
Ø Microwave and Optical Technology Letters: 1
Ø Solid State Technology: 1
Conferences: 68 (12 INVITED, 1 BEST PAPER)
Ø IEEE Instrumentation and Measurement Technology Conference (IMTC): 10
Ø IEEE International Reliability Physics Symposium Proceedings (IRPS): 9 (1 INVITED)
Ø Meeting of The Electrochemical Society (ECS): 6 (4 INVITED)
Ø European Solid-State Device Research Conference (ESSDERC): 5
Ø International Electron Devices Meeting Technical Digest (IEDM): 3 (1 INVITED)
Ø International Conference on Solid-State and Integrated-Circuit Technology (ICSICT): 3 (3 INVITED)
Ø International Conference on Silicon Photovoltaics , Energy Procedia (SiliconPV): 3
Ø European Conference on ULtimate Integration of Silicon (ULIS): 3
Ø IEEE Semiconductor Interface Specialists Conference (SISC): 3
Ø IEEE International Symposium on Circuits and Systems (ISCAS): 2
Ø International Conference on Solid State Devices and Materials (SSDM): 2 (1 INVITED)
Ø Conference on Insulating Films on Semiconductors (INFOS): 2
Ø International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA): 2
Ø Workshop on Dielectrics in Microelectronics (WODIM): 2
Ø Symposium on VLSI Technology Digest of Technical Papers (VLSI): 1
Ø International Semiconductor Technology Conference/China Semiconductor Technology International
Conference (ISTC/CSTIC): 1
Ø China Semiconductor Technology International Conference (CSTIC): 1
Ø International Conference on IC Design and Technology (ICICDT): 1 (INVITED)
Ø Device Research Conference (DRC): 1
Ø IEEE International Conference on Microelectronics (MIEL): 1 (BEST PAPER)
Ø International Conference on Noise and Fluctuations (ICNF): 1 (1 INVITED)
Ø International Workshop on Electron Devices and Semiconductor Technology (IEDST): 1
Ø International Conference on Unsolved Problems of Noise (UPoN): 1
Ø International Conference on Atomic Layer Deposition (ALD): 1
Ø EUROMICRO Conference (EUROMICRO): 1
Ø IMEKO Conference (IMEKO): 1
Ø Italian Conference on Photonics Technologies, Fotonica AEIT (Fotonica AEIT): 1
National Patents: 1
Citation count: 1070 (from ISI Web of Science), 1340 (from Scopus), 1720 (from Google Scholar)
h-index: 18 (from ISI Web of Science), 20 (from Scopus), 23 (from Google Scholar)
JOURNALS
[98] D. Albano, M. Lanuzza, R. Taco, F. Crupi, “Gate-level body biasing for subthreshold logic circuits: analytical modeling
and design guidelines”, to be published in International Journal of Circuit Theory and Applications
[97] D. Albano, F. Crupi, F. Cucchi, G. Iannaccone, “A Sub-kT/q Voltage Reference Operating at 150 mV” , to be published
in IEEE Transactions on VLSI Systems
[96] L. Magnelli, F. Crupi, P. Corsonello, G. Iannaccone, “A sub-1V nanopower temperature compensated subthreshold
CMOS voltage reference with 0.065 %/V line sensitivity”, to be published in International Journal of Circuit Theory and
Applications
[95] S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi, S. Richter, Q.T. Zao, S. Mantl, “Impact of TFET unidirectionality
and ambipolarity on the performance of 6T SRAM cells”, to be published in IEEE Journal of the Electron Devices Society
[94] D. Albano, F. Crupi, F. Cucchi, G. Iannaccone, “A picopower temperature-compensated, subthreshold CMOS voltage
reference”, International Journal of Circuit Theory and Applications, vol. 42, n. 12, pp. 1306-1318, 2014
[93] L.M. Procel, F. Crupi, J. Franco, L. Trojman, B. Kaczer, “Defect-Centric Distribution of Channel Hot Carrier Degradation
in Nano-MOSFETs”, IEEE Electron Device Letters, vol. 35, n. 12, pp. 1167-1169, 2014
[92] E. Simoen, A. Federico, M. Aoulaiche, R. Ritzenthaler, T. Schram, H. Arimura, M. Cho, T. Kauerauf, G. Groeseneken, N.
Horiguchi, A. Thean, F. Crupi, A. Spessot, C. Caillat, P. Fazan, H.-J. Na, Y. Son, K.B. Noh, “Low-frequency noise
assessment of border traps in Al2O3 capped DRAM peripheral MOSFETs”, Semiconductor Science and Technology, vol. 29,
n. 11, 115015, 2014
[91] L. Magnelli, F.A. Amoroso, F. Crupi, G. Cappuccino, G. Iannaccone, “Design of a 75 nW, 0.5 V Subthreshold CMOS
Operational Amplifier”, International Journal of Circuit Theory and Applications, vol. 2, n. 9, pp. 967-977, 2014
[90] M. Scarpino, S. Gupta, D. Lin, A. Alian, F. Crupi, N. Collaert, A. Thean, E. Simoen, “Border Traps in InGaAs nMOSFETs
Assessed by Low-Frequency Noise”, IEEE Electron Device Letters, vol. 35, n. 7, pp. 720-722, 2014
[89] A.N. Tallarico, M. Cho, J. Franco, R. Ritzenthaler, M. Togo, N. Horiguchi, G. Groeseneken, F. Crupi, “Impact of the
Substrate Orientation on CHC Reliability in n-FinFETs – Separation of the Various Contributions”, IEEE Transactions on
Device and Materials Reliability, vol. 14, n. 1, pp. 52-56, 2014
[88] P. Magnone, D. Tonini, R. De Rose, M. Frei, F. Crupi, E. Sangiorgi, C. Fiegna, “Numerical Simulation and Modeling of
Resistive and Recombination Losses in MWT Solar Cells”, IEEE Journal of Photovoltaics, vol. 3, n. 4, pp. 1215-1221, 2013
[87] V. Maccaronio, F. Crupi, L.M. Procel, L. Goux , E. Simoen, L. Trojman, "Low-frequency noise behaviour of the
conductive filament in bipolar HfO2-based resistive Random Access Memory", Microelectronic Engineering, vol. 107, pp. 1-5,
2013
[86] L.M. Procel, L. Trojman, J. Moreno, V. Maccaronio, F. Crupi, R. Degraeve, L. Goux, E. Simoen, “Experimental evidence
of the quantum point contact theory in the conduction mechanism of bipolar HfO2-based resistive random access memories”,
Journal of Applied Physics, vol. 114, 074509, 2013
[85] E. Simoen, T. Romeo, L. Pantisano, A. Luque Rodríguez, J.A. Jiménez Tejada, M. Aoulaiche, A. Veloso, M. Jurczak, R.
Krom, J. Mitard, Ch. Caillat, P. Fazan, F. Crupi, C. Claeys, “Insights into low frequency noise in high-mobility transistors”,
Solid State Technology, vol. 56, n. 2, pp. 25-28, 2013
[84] F. Crupi, D. Albano, M. Alioto, J. Franco, L. Selmi, J. Mitard, G. Groeseneken, “Impact of High-Mobility Materials on the
Performance of Near- and Sub-Threshold CMOS Logic Circuits”, IEEE Transactions on Electron Devices, vol. 60, n. 3, pp.
972-977, 2013
[83] R. De Rose, A. Malomo, P. Magnone, F. Crupi, G. Cellere, M. Martire, D. Tonini, E. Sangiorgi, “A Methodology to
Account for the Finger Interruptions in Solar Cell Performance”, Microelectronics Reliability, special issue devoted to
ESREF2012, vol. 52, pp. 2500-2503, 2012
[82] J. Franco, S. Graziano, B. Kaczer, F. Crupi, L.-Å Ragnarsson, T. Grasser, G. Groeseneken, “BTI Reliability of Ultra-Thin
EOT MOSFETs for Sub-Threshold Logic”, Microelectronics Reliability, special issue devoted to ESREF2012, vol. 52, pp.
1932-1935, 2012
[81] P. Magnone, F. Crupi, N. Wils, H. Tuinhout, C. Fiegna, “Characterization and Modeling of Hot Carrier Induced Variability
in Subthreshold Region”, IEEE Transactions on Electron Devices, vol. 59, n. 8, pp. 2093-2099, 2012
[80] F. Crupi, M. Alioto, J. Franco, P. Magnone, M. Togo, N. Horiguchi, G. Groeseneken, “Understanding the Basic
Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic from Device Measurements”, IEEE Transactions on Circuits
and Systems II, vol. 59, n. 7, pp. 439-442, 2012
[79] É. O’Connor, K. Cherkaoui, S. Monaghan, D. O'Connell, I.M. Povey, P. Casey, S.B. Newcomb, Y.Y. Gomeniuk, G.
Provenzano, F. Crupi, G. Hughes , P.K. Hurley, “Observation of peripheral charge induced low frequency CV behaviour in
metal-oxide-semiconductor capacitors on Si and GaAs substrates”, Journal of Applied Physics, vol. 111, 124104, 2012
[78] F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T.Y. Hoffmann, “Buried
Silicon-Germanium pMOSFETs: Experimental Analysis in VLSI Circuits under Aggressive Voltage Scaling”, IEEE
Transactions on VLSI Systems vol. 20, n. 8, pp. 1487-1495, 2012
[77] G. Giusi, G. Iannaccone, F. Crupi, “A microscopically accurate model of partially ballistic nanoMOSFETs in saturation
based on channel backscattering”, IEEE Transactions on Electron Devices, vol. 58, n. 3, pp. 691-697, 2011
[76] P. Magnone, F. Crupi, N. Wils, R. Jain, H. Tuinhout, P. Andricciola, G. Giusi, C. Fiegna, “Impact of Hot Carriers on
nMOSFET Variability in 45 nm and 65 nm CMOS Technologies”, IEEE Transactions on Electron Devices, vol. 58, n. 8, pp.
2347-2353, 2011
[75] G. Giusi, G. Iannaccone, F. Crupi, U. Ravaioli, “A Backscattering Model Incorporating the Effective Carrier Temperature
in Nano MOSFET”, IEEE Electron Device Letters, vol. 32, n. 7, pp. 853-855, 2011
[74] P. Magnone, F. Crupi, M. Alioto, B. Kaczer, B. De Jaeger, “Understanding the Potential and the Limits of Germanium
pMOSFETs for VLSI Circuits from Experimental Measurements”, IEEE Transactions on VLSI Systems, vol. 19, n. 9, pp.
1569-1582, 2011
[73] L. Magnelli, F. Crupi, P. Corsonello, C. Pace, G. Iannaccone, “A 2.6 nW, 0.45 V Temperature Compensated
Subthreshold CMOS Voltage Reference”, IEEE Journal of Solid State Circuits, vol. 46, n. 2, pp. 465-474, 2011
[72] S. Monaghan, A. O’Mahony, K. Cherkaoui, É. O’Connor, I.M. Povey, M.G. Nolan, D. O’Connell, M.E. Pemble, P.K.
Hurley, G. Provenzano, F. Crupi, S.B. Newcomb, “Electrical analysis of three-stage passivated In0.53Ga0.47As capacitors with
varying HfO2 thicknesses and incorporating an Al2O3 interface control layer”, Journal of Vacuum Science and Technology B,
special issue devoted to WODIM2010, vol. 29, n. 1, pp. 01A807-01A807-8, 2011
[71] G. Giusi, F. Crupi, P. Magnone, “Criticisms on and Comparison of Experimental Channel Backscattering Extraction
Methods”, Microelectronic Engineering, vol. 88, pp. 76-81, 2011
[70] P. Magnone, F. Crupi, A. Mercha, P. Andricciola, H. Tuinhout, R. J. P. Lander, “FinFET mismatch in subthreshold
region: theory and experiments”, IEEE Transactions on Electron Devices, vol. 57, n. 11, pp. 2848-2856, 2010
[69] A. O’Mahony, S. Monaghan, G. Provenzano, I.M. Povey, M.G. Nolan, É. O’Connor, K. Cherkaoui, S.B. Newcomb, F.
Crupi, P.K. Hurley, M.E. Pemble, “Structural and electrical analysis of the atomic layer deposition of HfO2/n-In0.53Ga0.47As
capacitors with and without an Al2O3 interface control layer”, Applied Physics Letters, vol. 97, 052904, 2010
[68] C. Gerardi, E. Tripiciano, G. Cinà, S. Lombardo, C. Garozzo, D. Corso, G. Betrò, C. Pace, F. Crupi, “Multiple gate NVM
cells with improved Fowler-Nordheim tunneling program and erase performances”, Solid-State Electronics, vol. 54, pp. 13191325, 2010
[67] G. Giusi, F. Crupi, C. Pace, C. Ciofi, P. Magnone, “Instrumentation design for cross-correlation measurements between
gate and drain low frequency noise in MOSFETS”, Fluctuation and Noise Letters, vol. 9, n. 3, pp. 313-322, 2010
[66] G. Giusi, G. Iannaccone, D. Maji, F. Crupi, “Barrier Lowering and Backscattering Extraction in Short-Channel
MOSFETs”, IEEE Transactions on Electron Devices, vol. 57, n. 9, pp. 2132-2137, 2010
[65] G. Giusi, M.A. Alam, F. Crupi, S. Pierro, “Bipolar Mode Operation and Scalability of Double Gate Capacitorless 1TDRAM Cells”, IEEE Transactions on Electron Devices, vol. 57, n. 8, pp. 1743-1750, 2010
[64] M. Lisiansky, G. Cassuto, Y. Roizin, D. Corso, S. Libertino, A. Marino, S. Lombardo, I. Crupi, C. Pace, F. Crupi, D. Fuks,
A. Kiv, E. Della Sala, G. Capuano, F. Palumbo, “Radiation Tolerance of NROM embedded products”, IEEE Transactions on
Nuclear Science, vol. 57, n. 4, pp. 2309-2317, 2010
[63] S. Chabukswar, D. Maji, C.R. Manoj, K.G. Anil, V.R. Rao, F. Crupi, P. Magnone, G. Giusi, C.Pace, N. Collaert,
“Implications of Fin Width Scaling on Variability and Reliability of High-k Metal Gate FinFETs”, Microelectronic Engineering,
vol. 87, pp. 1963-1967, 2010
[62] P. Magnone, A. Mercha, V. Subramanian, P. Parvais, N. Collaert, M. Dehan, S. Decoutere, G. Groeseneken, J. Benson,
T. Merelle, R. Lander, F. Crupi, C. Pace, “Matching performance of finFET devices with fin widths down to 10nm”, IEEE
Electron Device Letters, vol. 30, n. 12, pp. 1374-1376, 2009
[61] F. Crupi, G. Giusi, G. Iannaccone, P. Magnone, C. Pace, E. Simoen, C. Claeys, “Analytical model for the 1/f noise in the
tunneling current through metal-oxide-semiconductor structures”, Journal of Applied Physics, vol. 106, 073710, 2009
[60] G. Giusi, C. Pace, F. Crupi, “Cross-correlation based trans-impedance amplifier for current noise measurements”,
International Journal of Circuit Theory and Applications, vol. 37, n. 6, pp. 781-792, 2009
[59] P. Magnone, F. Crupi, G. Giusi, C. Pace, E. Simoen, C. Claeys, L. Pantisano, D. Maji, V.R. Rao, P. Srinivasan, “1/f
noise in drain and gate current of MOSFETs with high-k gate stacks”, IEEE Transactions on Device and Materials Reliability,
vol. 9, n. 2, pp. 180-189, 2009 (INVITED)
[58] E. Simoen, F. De Stefano, G. Eneman, B. De Jaeger, C. Claeys, F. Crupi, “On the temperature and field dependence of
trap-assisted-tunneling current in Ge p+n junctions”, IEEE Electron Device Letters, vol. 30, n. 5, pp. 562-564, 2009
[57] D. Maji, F. Crupi, E. Amat, E. Simoen, B. De Jaeger, D.P. Brunco, C.R. Manoj, V.R. Rao, P. Magnone, G. Giusi, C.
Pace, L. Pantisano, J. Mitard, R. Rodriguez, M. Nafrìa, “Understanding and Optimization of Hot Carrier Reliability in
Germanium-on-Silicon pMOSFETs”, IEEE Transactions on Electron Devices, vol. 56, n. 5, pp. 1063-1069, 2009
[56] G. Giusi, F. Crupi, C. Pace, P. Magnone, “Full model and characterization of noise in operational amplifier”, IEEE
Transactions on Circuits and Systems I, vol. 56, n. 1, pp. 97-102, 2009
[55] G. Giusi, F. Crupi, C. Pace, “Ultra sensitive low noise voltage amplifier for spectral analysis”, Review of Scientific
Instruments, vol. 79, 084701, 2008
[54] P. Magnone, L. Pantisano, F. Crupi, L. Trojman, C. Pace, G. Giusi, “On the impact of defects close to the gate electrode
on the low frequency 1/f noise”, IEEE Electron Device Letters, vol. 29, n. 9, pp. 1056-1058, 2008
[53] C. Claeys, E. Simoen, S. Put, G. Giusi, F. Crupi, “Impact strain engineering on gate stack quality and reliability”, SolidState Electronis, Review Article, vol. 52, pp. 1115-1126, 2008
[52] P. Magnone, V. Subramanian, B. Parvais, A. Mercha, C. Pace, M. Dehan, S. Decoutere, G. Groeseneken, F. Crupi, S.
Pierro, “Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices”,
Microelectronic Engineering, vol. 85, pp. 1728-1731, 2008
[51] E. Miranda, P. Falbo, M. Nafría, F. Crupi, “Analysis of the progressive breakdown current in HfSiON gate stacks”,
Applied Physics Letters, vol. 92, 253505, 2008
[50] D. Maji, F. Crupi, G. Giusi, C. Pace, E. Simoen, C. Claeys, V.R. Rao, “DC and Noise Properties of Gate Current in epiGe pMOSFETs with TiN/TaN/HfO2/SiO2 Gate Stack”, Applied Physics Letters, vol. 92, 163508, 2008
[49] G. Giusi, F. Crupi, C. Pace, “An algorithm for separating multi-level random telegraph signal from 1/f noise”, Review of
Scientific Instruments, vol. 79, 024701, 2008
[48] C. Pace, G. Giusi, F. Crupi, S. Lombardo, “Detection and classification of single-electron jumps in Si nanocrystal
memories”, IEEE Transactions on Instrumentation and Measurement, vol. 57, n. 2, pp. 364-368, 2008
[47] F. Crupi, P. Magnone, A. Pugliese, G. Cappuccino, “Performance of current mirror with high-k gate dielectrics”,
Microelectronic Engineering, vol. 85, pp. 284-288, 2008
[46] P. Magnone, C. Pace, F. Crupi, G. Giusi, “Low frequency noise in nMOSFETs with subnanometer EOT Hafnium-based
gate dielectrics”, Microelectronics Reliability, vol. 47, pp. 2109-2113, 2007
[45] C. Ciofi, F. Crupi, C. Pace, G. Scandurra, M. Patanè, “A new circuit topology for the realization of very low noise, wide
bandwidth transimpedance amplifier”, IEEE Transactions on Instrumentation and Measurement, vol. 56, n. 5, pp. 1626-1631,
2007
[44] L. Aguilera, J. Martín-Martínez, M. Porti, R. Rodríguez, M. Cambrea, F. Crupi, M. Nafría, X. Aymerich, “Comparison of
stressed Poly-Si and TiN gated Hf-based NMOSFETs characteristics, modeling and their impact on circuits performance”,
Microelectronic Engineering, special issue devoted to INFOS2007, vol. 84, pp. 2113-2116, 2007
[43] F. Crupi, L. Magnelli, P. Falbo, M. Lanuzza, M. Nafría, R. Rodríguez, “Performance and reliability of ultra-thin oxide
nMOSFETs under variable body bias”, Microelectronic Engineering, special issue devoted to INFOS2007, vol. 84, pp. 19471950, 2007
[42] G. Cappuccino, F. Crupi, A. Pugliese, “Impact of the variable output resistance on the transient response of LC
transmission line CMOS buffers and its model”, Microwave and Optical Technology Letters, vol. 49, n. 7, pp. 1504-1509,
2007
[41] P. Srinivasan, F. Crupi, P. Magnone, E. Simoen, C. Pace, D. Misra, C. Claeys, “Impact of the interfacial layer on the
low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks”, Microelectronics Reliability, special issue
devoted to WODIM2006, vol. 47, pp. 501-504, 2007
[40] P. Magnone, F. Crupi, L. Pantisano, C. Pace, “Fermi-level pinning at polysilicon-HfO2 interface as a source of drain and
gate current 1/f noise”, Applied Physics Letters, vol. 90, 073507, 2007
[39] D. Corso, C. Pace, F. Crupi, S. Lombardo, “Single electron program/erase tunnel events in nanocrystal memories”,
IEEE Transactions on Nanotechnology, vol. 6, n. 1, pp. 35-42, 2007
[38] C. Pace, F. Crupi, D. Corso, S. Lombardo, “Experimental study of single-electron phenomena in silicon nanocrystal
memories”, Journal of Nanoscience and Nanotechnology vol. 7, n. 1, pp. 322-328, 2007
[37] A. Campera, G. Iannaccone, F. Crupi, “Modeling of tunnelling currents in Hf-based gate stacks as a function of
temperature and extraction of material parameters”, IEEE Transactions on Electron Devices, vol. 54, n. 1, pp. 83-89, 2007
[36] G. Giusi, F. Crupi, E. Simoen, G. Eneman, M. Jurczak, “Performance and reliability of strained-silicon nMOSFETs with
SiN cap layer”, IEEE Transactions on Electron Devices, vol. 54, n. 1, pp. 78-82, 2007
[35] G. Giusi, F. Crupi, C. Ciofi, C. Pace, “Three-channel amplifier for high-sensitivity voltage noise measurements”, Review
of Scientific Instruments, vol. 77, 095104, 2006
[34] F. Crupi, B. Kaczer, R. Degraeve, V. Subramanian, P. Srinivasan, E. Simoen, A. Dixit, M. Jurczak, G. Groeseneken,
“Reliability comparison of triple-gate versus planar SOI FETs”, IEEE Transactions on Electron Devices, vol. 53, n. 9, pp.
2351-2357, 2006
[33] F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, C. Claeys, “Impact of the interfacial layer on lowfrequency noise (1/f) behavior of MOSFETs with advanced gate stacks”, IEEE Electron Device Letters, vol. 27, n. 8, pp. 688692, 2006
[32] F. Crupi, G. Giusi, C. Ciofi, C. Pace, “Enhanced sensitivity cross-correlation method for voltage noise measurements”,
IEEE Transactions on Instrumentation and Measurement, vol. 55, n. 4, pp. 1143-1147, 2006
[31] C. Ciofi, F. Crupi, C. Pace, G. Scandurra, “How to enlarge the bandwidth without increasing the noise in op-amp based
transimpedance amplifier”, IEEE Transactions on Instrumentation and Measurement, vol. 55, n. 3, pp. 814-819, 2006
[30] G. Giusi, E. Simoen, G. Eneman, P. Verheyen, F. Crupi, K. De Meyer, C. Claeys, C. Ciofi, “Low-frequency (1/f) noise
behavior of locally stressed HfO2/TiN gate stack p-MOSFETs”, IEEE Electron Device Letters, vol. 27, n. 6, pp. 508-510, 2006
[29] G. Giusi, F. Crupi, C. Pace, C. Ciofi, G. Groeseneken, “Comparative Study of Drain and Gate Low-Frequency Noise in
nMOSFETs with Hafnium-Based Gate Dielectrics”, IEEE Transactions on Electron Devices, vol. 53, n. 4, pp. 823-828, 2006
[28] G. Giusi, F. Crupi, C. Ciofi, C. Pace, “Ultra sensitive method for current noise measurements”, Review of Scientific
Instruments, vol. 77, 015107, 2006
[27] C. Pace, F. Crupi, S. Lombardo, C. Gerardi, G. Cocorullo, “Room-temperature single-electron effects in Si nanocrystal
memories”, Applied Physics Letters, vol. 87, 182106, 2005, also selected for the November 7, 2005 issue of Virtual Journal
of Nanoscale Science & Technology
[26] F. Crupi, T. Kauerauf, R. Degraeve, L. Pantisano, G. Groeseneken, “A Novel Methodology for Sensing the Breakdown
Location and its Application to the Reliability Study of Ultra-Thin Hf-Silicate Gate Dielectrics”, IEEE Transactions on Electron
Devices, vol. 52, n. 8, pp. 1759-1765, 2005
[25] F. Crupi, C. Pace, G. Cocorullo, G. Groeseneken, M. Aoulaiche, M. Houssa, “Positive Bias Temperature Instability in
nMOSFETs with ultra-thin Hf-silicate gate dielectrics”, Microelectronic Engineering, special issue devoted to INFOS2005, vol.
80, pp. 130-133, 2005
[24] G. Giusi, N. Donato, C. Ciofi, F. Crupi, “A new technique for extracting the MOSFET threshold voltage using noise
measurements”, Fluctuation and Noise Letters, vol. 4, n. 2, pp. 643-649, 2004
[23] A. Nannipieri, G. Iannaccone, F. Crupi, “Extraction of the trap distribution responsible for SILCs in MOS structures from
measurements and simulations of DC and noise properties”, Microelectronics Realibility, special issue devoted to
ESREF2004, vol. 44, pp. 1497-1501, 2004
[22] B. Kaczer , A. De Keersgieter , R. Degraeve, F. Crupi, G. Groeseneken, “Modeling pFET currents after soft breakdown
at different gate locations”, Microelectronic Engineering, special issue devoted to INFOS2003, vol. 72, n. 1-4, pp. 125-129,
2004
[21] C. Ciofi, F. Crupi, C. Pace, G. Scandurra, “Micro-Prober for Wafer-Level Low-Noise Measurements in MOS Devices”,
IEEE Transactions on Instrumentation and Measurement, vol. 52, n.5, pp. 1533-1536, 2003
[20] C. Pace, C. Ciofi, F. Crupi, “Very Low Noise, High Accuracy, Programmable Voltage Reference”, IEEE Transactions on
Instrumentation and Measurement, vol. 52, n. 4, pp. 1251-1254, 2003
[19] G. Iannaccone, F. Crupi, B. Neri, S. Lombardo, “Theory and Experiment of Suppressed Shot Noise in Stress-Induced
Leakage Currents”, IEEE Transactions on Electron Devices , vol. 50, n. 5, pp. 1363-1369, 2003
[18] F. Crupi, B. Kaczer, G. Groeseneken, A. De Keersgieter, “New Insights Into the Relation Between Channel Hot Carrier
Degradation and Oxide Breakdown in Short Channel nMOSFETs”, IEEE Electron Device Letters, vol. 24, n. 4, pp. 278-280,
2003
[17] F. Crupi, B. Kaczer, R. Degraeve, A. De Keersgieter, G. Groeseneken, “A Comparative Study of the Oxide Breakdown
in Short Channel n- and p-MOSFETs Stressed in Inversion and in Accumulation Regimes”, IEEE Transactions on Device
and Materials Reliability, vol. 3, n. 1, pp. 8-13, 2003
[16] F. Crupi, G. Iannaccone, C. Ciofi, B. Neri, S. Lombardo, C. Pace, “Low frequency current noise in unstressed/stressed
thin oxide metal-oxide-semiconductor capacitors”, Solid-State Electronics, vol. 46, n. 11, pp. 1807-1813, 2002
[15] C. Ciofi, F. Crupi, C. Pace, “A New Method for High Sensitivity Noise Measurements”, IEEE Transactions on
Instrumentation and Measurement, vol. 51, n. 4, pp. 656-659, 2002
[14] F. Crupi, C. Ciofi, A. Germanò, G. Iannaccone, J.H. Stathis, S. Lombardo, “On the role of interface states in low voltage
leakage currents of metal-oxide-semiconductor structures”, Applied Physics Letters, vol. 80, n. 24, pp. 4597-4599, 2002
[13] F. Crupi, C. Ciofi, G. Iannaccone, B. Neri, S. Lombardo, “Current noise at the oxide hard-breakdown”, Microelectronic
Engineering, special issue devoted to INFOS2001, vol. 59, pp. 43-47, 2001
[12] S. Lombardo, A. La Magna, I. Crupi, C. Gerardi, F. Crupi, “Reduction of thermal damage in ultra-thin gate oxides after
intrinsic dielectric breakdown”, Applied Physics Letters, vol. 79, n. 10, pp. 1522-1524, 2001
[11] F. Crupi, C. Ciofi, C. Pace, G. Iannaccone, B. Neri, “Noise as a probe of the charge transport mechanisms through thin
oxides in MOS structures”, Fluctuation and Noise Letters, vol. 1, n. 2, pp. 61-64, 2001
[10] F. Crupi, G. Iannaccone, I. Crupi, R. Degraeve, G. Groeseneken, H.E. Maes, “Characterization of Soft Breakdown in
Thin Oxide nMOSFETs Based on the Analysis of the Substrate Current”, IEEE Transactions on Electron Devices, vol. 48, n.
6, pp. 1109-1113, 2001
[9] G. Iannaccone, F. Crupi, B. Neri, S. Lombardo, “Suppressed shot noise in trap-assisted tunneling of metal-oxidesemiconductor capacitors”, Applied Physics Letters, vol. 77, n. 18, pp. 2876-2878, 2000
[8] F. Crupi, G. Iannaccone, B. Neri, C. Ciofi, S. Lombardo, “Shot noise partial suppression in the SILC regime”,
Microelectronics Reliability, special issue devoted to ESREF2000, vol. 40, pp. 1605-1608, 2000
[7] F. Crupi, B. Neri, S. Lombardo, “Pre-Breakdown in Thin SiO2 Films”, IEEE Electron Device Letters, vol. 21, n. 6, pp. 319321, 2000
[6] S. Lombardo, F. Crupi, C. Spinella, B. Neri, “Transients during pre-breakdown and hard breakdown of thin gate oxides in
metal-SiO2-Si capacitors”, Materials Science in Semiconductor Processing, vol. 2, n.4, pp. 359-367, 1999
[5] S. Lombardo, A. La Magna, C. Spinella, C. Gerardi, F. Crupi, “Degradation and hard breakdown transient of thin gate
oxides in Metal-SiO2-Si capacitors: dependence on oxide thickness”, Journal of Applied Physics, vol. 86, n. 11, pp. 63826391, 1999
[4] S. Lombardo, A. La Magna, C. Gerardi, M. Alessandri, F. Crupi, “Soft breakdown of gate oxides in metal-SiO2-Si
capacitors under stress with hot electrons”, Applied Physics Letters, vol. 75, n. 8, pp. 1161-1163, 1999
[3] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, H.E. Maes, “Investigation and Comparison of the Noise in the Gate
and in the Substrate Current after Soft-Breakdown”, Japanese Journal of Applied Physics, vol. 38, n. 4B, pp. 2219-2222,
1999
[2] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, H.E. Maes, “On the Properties of the Gate and Substrate Current
after Soft Breakdown in Ultrathin Oxide Layers”, IEEE Transactions on Electron Devices, vol. 45, n. 11, pp. 2329-2334, 1998
[1] S. Lombardo, F. Crupi, A. La Magna, C. Spinella, A. Terrasi, A. La Mantia, B. Neri, “Electrical and thermal transient
during dielectric breakdown of thin oxides in metal-SiO2-silicon capacitors”, Journal of Applied Physics, vol. 84, n. 1, pp.472479, 1998
CONFERENCES
[68] B. Kaczer, J. Franco, M. Cho, T. Grasser, Ph.J. Roussel, S. Tyaginov, M. Bina, Y. Wimmer, L.M. Procel, L. Trojman, F.
Crupi, G. Pitner, V. Putcha, P. Weckx, E. Bury, Z. Ji, A. De Keersgieter, T. Chiarella, N. Horiguchi, G. Groeseneken, A.
Thean, “Origins and Implications of Increased Channel Hot Carrier Variability in nFinFETs” to be presented at IEEE
International Reliability Physics Symposium Proceedings, Monterey 2015
[67] S. Strangio, P. Magnone, F. Crupi, C. Fiegna, C. Pace, G. Iannaccone, A. Heiman, D. Shamir, “Toward understanding
of donor-traps-related dispersion phenomena on normally-ON AlGaN/GaN HEMT through transient simulations” to be
presented at European Conference on ULtimate Integration of Silicon, Bologna 2015
[66] S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi, “Analysis of TFET based 6T SRAM cells implemented with state
of the art silicon nanowires”, European Solid-State Device Research Conference, pp. 282-285, Venezia 2014
[65] P. Procel, V. Maccaronio, F. Crupi, G. Cocorullo, M. Zanuccoli, P. Magnone, C. Fiegna, “Analysis of the impact of
doping levels on performance of back contact - back junction solar cells”, International Conference on Crystalline Silicon
Photovoltaics, Energy Procedia, vol. 55, pp. 128-132, 's-Hertogenbosch 2014
[64] S. Strangio, P. Palestri, D. Esseni, L. Selmi, F. Crupi, “Performance analysis of different SRAM cell topologies
employing tunnel-FETs”, Device Research Conference, pp. 143-144, Santa Barbara 2014
[63] P. Procel, V. Maccaronio, F. Crupi, G. Cocorullo, M. Zanuccoli, “Analysis of the impact of rear side geometry on
performance of back-contact back-junction solar cells”, Italian Conference on Photonics Technologies, Fotonica AEIT, Napoli
2014
[62] M. Scarpino, D. Lin, A. Alian, C. Merckling, F. Crupi, N. Collaert, A. Thean, E. Simoen, C. Claeys, “Impact of pre- and
post-growth treatment on the low-frequency noise of InGaAs nMOSFETs”, China Semiconductor Technology International
Conference, vol. 60, n. 1, pp. 115-120, Shangai 2014
[61] M. Aoulaiche, E. Simoen, R. Ritzenthaler, T. Schram, H. Arimura, M. Cho, T. Kauerauf, G. Groeseneken, N. Horiguchi,
A. Thean, A. Federico, F. Crupi, A. Spessot, C. Caillat, P. Fazan, H.-J. Na, Y. Son, K.B. Noh, "Impact of Al2O3 position on
performances and reliability in high-k metal gated DRAM periphery transistors”, European Solid-State Device Research
Conference, pp. 190-193, Bucharest 2013
[60] P. Magnone, R. De Rose, C. Fiegna, E. Sangiorgi, F. Crupi, M. Lanuzza, M. Frei, D. Tonini, “A comparative study of
MWT artchitectures by means of numerical simulations”, International Conference on Crystalline Silicon Photovoltaics,
Energy Procedia, vol. 38, pp. 131-136, Hamelin 2013
[59] E. Simoen, T. Romeo, L. Pantisano, A. Luque Rodríguez, J.A. Jiménez Tejada, M. Aoulaiche, A. Veloso, M. Jurczak, R.
Krom, J. Mitard, Ch. Caillat, P. Fazan, F. Crupi, C. Claeys, “Insights in low frequency noise of advanced and high-mobility
channel transistors”, International Electron Devices Meeting Technical Digest, San Francisco 2012 (INVITED)
[58] F. Crupi, P. Magnone, M. Alioto, J. Franco, G. Groeseneken, “Early Assessment of Emerging Technologies for VLSI
Logic Circuits from Experimental Measurements”, International Conference on Solid-State and Integrated-Circuit Technology,
Xi’an 2012 (INVITED)
[57] C. Claeys, S. Iacovo, D. Kobayashi, A. Mercha, A. Griffoni, Ph. Roussel, F. Crupi, E. Simoen, “Wafer Level Statistical
Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology”, Meeting of
The Electrochemical Society, Honolulu 2012
[56] T. Romeo, L. Pantisano, E. Simoen, R. Krom, M. Togo, N. Horiguchi, J. Mitard, A. Thean, G. Groeseneken, C. Claeys,
F. Crupi, “Low-Frequency Noise Assessment of the Transport Mechanisms in SiGe Channel Bulk FinFETs”, European SolidState Device Research Conference, pp. 330-333, Bordeaux 2012
[55] J. Franco, B. Kaczer, J. Mitard, M. Toledano-Luque, G. Eneman, Ph. J. Roussel, M. Cho, T. Kauerauf, T. Grasser, F.
Crupi, L. Witters, G. Hellings, L.-Å Ragnarsson, N. Horiguchi, M. Heyns, G. Groeseneken, “Superior Reliability and Reduced
Time-Dependent Variability in High-Mobility SiGe Channel pMOSFETs for VLSI Logic Applications”, International Conference
on IC Design and Technology, 6232839, Austin 2012 (INVITED)
[54] P. Magnone, A. Napoletano, R. De Rose, F. Crupi, D. Tonini, G. Cellere, M. Galiazzo, E. Sangiorgi, C. Fiegna, “A
methodology to account for the finger non-uniformity in photovoltaic solar cell”, International Conference on Crystalline
Silicon Photovoltaics, Energy Procedia, vol. 27, pp. 191-196, Leuven 2012
[53] G. Eneman, G. Hellings, J. Mitard, L. Witters, S. Yamaguchi, M. Garcia Bardon, P. Christie, C. Ortolland, A. Hikavyy, P.
Favia, M. Bargallo Gonzalez, E. Simoen, F. Crupi, M. Kobayashi, J. Franco, S. Takeoka, R. Krom, H. Bender, R. Loo, C.
Claeys, K. De Meyer, T. Hoffmann, “Si1-xGex-Channel PFETs: Scalability, Layout Considerations and Compatibility with Other
Stress Techniques”, Meeting of The Electrochemical Society, vol. 35, n. 3, pp. 493-503, Montreal 2011 (INVITED)
[52] F. Crupi, M. Alioto, J. Franco, P. Magnone, B. Kaczer, G. Groeseneken, J. Mitard, L. Witters, T.Y. Hoffmann,
“Experimental Analysis of Buried SiGe pMOSFETs from the Perspective of Aggressive Voltage Scaling”, IEEE International
Symposium on Circuits and Systems, pp. 2249-2252, Rio de Janeiro 2011
[51] J. Franco, B. Kaczer, G. Eneman, Ph. J. Roussel, M. Cho, J. Mitard, L. Witters, T.Y. Hoffmann, G. Groeseneken, F.
Crupi, T. Grasser, “On the Recoverable and Permanent Components of Hot Carrier and NBTI in Si pMOSFETs and their
Implications in Si0.45Ge0.55 pMOSFETs”, IEEE International Reliability Physics Symposium Proceedings, pp. 624-629,
Monterey 2011
[50] A. O’Mahony, S. Monaghan, R. Chiodo, I.M. Povey, K. Cherkaoui, R.E. Nagle, É. O’Connor, R.D. Long, V. Djara, D.
O’Connell, F. Crupi, M.E. Pemble, P.K. Hurley, “Structural and Electrical Analysis of Thin Interface Control Layers of MgO or
Al2O3 Deposited by Atomic Layer Deposition and Incorporated at the high-k/III-V Interface of MO2/InxGa1-xAs (M = Hf|Zr, x =
0|0.53) Gate Stacks”, Meeting of The Electrochemical Society, vol. 33, n. 2, pp. 69-82, Las Vegas 2010
[49] G. Giusi, G. Iannaccone, D. Maji, F. Crupi, “Experimental Extraction of Barrier Lowering and Backscattering in Saturated
Short-Channel MOSFETs”, International Conference on Solid-State and Integrated-Circuit Technology, n. 5667354, pp.
1761-1764, Shangai 2010 (INVITED)
[48] J. Mitard, L. Witters, M. Garcia Bardon, P. Christie, J. Franco, A. Mercha, P. Magnone, M. Alioto, F. Crupi, L.-Å.
Ragnarsson, A. Hikavyy, B. Vincent, T. Chiarella, R. Loo, J. Tseng, S. Yamaguchi, S. Takeoka, W.-E. Wang, P. Absil, T.
Hoffmann, “Sub-nm EOT high-mobility SiGe-55% channel pFETs: delivering high performance at scaled VDD”, International
Electron Devices Meeting Technical Digest, pp. 249-252, San Francisco 2010
[47] J. Franco, B. Kaczer, J. Mitard, G. Eneman, Ph. J. Roussel, F. Crupi, T. Grasser, L. Witters, T.Y. Hoffmann, G.
Groeseneken, “Implications of Channel Hot Carrier Degradation in Si0.45Ge0.55 pMOSFETs”, IEEE Semiconductor Interface
Specialists Conference, San Diego 2010
[46] A. O’Mahony, S. Monaghan, R. Chiodo, I.M. Povey, A. Blake, K. Cherkaoui, É. O’Connor, R.E. Nagle, R.D. Long, V.
Djara, D. O’Connell, S.B. Newcomb, F. Crupi, P.K. Hurley, M.E. Pemble, “Electrical characterisation of Pd/HfO2 MOSCAPs
with/without a thin Al2O3 or MgO interface control layer deposited on GaAs or In0.53Ga0.47As/InP by ALD”, Workshop on
Dielectrics in Microelectronics, Bratislava 2010
[45] A. O’Mahony, S. Monaghan, R. Chiodo, I.M. Povey, A. Blake, R.E. Nagle, J.A. Hamilton, M.G. Nolan, K. Cherkaoui, V.
Djara, D. O’Connell, S.B. Newcomb, F. Crupi, P.K. Hurley, M.E. Pemble, “Electrical and structural characterisation of
Al2O3/HfO2, MgO/HfO2 and HfO2 layers deposited by ALD on GaAs and In0.53Ga0.47As”, International Conference on Atomic
Layer Deposition, Seoul 2010
[44] P. Magnone, F. Crupi, M. Alioto, B. Kaczer, “Experimental study of leakage-delay trade-off in Germanium pMOSFETs
for logic circuits”, IEEE International Symposium on Circuits and Systems, pp. 1609-1702, Paris 2010
[43] D. Maji, F. Crupi, P. Magnone, G. Giusi, C. Pace, E. Simoen, V.R. Rao, “Characterization of interface and oxide traps in
Ge pMOSFETs based on DCIV technique”, IEEE Proc. International Workshop on Electron Devices and Semiconductor
Technology, Bombay 2009
[42] F. Crupi, P. Magnone, E. Simoen, A. Mercha, L. Pantisano, G. Giusi, C. Pace, C. Claeys, “The role of the interfaces in
the 1/f noise of MOSFETs with high-k gate stacks”, Meeting of The Electrochemical Society, vol. 19, n. 2, pp. 87-99, San
Francisco 2009 (INVITED)
[41] E. Simoen, F. De Stefano, G. Eneman, B. De Jaeger, C. Claeys, F. Crupi, “pMOSFET off-state leakage and junction
leakage current in Ge-based devices”, International Semiconductor Technology Conference/China Semiconductor
Technology International Conference, vol. 18, n. 1, pp. 61-66, Shanghai 2009
[40] F. Crupi, P. Magnone, G. Iannaccone, G. Giusi, C. Pace, E. Simoen, C. Claeys, “Modeling the gate current 1/f noise and
its application to advanced CMOS devices”, International Conference on Solid-State and Integrated-Circuit Technology, pp.
420 423, Beijing 2008 (INVITED)
[39] K. Martens, J. Mitard, B. De Jaeger, M. Meuris, H. Maes, G. Groeseneken, F. Minucci, F. Crupi, “Impact of Si-thickness
on interface and device properties for Si-passivated Ge pMOSFETs”, European Solid-State Device Research Conference,
pp. 138-141, Edinburgh 2008
[38] E. Miranda, P. Falbo, M. Nafría, F. Crupi, “Progressive breakdown dynamics in HfSiON/SiON gate stacks”, IEEE
International Conference on Microelectronics, pp. 525-528, Nis 2008 (BEST PAPER)
[37] G. Groeseneken, F. Crupi, A. Shickova, S. Thijs, D. Linten, B. Kaczer, N. Collaert, M. Jurczak, “Reliability issues in
MuGFET nanodevices”, IEEE International Reliability Physics Symposium Proceedings, pp. 52-60, Phoenix 2008 (INVITED)
[36] P. Magnone, F. Crupi, G. Iannaccone, G. Giusi, C. Pace, E. Simoen, C. Claeys, “A model for MOS gate stack quality
evaluation based on the gate current 1/f noise”, European Conference on ULtimate Integration of Silicon, pp. 141-144, Udine
2008
[35] C. Claeys, E. Simoen, G. Giusi, F. Crupi, “Does strain engineering impacts the gate stack quality and reliability?”,
Meeting of The Electrochemical Society, vol. 11, n. 6, pp. 101-114, Washington DC 2007 (INVITED)
[34] G. Giusi, F. Crupi, C. Pace, “A procedure for extracting 1/f noise from random telegraph signals”, IEEE Instrumentation
and Measurement Technology Conference, n. 4258288, Warsaw 2007
[33] F. Crupi, G. Giusi, C. Pace, “Two-channel amplifier for high-sensitivity voltage noise measurements”, IEEE
Instrumentation and Measurement Technology Conference, n. 4258236, Warsaw 2007
[32] F. Crupi, “Threshold voltage instability and low frequency noise in Hafnium-based gate dielectrics”, Meeting of The
Electrochemical Society, vol. 3, n. 3, pp. 205-214, Cancun 2006 (INVITED)
[31] F. Crupi, P. Srinivasan, P. Magnone, E. Simoen, C. Pace, D. Misra, C. Claeys, “Impact of the interfacial layer on the
low-frequency noise (1/f) behavior of MOSFETs with advanced gate stacks”, Workshop on Dielectrics in Microelectronics,
Catania 2006
[30] R. Degraeve, Ph. Roussel, M. Cho, B. Kaczer, T. Kauerauf, F. Crupi, G. Groeseneken, “Explaining ‘voltage-driven’
breakdown statistics by accurately modeling leakage current increase in thin SiON and SiO2/high-k stacks”, IEEE
International Reliability Physics Symposium Proceedings, pp. 82-89, San Jose 2006
[29] C. Pace, F. Crupi, S. Lombardo, G. Giusi, “Dedicated instrumentation for single-electron effects detection in Si
nanocrystal memories”, IEEE Instrumentation and Measurement Technology Conference, pp. 1856-1859, Sorrento 2006
[28] G. Giusi, F. Crupi, C. Ciofi, C. Pace, “Instrumentation design for gate and drain low frequency noise measurements”,
IEEE Instrumentation and Measurement Technology Conference, pp. 1747-1750, Sorrento 2006
[27] A. Campera, G. Iannaccone, F. Crupi, G. Groeseneken, “Extraction of physical parameters of alternative high-k gate
stacks through comparison between measurements and quantum simulations”, European Conference on ULtimate
Integration of Silicon, pp. 35-38, Bologna 2005
[26] S. Cimino, L. Pantisano, M. Aoulaiche, R. Degraeve, D.H. Kwak, F. Crupi, G. Groeseneken, A. Paccagnella, “Hot carrier
degradation on n-channel HfSiON MOSFETs: effects on the device performance and lifetime”, IEEE International Reliability
Physics Symposium Proceedings, pp. 275-279, San Diego 2005
[25] T. Kauerauf , R. Degraeve, F. Crupi, B. Kaczer, G. Groeseneken, H.E. Maes, “Trap generation and progressive wearout
in thin HfSiON”, IEEE International Reliability Physics Symposium Proceedings, pp. 45-49, San Diego 2005
[24] F. Crupi, G. Giusi, C. Ciofi, C. Pace, “A novel ultra sensitive method for voltage noise measurements”, IEEE
Instrumentation and Measurement Technology Conference, pp. 1190-1193, Ottawa 2005
[23] R. Degraeve, F. Crupi, D. H. Kwak, G. Groeseneken, “On the defect generation and low voltage extrapolation of QBD in
SiO2/HfO2 stacks”, Symposium on VLSI Technology Digest of Technical Papers, pp. 140-141, Hawaii 2004
[22] R. Degraeve, F. Crupi, M. Houssa, D.H. Kwak, A. Kerber, E. Cartier, T. Kauerauf, P. Roussel, J.L. Autran, G. Pourtois,
L. Pantisano, S. Degendt, M. Heyns, G. Groeseneken, “Reliability issues in high-k stacks”, International Conference on Solid
State Devices and Materials, Tokyo 2004 (INVITED)
[21] C. Ciofi, F. Crupi, C. Pace, G. Scandurra, “Improved trade-off between noise and bandwidth in op-amp based
transimpedance amplifier”, IEEE Instrumentation and Measurement Technology Conference, vol. 3, pp. 1990-1993, Como
2004
[20] F. Crupi, R. Degraeve, A. Kerber, D. H. Kwak, G. Groeseneken, “Correlation between stress-induced leakage current
(SILC) and the HFO2 bulk trap density in a SIO2/HFO2 stack”, IEEE International Reliability Physics Symposium Proceedings,
pp. 181-187, Phoenix 2004
[19] F. Crupi, B. Neri, “Gate current noise evolution and dielectric breakdown of MOS microstructures”, International
Conference on Noise and Fluctuations, pp. 775-780, Prague 2003 (INVITED)
[18] G. Cappuccino, F. Crupi, “Impact of channel-length modulation on the transient response of CMOS gates driving LClines”, EUROMICRO Conference, Belek 2003
[17] B. Kaczer, A. De Keersgieter, R. Degraeve, F. Crupi, G. Groeseneken, “Modeling pFET currents after soft breakdown at
different gate locations”, Conference on Insulating Films on Semiconductors, Barcelona 2003
[16] B. Kaczer, F. Crupi, R. Degraeve, P. Roussel, C. Ciofi, G. Groeseneken, “Observation of hot-carrier-induced nFET gateoxide breakdown in dynamically stressed CMOS circuits”, International Electron Devices Meeting Technical Digest,
pp. 171-174, San Francisco 2002
[15] B. Kaczer, R. Degraeve, A. De Keersgieter, G. Groeseneken, F. Crupi, “Understanding nMOSFET characteristics after
soft breakdown and their dependence on the breakdown location”, European Solid-State Device Research Conference,
pp. 139-142, Firenze 2002
[14] C. Ciofi, F. Crupi, C. Pace, G. Scandurra, P. Sturniolo, “Dedicated probe system for wafer level noise measurements in
MOS devices”, IEEE Instrumentation and Measurement Technology Conference, vol. 1, pp. 769-772, Anchorage 2002
[13] C. Pace, C. Ciofi, F. Crupi, A. Giacobbe, “Very low noise, high accuracy, programmable voltage reference”, IEEE
Instrumentation and Measurement Technology Conference, vol. 1, pp. 635-638, Anchorage 2002
[12] F. Crupi, B. Kaczer, R. Degraeve, A. De Keersgieter, G. Groeseneken, “Location and hardness of the oxide breakdown
in short channel n- and p-MOSFETs” IEEE International Reliability Physics Symposium Proceedings, pp. 55-59, Dallas 2002
[11] F. Crupi, C. Ciofi, G. Iannaccone, B. Neri, S. Lombardo, “Current noise at the oxide hard-breakdown”, Conference on
Insulating Films on Semiconductors, pp. 17-18, Udine 2001
[10] C. Ciofi, F. Crupi, C. Pace, “A new method for high sensitivity noise measurements”, IEEE Instrumentation and
Measurement Technology Conference, vol. 3, pp. 1703-1708, Budapest 2001
[9] S. Lombardo, F. Crupi, J.H. Stathis, “Softening of breakdown in ultra-thin gate oxide nMOSFETs at low inversion layer
density”, IEEE International Reliability Physics Symposium Proceedings, pp. 163-167, Orlando 2001
[8] F. Crupi, B. Neri, S. Lombardo, “On-off fluctuations of the tunnel current before breakdown of thin oxide MOS devices”,
International Conference on Unsolved Problems of Noise, n. 511, pp. 407-411, 2000
[7] B. Neri, F. Crupi, G. Basso, S. Lombardo: “A detailed analysis of the pre-breakdown current fluctuations in thin oxide
MOS capacitors”, International Symposium on the Physical and Failure Analysis of Integrated Circuits, pp.85-88, Singapore
1999
[6] F. Crupi, G. Iannaccone, B. Neri, I. Crupi, R. Degraeve, G. Groeseneken, H.E. Maes, “Origin of the substrate current after
soft-breakdown in thin oxide nMOSFETs”, International Symposium on the Physical and Failure Analysis of Integrated
Circuits, pp. 77-80, Singapore 1999
[5] G. Basso, F. Crupi, B. Neri, R. Giannetti, S. Lombardo, “A novel characterization tool for the study of dielectric breakdown
of ultra-thin oxide MOS structures”, IEEE Instrumentation and Measurement Technology Conference, vol. 3, pp. 1923-1926,
Venezia 1999
[4] N. Pangon, R. Degraeve, P. Roussel, G. Groeseneken, H.E. Maes, F. Crupi, “A new physically-based model for
temperature acceleration of time-to-breakdown”, IEEE Semiconductor Interface Specialists Conference, San Diego 1998
[3] T. Nigam, F. Crupi, R. Degraeve, M. Heyns, G. Groeseneken, and H.E. Maes, “A model for current conduction after softbreakdown”, IEEE Semiconductor Interface Specialists Conference, San Diego 1998
[2] G. Basso, V. Ciuti, F. Crupi, R. Giannetti, B. Neri, “PC based low noise measurement system for the characterization of
ultra thin oxide MOS devices”, IMEKO Conference, Napoli 1998
[1] F. Crupi, R. Degraeve, G. Groeseneken, T. Nigam, and H.E. Maes, “Characteristics and Correlated Fluctuations of the
Gate and Substrate Current after Oxide soft-Breakdown”, International Conference on Solid State Devices and Materials, pp.
144-145, Hiroshima 1998
NATIONAL PATENTS
[1] G. Giusi, F. Crupi, C. Ciofi, C. Pace, “Strumento elettronico ad elevatissima sensibilità per misura del rumore di tensione
di un bipolo”, CCIAA Cosenza, n° CZ2005A000010, May 2005