Series Input Modular Architecture
for Driving Multiple LEDs
J. Patterson, R. Zane
Colorado Power Electronics Center
University of Colorado at Boulder
Boulder, CO 80309-0425 USA
Email: {j patters, zane}@colorado.edu
Abstract – This paper introduces a modular power converter
architecture based on series input connected converter cells
with independent outputs that each drive a small series
string of LEDs. The approach provides the benefits of
operating from a high bus voltage while using low voltage
cells that independently regulate LED currents for
improved light uniformity and LED failure mitigation.
Stability of the series converter string and independent
regulation of the floating LED output currents are achieved
using a two-loop controller that relies on chain control
communications between cells to share system information.
Experimental verification of input bus voltage sharing and
independent cell current regulation is provided using a
prototype of the proposed system with four series buckboost converter cells, where each cell drives four 700 mA
LEDs.
Ig
ILED1
+
V1
_
Vg
Cell1
+
–
ILEDn
Additional
Parallel
Strings
+
Vn
_
Celln
Keywords – solid-state lighting, light emitting diodes, LED,
digital control, modular systems, series input, power
converter
I.
INTRODUCTION
Significant improvements have been achieved over the
past decade in solid state light emitting diodes (LEDs),
leading to high efficiency and high brightness solutions
that are expected to surpass and replace existing lighting
systems in many applications over the coming decade
[1,2]. Although the trend is towards development of
higher current and brightness LEDs, practical solutions for
replacing large lighting panels in general lighting
applications still require use of many LEDs in a system
[3]. Typical solutions place many if not all of the LEDs in
a series string when operating from a high voltage supply
such as the rectified ac line. In addition, current limiting
and regulation of each LED string is required to achieve
the specified luminous output and light uniformity in the
presence of variations in the LED forward voltages [4]
and applied input voltage. Existing solutions for current
regulation in LED strings include use of series resistors or
linear regulators [5] or a single high voltage switching
converter [6] per string. Each of these solutions has
drawbacks, including low efficiency for series linear
elements and high component stress and cost for high
voltage converters. Existing solutions also have limited
flexibility, requiring all LEDs in a large series string to
operate at the same current. The limitations make it
This work is co-sponsored by the National Science Foundation (under
Grant No. 0348772) and industry sponsors of the Colorado Power
Electronics Center.
978-1-4244-1668-4/08/$25.00 ©2008 IEEE
Figure 1 – Proposed Modular Architecture
difficult to compensate for variations in light output
among LEDs and individual LED failures in the system.
This paper introduces a modular architecture, as shown
in Fig. 1, based on series input connected power converter
cells with independent outputs that each drive a reduced
number of series LEDs. The converter cells share the
same input current but self-adjust their respective input
voltages to properly share the total input bus voltage. The
result is a modular architecture that can operate from a
high bus voltage using low voltage converter cells. The
approach has the flexibility to independently regulate the
currents in smaller sub-strings
of LEDs for improved light
_
uniformity and LED failure mitigation.
II.
SYSTEM DESCRIPTION
A. System Analysis
A block diagram of the system structure is shown in
Fig. 1, with detail given for one series string of converter
cells. The number of converter cells in a string is based on
the voltage rating for each cell. The total number of LEDs
associated with a string (sum of LEDs at output of each
cell) depends on the size of the system, but is preferably
selected to maximize efficiency by setting the nominal
converter conversion ratios to near unity. The approach
can be extended to larger systems by adding additional
parallel strings of converter cells.
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The input characteristics of the ith and jth cells in a series
string of n cells for the modular architecture are governed
by the following relationships
Vj =
η i Pj ,
Vi
η j Pi
⎛ η n Pj
Vg = V1 ⎜1 + 1 ∑
⎜
P1 j =2 η j
⎝
Ig = ∑
i
(1)
⎞,
⎟
⎟
⎠
(2)
Pi ,
ηiVg
(3)
where Ig is the input current, Vg is the input bus voltage,
Vi, Vj are cell input voltages, Pi, Pj are cell output powers,
and ηi, ηj are cell efficiencies. The converter cells ideally
act as constant power sinks in the input series string and
transfer regulated power to the output LEDs. This
behavior is shown in Fig. 2 with the input I-V
characteristic for two cells, while more cells would have
similar characteristics.
The startup and breakdown
regions represent operation below and above the rated
voltages of the converter cells, Vmin and Vmax, respectively.
Unfortunately, this type of series converter operation is
prone to instability, as shown in similar architectures [79]. At least one of the converter cells will always reach
steady state outside of the desired operating region, which
makes stabilization of the system the primary concern.
The main control objective, while ensuring stability of
the system, is to have proportional input voltage sharing
according to (1) while maintaining output current
regulation of the series LEDs. Two significant differences
in the LED system application compared to previous
series architectures are that (1) the converter cell outputs
independently drive floating LED loads and are thus not
connected in series or parallel and (2) the output power or
LED current regulation loop in each cell can be slow since
Ii
Constant Power Region
Desired Operating Points
Ig
Cell 1
Cell 2
Startup
Breakdown
Vmin
Vmax
Figure 2 – Input I-V characteristics for 2 cells
operating as constant power sinks
Vi
it only has to respond to gradual variations due to
temperature and aging.
Based on the characteristics mentioned above, there are
two proposed control approaches: an autonomous open
loop approach and a closed loop approach using inter-cell
communication. The open loop approach requires no
inter-cell communications, has a simple control
implementation and a preset nominal operating mode.
The closed loop solution achieves both stable input
voltage sharing and independent output current regulation.
The approach does require inter-cell communications, but
maintains modularity with identical cells and
communications are only preformed between neighboring
cells to avoid isolation requirements.
B. Open Loop Control Approach
The open loop solution is based on having each
converter cell behave as a constant loss-free resistor (LFR)
[10] at its input port. This approach provides stability to
the series converter string and ensures that each cell shares
the input bus voltage proportional to its relative power in
the system. The approach is termed “open loop” since the
output current of each cell is not regulated. The converter
cell may or may not have an internal feedback loop to
achieve LFR behavior, depending on the converter
topology and operating mode. One simple solution is to
use a buck-boost converter operated in the discontinuous
conduction mode (DCM) [10]. In this case, the averaged
input resistance Re of the cell is a function of the duty
cycle D as given by
Re =
2L ,
D 2Ts
(4)
where L is the inductance and Ts is the switching period.
Given nominal operating conditions, the cell duty
cycles would be preset at the factory or calibrated by the
user to generate the desired nominal LED output currents
based on a specified number of cells and nominal input
voltage Vg. The approach is simple and has several added
benefits including the ability to dim the LEDs by scaling
Vg and inherent power factor correction (PFC) due to the
resistor emulation of the input port. Drawbacks include
the requirement for preset configuration and the inability
to react to system variations such as changes in Vg,
component values or LED failures.
C. Closed Loop Control Approach
The closed loop approach requires the converter cells to
operate with two control loops in a similar fashion to PFC
converters [10], as shown in Fig. 3. A fast inner loop,
similar to the open loop approach, is used to achieve
resistor emulation at the converter cell input port. The
inner loop again provides stability to the series converter
string and ensures proportional bus voltage sharing. A
second slow outer loop with an integral type compensator
is used to regulate the cell’s LED current or power. This
approach ensures that the converter cells stabilize to the
desired input voltage while remaining robust to changes in
Vg and regulating the LED current for improved light
uniformity and LED failure response.
Since there are multiple competing loops within the
system, it is necessary to consider system stability. If
DCM buck-boost cells are again used to achieve near LFR
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behavior, then the desired duty cycle of a single series cell
can be written as
Ig
n
D1 =
Additional Converter Cells
with Compensation and
Chain Control
Rg
∑η P
2 L i =1 i i ,
⋅
2
η1 P1
Vg Ts
(5)
Vg +
–
where Pi is the cell output power. Given a nominal input
bus voltage Vg and assuming near identical cells with
efficiencyη = η i , the duty cycle can be approximated as
P
D1 ≈ K tot ,
P1
I1
P1
+
V1
_
R1
Duty Cycle
Generation
(6)
D1
Ptot_next
Chain
Control
where the constant K is given by
K=
(7)
and the total output power Ptot is given by
n
Ptot = ∑ Pi .
(8)
i =1
In order to properly control the system, it is necessary
to look at the potential change in duty cycle given the
dynamics of the cell output power. This sensitivity
function is given by
∂D1
=K
∂P1
Ptot
2 ,
(P1 )
(9)
3
2
which shows that the gain in the outer feedback loop will
have a strong dependence on the total power Ptot as well as
the cell’s own power Pi. In fact the polarity of the
sensitivity function changes when the power of a cell is
equal to the total power of all other cells. For this reason,
the knowledge of Ptot is required to ensure the duty cycle
is properly set.
ILED1
Ptot_prev
Figure 3 – Resistor emulator cell with closed loop
controller within distributed architecture
The communication approach taken involves passing
Ptot among the cells in order for each cell to update its
duty cycle corresponding to the received information. To
maintain modularity in the system and avoid the cost and
complexity of a system controller, a digital moving
window average or chain control is adopted [11]. Each
cell transfers in sequence the moving average of Ptot to the
next cell in the chain via a shared node according to
Ptot _ next [n] = Ptot _ prev [n] − Pled _ i [n − 1] + Pled _ i [n] . (10)
Figure 3 shows the LFR converter model with the closed
loop control approach. The controller consists of three
blocks, with a more detailed view shown in Fig. 4.
The current control block contains an integral
compensator which takes the measured error between a
reference and the output current and predicts the next
desired output current. The output power can be
approximated as a linear function of the output current
when the converter cell is not in the startup or breakdown
regions, therefore in closed loop the predicted output
current is proportional to the predicted output power of the
cell.
Ptot_prev [n]
ILED [n]
ILED_ref
Current
Control
Controller
2 Lη ,
2
Vg Ts
P1 −
+
VLED1
_
Pled_i [n]
G
Ptot_next [n]
Di [n]
z
-1
LUT
Clookup [n]
Pled_i [n-1]
Current
Control
Chain
Control
Duty Cycle
Generation
Figure 4 – Closed loop control block diagram as implemented with DCM buck-boost cell
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This predicted output power Pled_i[n] is then fed into the
chain control block. A new total power Ptot_next[n] is
calculated using the passed in total power Ptot_prev[n] from
the previous cell and the previous and current value for the
predicted cell output power as given in (10). The new
total power is then passed to the next cell in the chain.
The duty cycle generation block takes Pled_i[n] and
Ptot_next[n] from the chain control block and calculates the
cell’s duty cycle from (6) using only one multiplication
Di [n] = Clookup [n] ⋅ Ptot _ next [ n] ,
(11)
and a lookup table (LUT) to find the constant Clookup[n]
from its input Pled_i[n] according to
Clookup[n] =
K
.
(12)
Pled _ i [n]
In order to implement amplitude dimming with the
closed loop algorithm, K would need to be scaled with the
input voltage Vg which could be implemented with a LUT
in order to avoid the need for sensing Vg. One simple way
to implement LED failure mitigation would involve
sensing a fault condition such as excessive average current
or zero current. The converter cell could then short its
input allowing no power to be transferred to the load
while preserving continuity of the input current through
the rest of the series string. The controller ensures that the
remaining cells redistribute the input voltage while
maintaining current regulation.
III.
SIMULATION
A. Simulation Setup
For the modular architecture, the converter cell with
resistor emulation was modeled in Simulink. Using the
LFR model shown in Fig. 3 and a basic exponential model
Ptotprev
Ig
T1
cell_1
Ptotprev
Ig
v1
v2
v3
v4
Ig
T2
cell_2
Ig
Vin
Ptot
cell_3
Ptotprev
Ig
T4
Vin
Ptot
Ptotprev
T3
Vin
Ptot
Vin
Ptot
cell_4
Figure 5– MATLAB Simulink top level simulation
with offset sampling from (10) indicated
for the LED load, both control approaches were simulated.
Because the chain control relies on sequential
communication between cells, a discrete sampling
algorithm was implemented. Using a communication
sample time T1 for the bottom cell, three offsets were
created at
T2 = T1 +
T1 ,
4
T3 = T1 +
T1 , and
2
T4 = T1 +
3T1
4
(13)
for each of the remaining three cells. There was also a
specific startup procedure in the chain control to ensure a
proper simulation. In this manner, each floating cell has
ideal communication keeping the moving window
accurate. Figure 5 shows the top level Simulink model
implementation of chain control where the converter and
compensator model of Fig. 3 is inside each cell block and
input current Ig is generated from the voltage across a
source resistance Rg.
B. Open Loop Results
A simulation using the open loop control approach was
performed to validate resistor emulation techniques and
show the effects of dimming. The open loop simulation
was implemented by ignoring the chain control
information and setting the duty cycle inside the model to
a fixed value. Four resistor emulator operated converter
cells were series connected with fixed duty cycles.
Amplitude dimming was then simulated by initializing a
bus voltage at Vg = 50 V and then performing a step
transition to Vg = 40 V. The simulations verified the four
cells acted as resistors sharing the bus voltage and
consequently decreasing output current appropriately
when the bus voltage was reduced.
C. Closed Loop Results
Closed loop control of the system was also simulated
with several goals: to verify stable input voltage sharing
while maintaining output current regulation and to
validate the ease of LED failure mitigation.
Four series connected cells were again simulated using
the resistor emulator model but now with the chain control
and integral compensator enabled. Figure 6(a) shows all
four cells initially in regulation with 620 mA output
current. Two successive transients were applied to cells 4
and 2 respectively. Both transients were applied via an
LED reference current change to 402 mA. After applying
the transient in both cases, the duty cycle of the applied
cell increased to obtain the new regulated current and
correspondingly, shown in Fig. 6(b), its emulated
resistance decreased causing its share of the input voltage
to decrease. Simultaneously, the other three cells’ input
resistances increased, effectively regulating to the same
output current.
A second simulation was performed to show LED
failure mitigation. Assuming the cell could detect fault
conditions (i.e. excessive currents or open circuit) and
physically short its input, the simulation was created to
show the resultant dynamics of the remaining cells. The
transient in Fig. 7 shows the remaining three cells
redistributing the input voltage and regulating their output
currents. Table 1 gives the relevant DC operating points.
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(a)
(a)
(b)
(b)
Figure 7 – LED failure and input shorting of cell #1
(a) output current (b) input I-V trajectory
Figure 6 – Closed loop transients on cell #4 and #2 respectively
(a) output current (b) input I-V trajectory
TABLE I - DC OPERATING POINTS FOR CLOSED LOOP SIMULATIONS
Bus Input
V g [V]
C.L. Transients
Fig. 6
LED/Cell Failure
Fig. 7
Initial State
Final State
Initial State
Final State
IV.
50
50
40
40
I g [A]
1.045
0.865
1.051
0.833
Cell Input Voltage
Cell Output Current
V 1 [V] V 2 [V] V 3 [V] V 4 [V]
12.42
15.13
8.36
0.22
12.42
9.75
8.36
10.54
EXPERIMENT
A. Experimental Setup
A prototype was developed to experimentally verify the
modular architecture. The circuit employs the modularity
of the architecture by having separable converter and load
stages. Each cell is controlled via an onboard floating
FPGA and corresponding sensing circuitry and ADCs. In
order to power the FPGAs and other ICs reliably, two
auxiliary DC-DC converters are driven by the cell input
voltage with a UVLO that prevents operation below 6.3V
on any cell. Given the power sink nature of the auxiliary
12.42
15.13
10.44
13.18
12.42
9.75
12.53
15.81
I led 1 [A]
0.620
0.620
0.450
0.010
I led 2 [A]
0.620
0.402
0.450
0.450
I led 3 [A]
0.620
0.620
0.450
0.450
I led 4 [A]
0.620
0.402
0.450
0.450
converters, maintaining stability during startup is a
challenge. A 100 Ω resistor was placed across the cell
input to stabilize the voltages during startup when the
FPGAs were connecting to a CPU which was used for
virtual I/O and logic analyzer functions only. Once the
series string of converters reached a steady state open loop
condition, their emulated resistances were much less than
the 100 Ω resistor negating its effect.
A four switch buck-boost power stage, as shown in
Fig. 8, was implemented to test all three basic topologies
(buck, boost, and buck-boost). A DCM buck-boost
configuration was chosen in order to provide simple
resistor emulation for the inner control loop, although
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Ig
ILED2
L2
I2
+
+
FPGA
V2
Cin2
Cout2
_
Isolation
VLED
_
Ig
ILED1
L1
I1
+
+
FPGA
modular load configuration to test a variety of loads. A
four LED load was chosen for each cell and the
experiments covered an LED current range of 300 mA –
800 mA.
Each cell controller was implemented digitally in the
floating FPGA, while an isolation IC was used to
communicate between cells, validating the function of the
system without a central global controller. A differential
sensing circuit and an 8-bit ADC was used to convert the
sensed output current. The main digital hardware for the
controller itself was one LUT and one multiplier. A delay
line based hybrid DPWM was used for the gate drive
signal [15]. Figure 8 shows the prototype design and
Table 2 gives details of the hardware used.
V1
Cin1
Cout1
_
VLED
_
Figure 8 – Prototype design using isolated FPGAs
with Li = 1 μ H, Cin_i =1 μF. C out_i = 22 μ F
average current [12], hysteretic [13] or nonlinear carrier
control [14] methods could be used with a variety of
topologies and operating modes to achieve the same
result. Luxeon K2 700 mA emitters were used with a
B. Experimental Results
Many experiments were performed with this prototype
using different topologies, operating modes and
conditions. However, the two experiments shown in
Figs. 9-10 validate the key aspects of the two proposed
control approaches for this architecture. First, all four
cells were run using the open loop control approach and
DCM buck-boost power stages with four LEDs each. All
four cells were initialized at a duty cycle that yielded
approximately 620 mA output current given a bus voltage
Vg = 50 V. Then amplitude dimming was tested by
quickly decreasing the bus voltage to Vg = 40 V. Figure 9
shows that the four cells respond identically by decreasing
their output current according to the decrease in input
voltage.
A second experiment is shown in Fig. 10 which tested
the closed loop control approach with two successive
Figure 9 – Open loop control showing uniform dimming
Ch-1: I LED1, 500 mA/div; Ch-2: I LED2, 500 mA/div; Ch-3: I LED3,
500 mA/div; Ch-4: I LED4, 500 mA/div; Time: 1 s/div
Figure 10 – Closed loop transients on cell #4 and #2 respectively
Ch-1: I LED1, 500 mA/div; Ch-2: I LED2 , 500 mA/div; Ch-3: I LED3,
500 mA/div; Ch-4: I LED4, 500 mA/div; Time: 1 s/div
TABLE II - POWER SWITCHES AND IC COMPONENTS USED IN PROTOTYPE
Device
Part Number Description
Diode
PDS540
Schottky 40V 5A
MOSFET STN3NF06L N-Channel 60V 4A
ADC
AD7825
8bit 4Channel Multiplexed
HB Driver LM5101
Half Bridge Driver
Opamp
OPA350U
35MHz Rail-to-Rail
Isolator
ISO7221
Dual Digital Isolator 2MSPS
Boost
LT3436
Regulator 3A
Buck
LT3508
Dual Regulator 1.4A
TABLE III - DC OPERATING POINTS FOR EXPERIMENTS
Bus Input
Cell Input Voltage
Cell Output Current
V g [V] I g [A] V 1 [V] V 2 [V] V 3 [V] V 4 [V]
O.L. Dimming Fig.
9
C.L. Transients
Fig. 10
Initial State
Final State
Initial State
Final State
50
40
50
50
1.079
0.876
1.040
0.885
12.62
9.83
12.60
15.77
12.33
9.96
12.45
9.26
12.29
10.14
12.46
15.63
12.89
10.15
12.92
9.80
I led 1 [A]
0.625
0.373
0.635
0.640
I led 2 [A]
0.618
0.353
0.625
0.398
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I led 3 [A]
0.646
0.401
0.610
0.612
I led 4 [A]
0.626
0.388
0.620
0.402
small transients. The experimental results were obtained
using the same conditions as the simulation from Fig. 6
and correspond well to the simulation results. When a
transient change in the reference current occurred on one
cell, it changed its duty cycle to regulate to the new value,
while the remaining cells were able to maintain their
current regulation with only a small perturbation. Table 3
contains the DC operating points of the experiment for
both the open loop dimming test and the closed loop
transient.
The experimental results for the two
consecutive transients closely match the simulation of the
closed loop chain control architecture.
C. Observations
The experimental prototype was designed to be flexible
and stable through many different testing conditions. The
FPGAs were chosen to make control algorithm changes
quick and to have the ability to synchronize with a CPU
via JTAG communication for virtual I/O and logic
analyzer capabilities. The JTAG communication is in a
daisy chain structure and an isolation circuit was needed
to connect all the FPGAs to the CPU.
This
communication with the CPU was not used to stabilize the
system, but rather to provide simple monitoring and
triggering of operating modes. The auxiliary converters
used to power the FPGA, ADC, op-amp and drivers were
also used to simplify the experimental process.
A potential commercial application is to integrate the
control functions and power devices on a single low
voltage IC. The only external components are the inductor
and output capacitor, which can be minimized with high
frequency operation of the low voltage cell. Each
integrated cell would need only two control pins, one for
sending signals up the chain and one for sending signals
down the chain as well as the power stage pins. Isolators
are not required for communications since control pins
only connect to neighboring cells where current-mode
techniques could be used to communicate over these
overlapping nodes. A diagram of one option using a
buck-boost converter power stage is shown in Fig. 11.
The benefit when compared to one large high voltage
converter is that many miniature, high efficiency, reduced
voltage and power cells can be operated directly off of a
high voltage bus and grouped with sub-sets of LEDs and
distributed in the lighting fixture.
V. CONCLUSION
The proposed series input modular architecture for LED
lighting systems achieves the benefits of operating from a
high bus voltage using low voltage converter cells with
the flexibility to independently regulate the currents in
small sub-strings of LEDs for improved light uniformity
and LED failure mitigation. Stability of the series
converter string and independent regulation of the floating
LED output currents are achieved using a two-loop
controller that relies on chain control communications
between cells to share system information. Simulation and
experimental results demonstrate feasibility and operation
of the architecture using series buck-boost converter cells.
Both dimming and LED failure mitigation possibilities are
enumerated and briefly examined as added benefits of the
architecture.
Additional Converter Cells
Ig
Vg
+
–
+
Vi
_
Comup
Integrated
Control
and Power
Switches
ILED_i
Li
Cout_i
+
VLED_i
_
Comdown
Additional Converter Cells
Figure 11– Proposed integrated converter cell
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