University of Tennessee, Knoxville
Trace: Tennessee Research and Creative
Exchange
Masters Theses
Graduate School
8-2006
A Low Noise CMOS Charge-Sensitive
Preamplifier with Pole/Zero Compensation for a
Neutron Detection System
Steven Curtis Bunch
University of Tennessee - Knoxville
Recommended Citation
Bunch, Steven Curtis, "A Low Noise CMOS Charge-Sensitive Preamplifier with Pole/Zero Compensation for a Neutron Detection
System. " Master's Thesis, University of Tennessee, 2006.
http://trace.tennessee.edu/utk_gradthes/1514
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To the Graduate Council:
I am submitting herewith a thesis written by Steven Curtis Bunch entitled "A Low Noise CMOS ChargeSensitive Preamplifier with Pole/Zero Compensation for a Neutron Detection System." I have examined
the final electronic copy of this thesis for form and content and recommend that it be accepted in partial
fulfillment of the requirements for the degree of Master of Science, with a major in Electrical
Engineering.
Benjamin J. Blalock, Major Professor
We have read this thesis and recommend its acceptance:
Charles L. Britton, Jr., Syed K. Islam
Accepted for the Council:
Dixie L. Thompson
Vice Provost and Dean of the Graduate School
(Original signatures are on file with official student records.)
To the Graduate Council:
I am submitting herewith a thesis written by Steven Curtis Bunch entitled “A Low Noise
CMOS Charge-Sensitive Preamplifier with Pole/Zero Compensation for a Neutron
Detection System.” I have examined the final electronic copy of this thesis for form and
content and recommend that it be accepted in partial fulfillment of the requirements for
the degree of Master of Science, with a major in Electrical Engineering.
___Benjamin J. Blalock_______________
Major Professor
We have read this thesis
and recommend its acceptance:
___Charles L. Britton, Jr.__________
___Syed K. Islam________________
Accepted for the Council:
__Anne Mayhew_____________________
Vice Chancellor and
Dean of Graduate Studies
(Original signatures are on file with official student records.)
A LOW NOISE CMOS CHARGE-SENSITIVE PREAMPLIFIER WITH
POLE/ZERO COMPENSATION FOR A NEUTRON DETECTION SYSTEM
A Thesis Presented for the
Master of Science Degree
The University of Tennessee, Knoxville
Steven Curtis Bunch
August 2006
DEDICATION
This thesis is dedicated to my brother, Daniel Allen Bunch. Daniel departed this
earth on July 18, 2004 and is greatly missed by his friends and family but mostly his
brother. I love you and will see you again, not today but someday.
Psalms 100
ii
ACKNOWLEDGMENTS
I would like to thank all of the faculty and staff in the Electrical and Computer
Engineering Department for their support. Specifically I would like to thank Dr. Ben
Blalock for teaching me the fundamentals of analog circuit design, Dr. Syed Islam and
Dr. Don Bouldin for teaching me the fundamentals of CMOS circuit design, and special
thanks to Dr. Charles Britton for his guidance and teaching of nuclear detector systems.
I am especially grateful for the Graduate Research Assistantship I was awarded
for the duration of my Masters work. Without the GRA I would have not been able to
pursue my Master of Science degree as soon as I wanted. My fellow students and
colleagues deserve many thanks as well for providing different outlooks on many of the
issues that were encountered during the project. Specifically I would like to thank Dr.
Stephen Terry, Robert Greenwell, Suheng Chen, James Vandersand, Mark Hale, and
Jonathan Britton.
I believe that family and friends deserve the most thanks for the support during
my graduate studies. I especially want to thank my loving wife Jestina whom I could not
have succeeded without her love, support, and understanding.
This project was made possible by the National Science Foundation along with
collaborations with Kansas State University, Dr. Douglas McGregor who is the PI for the
project, Spallation Neutron Source, and Oak Ridge National Laboratory.
iii
ABSTRACT
This thesis presents the design and implementation of a low noise CMOS charge
sensitive preamplifier with pole/zero compensation for a neutron detector to be installed
on the Spallation Neutron Source in Oak Ridge, TN. The first prototype chip has been
fabricated using Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm
process. The system contains a preamplifier, an active resistive feedback network, a
pole/zero compensation network, and the first real pole input to the shaper system.
Experimental results of the system show that proper functionality was achieved. The
preamplifier is noise dominant with only 540 rms electron noise at 5 pF detector
capacitance and can be used with either a positive or negative input charge signal. The
active resistive feedback network uses an on chip nanoampere current source for biasing
and a 4-bit D/A converter for user selectable feedback resistance and detector leakage
current compensation up to 15 nA. The pole/zero compensation network actively tracks
the feedback network for automatic compensation. The first real pole sets the first time
constant for the shaper system.
iv
TABLE OF CONTENTS
CHAPTER 1 ..................................................................................................................................................1
INTRODUCTION AND OVERVIEW.......................................................................................................1
Introduction ...........................................................................................................................................1
Overview................................................................................................................................................2
CHAPTER 2 ..................................................................................................................................................3
RADIATION-DETECTOR SIGNAL FORMATION AND SIGNAL PROCESSING ..............................3
Signal Formation in a Detector .............................................................................................................3
Preamplifier Signal Processing .............................................................................................................4
Pole/Zero Compensation .......................................................................................................................6
CHAPTER 3 ..................................................................................................................................................8
DESIGN OF FRONT-END COMPONENTS.............................................................................................8
Input MOSFET Noise Optimization.......................................................................................................8
Preamplifier Design.............................................................................................................................10
Feedback Network Design ...................................................................................................................24
Pole/Zero Compensation Network Design...........................................................................................30
First Real Pole Design.........................................................................................................................33
CMOS Layout Techniques ...................................................................................................................35
CHAPTER 4 ................................................................................................................................................42
MEASURED RESULTS ..........................................................................................................................42
Preamplifier Measurements.................................................................................................................42
First Real Pole Measurements.............................................................................................................48
System Measurements ..........................................................................................................................50
CHAPTER 5 ................................................................................................................................................53
CONCLUSION ........................................................................................................................................53
Preamplifier Conclusions ....................................................................................................................53
First Real Pole Conclusions ................................................................................................................54
System Conclusions .............................................................................................................................54
LIST OF REFERENCES ...........................................................................................................................56
APPENDIX ..................................................................................................................................................59
VITA.............................................................................................................................................................62
v
TABLE OF FIGURES
Figure 2.1 – General radiation detector schematic ............................................................. 4
Figure 2.2 – General preamplifier schematic...................................................................... 4
Figure 2.3 – Preamplifier noise model................................................................................ 5
Figure 2.4 – General pole/zero compensation network ...................................................... 6
Figure 2.5 – Detector system signal formation................................................................... 7
Figure 3.1 – Preamplifier schematic ................................................................................. 11
Figure 3.2 – Relevant MOSFET parasitic capacitances ................................................... 11
Figure 3.3 – Preamplifier input MOSFET bias................................................................. 13
Figure 3.4 – W optimization of M2 .................................................................................. 14
Figure 3.5 – L optimization of M2.................................................................................... 15
Figure 3.6 – W optimization of M3 .................................................................................. 15
Figure 3.7 – L optimization of M3.................................................................................... 16
Figure 3.8 – Total noise of M1, M2, and M3 ................................................................... 16
Figure 3.9 – Simple current mirror topology .................................................................... 18
Figure 3.10 – Cascode current mirror topology................................................................ 18
Figure 3.11 – Preamplifier current mirror comparison..................................................... 19
Figure 3.12 – Preamplifier loop transmission setup ......................................................... 20
Figure 3.13 – Preamplifier loop transmission w/o compensation..................................... 21
Figure 3.14 – Preamplifier loop transmission w/ compensation....................................... 21
Figure 3.15 – Preamplifier half gain adjustment .............................................................. 22
Figure 3.16 – Final preamplifier circuit w/o feedback ..................................................... 23
Figure 3.17 – Single MOSFET feedback network............................................................ 25
Figure 3.18 – Low frequency feedback loop .................................................................... 25
Figure 3.19 – Feedback network....................................................................................... 26
Figure 3.20 – Nanoampere current source........................................................................ 27
Figure 3.21 – 4-bit D/A feedback network bias converter................................................ 28
Figure 3.22 – D/A setting 1 for largest effective resistance ............................................. 29
Figure 3.23 – D/A setting 15 for smallest effective resistance ......................................... 30
Figure 3.24 – Pole/Zero compensation circuit topology................................................... 31
Figure 3.25 – Pole/Zero compensation tracking ............................................................... 32
Figure 3.26 – First pole opamp topology.......................................................................... 33
Figure 3.27 – First pole opamp AOL and phase................................................................. 34
Figure 3.28 – First pole opamp AOL and phase w/ Cc ....................................................... 36
Figure 3.29 – First pole opamp AOL and phase w/ Cc and Rz ........................................... 36
Figure 3.30 – Substrate cross-section of latch up devices ................................................ 38
Figure 3.31 – Latch up equivalent circuit ......................................................................... 38
Figure 3.32 – Guard ring layout in an n-well.................................................................... 39
Figure 3.33 – Preamplifier layout ..................................................................................... 40
Figure 3.34 – Channel layout............................................................................................ 40
Figure 3.35 – Padframe layout.......................................................................................... 41
Figure 4.1 – Preamplifier rise time vs. input bias current (full gain)................................ 43
Figure 4.2 – Preamplifier rise time vs. input bias current (half gain)............................... 43
Figure 4.3 – Preamplifier gain vs. input bias current (full gain)....................................... 45
vi
Figure 4.4 – Preamplifier gain vs. input bias current (half gain)...................................... 45
Figure 4.5 – Noise vs. input MOSFET bias current ......................................................... 46
Figure 4.6 – Preamplifier output vs. feedback settings (full gain).................................... 47
Figure 4.7 – Preamplifier output vs. feedback settings (half gain)................................... 47
Figure 4.8 – First real pole output vs. preamplifier feedback settings (positive charge
input and full gain)....................................................................................... 48
Figure 4.9 – First real pole output vs. preamplifier feedback settings (positive charge
input and half gain) ...................................................................................... 49
Figure 4.10 – First real pole output vs. preamplifier feedback settings (negative charge
input and full gain)....................................................................................... 49
Figure 4.11 – First real pole output vs. preamplifier feedback settings (negative charge
input and half gain) ...................................................................................... 50
Figure 4.12 – Total system noise vs. detector capacitance ............................................... 51
Figure 4.13 – Total system gain across a single chip ....................................................... 52
Figure 4.14 – Total system gain across multiple chips..................................................... 52
Figure A.1 – Preamplifier loop transmission setup .......................................................... 60
Figure A.2 – Preamplifier loop transmission small signal model..................................... 60
vii
CHAPTER 1
INTRODUCTION AND OVERVIEW
Introduction
Radiation detector systems have been widely used for many years in nuclear
science applications. These systems allow scientists and engineers the ability to observe
and study a variety of topics such as Positron Emission Tomography (PET), Germanium
spectroscopy, X-Ray spectroscopy, and many others. Each detector system has different
requirements based on the specific application it is used in. However, some detector
systems have been generalized in order to reduce cost and to allow for reuse on differing
applications.
Many advances in radiation detector systems have been achieved over the years
such as moving from the printed circuit board (PCB) design with discrete components to
the application specific integrated circuit (ASIC), or microchip, design. Detector systems
on a chip allow for a much smaller and more compact design than the PCB. Also, a large
number of high resolution channels can be fabricated on a single chip thus making
radiation detectors on a chip the ideal approach. ASICs are paving the way for low cost
and high volume manufacturability. With these new technological advances, however,
come many challenges in the design process.
The specific application this thesis will focus on is a detector system for the
Spallation Neutron Source (SNS). The SNS is an accelerator-based neutron source in
Oak Ridge, Tennessee, which was built by the U.S. Department of Energy. The SNS will
provide the most intense source of pulsed neutron beams in the world for scientific
research and industrial development and is due to begin operation in 2007. The SNS will
require a variety of neutron detectors for the beam port instruments. Because the SNS
instruments will require detectors capable of spatial resolutions of 100 microns by 500
microns and response times of less than 10 microseconds, a new detector system must be
developed since no current detector systems are capable of these specifications [1].
1
Overview
This thesis provides a detailed discussion of the design and fabrication of the
front-end electronics for a neutron detector ASIC. The front-end circuit design consists
of a low noise charge-sensitive preamplifier, a highly resistive active feedback/reset
network with compensation, a nanoampere current source, and an operational amplifier,
or opamp. The preamplifier topology is a regulated cascode structure optimized for low
noise and very fast rise time performance.
The feedback/reset network is a low
frequency feedback loop optimized for detector leakage current compensation [2]. The
current source is a nanoampere source to supply the active feedback/reset network
biasing for high resistivity and proper detector leakage current compensation [3] that is
controlled by a DAC. The opamp is a high-gain circuit with dominant pole frequency
response used in the shaper system to establish the first real pole.
Chapter 2 provides the necessary background information of a radiation detector
signal formation and the required signal processing by the ASIC. Chapter 3 explains the
design of the preamplifier, including noise optimization, design of the active
feedback/reset network, design of the pole/zero compensation components, first real pole
of the shaper, and special layout techniques. Chapter 4 presents the results of the
fabricated ASIC and Chapter 5 contains conclusions made of the overall system and
performance.
2
CHAPTER 2
RADIATION-DETECTOR SIGNAL FORMATION AND SIGNAL
PROCESSING
The main objective of a radiation detector is to translate a radiation event into
charge that can be manipulated by electronics. There are many different components that
make up a radiation detector system such as the detector itself, a charge sensitive
preamplifier, a pulse shaper, a discriminator, etc. This chapter will expand on how
charge is created from a detector and how the translated signal is used in the system
electronics.
Signal Formation in a Detector
When a charged particle passes through a radiation detector, ions are created.
This event creates an accumulated charge which is proportional to the detector-medium
energy required to create an electron-hole pair. The value of charge is found by first
obtaining the total number of electron-hole pairs created and then multiplying by the
charge of a single electron. For example, a charged particle with 1.47 MeV of energy
passing through a silicon strip detector will illustrate this. Because the amount of energy
required to create an electron-hole pair in silicon is 3.6 eV/pair [13], the total number of
electron-hole pairs is found by dividing the total energy of the charged particle by 3.6
eV/pair which yields approximately 408,333 pairs. Then multiplying the total number of
electron-hole pairs by 1.6E-19 C/e- yields a charge of approximately 65.3 fC.
Electronically, a silicon-based radiation detector is a reverse biased diode.
Because of this, the radiation detector inherently has a reverse bias leakage current and a
junction depletion capacitance. These two parasitics will play an important role in the
design of the preamplifier. Figure 2.1 illustrates how a radiation detector is modeled
schematically.
3
i (t)
Cdet
Figure 2.1 – General radiation detector schematic
Rf
Cf
__
+
Figure 2.2 – General preamplifier schematic
Preamplifier Signal Processing
A preamplifier is used in the radiation detector system to enhance signal-to-noise
ratio and for converting the charge into a usable voltage pulse signal. Equation 2.1 shows
how charge can be converted into voltage
V=
Q
C
(2.1)
where V is voltage in Volts, Q is charge in Coulombs, and C is capacitance in Farads.
The capacitance is introduced as a feedback element connected between the input and
output of the preamplifier.
Because the feedback capacitor stores the incoming charge, a path needs to be
provided to allow for the charge to bleed off before the next radiation event occurs.
Therefore a discharge path needs to be applied between the input and output of the
preamplifier to allow for the charge to bleed off of the capacitor. Figure 2.2 above
illustrates how the preamplifier is modeled.
4
Past work has been done on optimizing the noise of radiation detector systems [5].
Results have shown that the input MOSFET in the preamplifier needs to dominate the
noise of the entire system. Therefore the noise sources that contribute to the input
MOSFET noise need to be modeled and defined and then optimized for each detector
system. Figure 2.3 shows the noise model for the input MOSFET of the preamplifier.
The input MOSFET contributes thermal and flicker noise to the system which can be
optimized by the designer. The detector and feedback resistor contribute parallel noise
sources as well. Techniques used to optimize the noise of the system are shown in
Chapter 3.
Since it is highly desirable to have only the input device of the preamplifier be the
dominant noise source of the system, the feedback resistor must be very large, typically
in the range of GΩs. Equation 2.2 describes the thermal noise which is characterized by
a parallel current generator associated with the resistor [4].
i2 =
4kT
R
(2.2)
It can be seen that a larger resistance value would yield a lower noise contribution
than a smaller value. Unfortunately, a resistor on the order of GΩs would be very
impractical to fabricate on silicon, therefore a CMOS feedback network must be
implemented to emulate a large resistor. Chapter 3 discusses the feedback network used
in this implementation.
Detector
and feedback
resistor parallel
noise
M1
I2therm + i21/f
Figure 2.3 – Preamplifier noise model
5
Pole/Zero Compensation
The resistive and capacitive feedback elements across the preamplifier create a
pole in the closed-loop transfer function. Typically radiation detectors operate at with
many radiation events occurring each second. Pile up happens when radiation events
occur before the output of the system is able to return to baseline. Therefore a very short
time constant is required to prevent pile up from occurring.
Because of the large
resistance required for low noise and the low capacitance required for low gain, a long
time constant is created which is not suitable for the signal processing. One way to
compensate for the large time constant is to introduce a zero into the system with the
same time constant to cancel out the pole created from the preamplifier feedback loop.
Then an amplifier can be added with the desired feedback loop to provide a fast time
constant for the pulse shaper system. Figure 2.4 illustrates a simplified schematic of the
system [14]. Figure 2.5 shows an example of the output of the preamplifier and the
pole/zero compensation.
Rf
R1
Cf
Cz
C
Vout2
Iin
Cdet
Vout1
Rz
Figure 2.4 – General pole/zero compensation network
6
Detector Input
Preamplifier Output
Pole/Zero
Compensation
Figure 2.5 – Detector system signal formation
Equation 2.3 gives the transfer function for the preamplifier.
Vout1
Rf
=
Iin
1 + s Rf Cf
(2.3)
Equation 2.4 gives the transfer function for the first real pole.
Vout2 R1 (1 + s Cz Rz)
=
Vout1 Rz (1 + s C1 R1)
(2.4)
Multiplying 2.3 and 2.4 yields the total transfer function for the pole/zero compensation
network.
Vout2
Rf R1 (1 + s Cz Rz)
=
Iin
Rz (1 +s Rf Cf) (1 + s C1 R1)
(2.5)
The values of R1 and C1 determine the desired time constant of the pulse. The values of
Cz and Cf along with Rz and Rf must be equal for the pole/zero compensation to work.
However, it may be desirable to have Cz and Cf different values as well as Rz and Rf as
long as the product of Rz and Cz is equal to that of Rf and Cf. Resizing these devices is
advantageous when considering layout issues and/or the gain of the first real pole block.
7
CHAPTER 3
DESIGN OF FRONT-END COMPONENTS
The front-end electronics define how well the remaining components of the
readout system will operate. For example, the input MOSFET of the preamplifier is
designed and optimized to be the dominant noise source of the entire system. This
chapter will elaborate on the design of the front-end electronics which include the
preamplifier, feedback network, pole/zero compensation network, first real pole
implementation, and CMOS layout techniques. The fabrication process for the chip is
Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 µm [10, 11] using the
MOSIS [8] foundry service.
Input MOSFET Noise Optimization
Because signal integrity is extremely important in this type of system, it is critical
that all noise sources be defined and then designed to be as low as possible. Since the
preamplifier is charge-sensitive, a convenient method of defining noise is to use an
equivalent number of electrons. Equation 3.1 shows the conversion of the voltage noise
value to number of electrons.
Number of electrons =
Qin (rms Noise)
Vout (1.6E10 −19 )
(3.1)
In 3.1 the noise is the total input referred noise of the system in Volts rms, Qin is the input
charge to the preamplifier, and Vout is the output voltage being measured.
The Equivalent Noise Charge (ENC) is the traditional measurement term for
describing the resolution of charge sensitive front-end electronics. The ENC corresponds
to the charge that must be delivered to the front-end in order to achieve a signal to noise
ratio equal to the unity and is measured in rms electrons. Equation 3.2 states the classical
ENC model for a charge sensitive preamplifier [5].
ENC
2
⎡ 4kT γ K f
= (C det + C gs ) 2 ⎢
+
C gs
⎢⎣ g m
8
⎤
⎥
⎥⎦
(3.2)
The first term in the bracket is due to the thermal noise of the input MOSFET and the
second term is the 1/f noise of the input MOSFET. Cdet is the detector capacitance and
Cgs is the MOSFET gate to source capacitance.
There are many variables that contribute to the ENC of a MOSFET which are
technology dependent and user defined. A designer usually only has control of the W/L
ratio of the transistor and is therefore limited in the noise optimization process. The only
parameters in equation 3.2 that the designer has control over is gm and Cgs. A high gm
yields a lower thermal noise contribution to the ENC, however, an optimum for Cgs must
exist since increasing or decreasing Cgs can mean large changes in the ENC. Equations
3.3 and 3.4 define gm in strong inversion saturation and Cgs in terms of W and L
respectively in order to visualize how a change in W and L will affect each term [5].
gm =
W
ID
L
(3.3)
2
C ox WL
3
(3.4)
2µ N C ox
C gs =
The first design consideration would be to use the minimum L allowed in the process
technology being used which allows the maximum gm with respect to L. In order to find
the optimum W for the ENC, Cgs will have to be optimized. The optimum ENC with
respect to Cgs will yield the required value of W.
Solving 3.4 for Cox and substituting
into 3.3 yields
3µ N C gs I D
gm =
L2
(3.5)
Substituting 3.5 into the thermal noise portion of 3.2 differentiating with respect to Cgs,
and setting the result equal to zero gives
C gs =
C det
3
(3.6)
Using 3.6 along with a known Cdet, W can be defined to give the required Cgs value for
the MOSFET [5]. This optimization method was used to optimize the input MOSFET
designed for this neutron detection system that is explored in more detail in the next
section.
9
Preamplifier Design
Many different charge sensitive preamplifier topologies have been designed
according to the detector and system they will be operating in [2, 7, 12].
The
preamplifier designed for this project had to meet a variety of specifications mostly based
on the neutron detector interface. The specifications include the following:
•
Low noise ≤ 1000 electrons for detector capacitance of 5 pF
•
Positive or Negative charge input
•
Detector leakage current compensation
•
Active pole/zero compensation network
•
Preamplifier gain adjustment
The circuit topology chosen for the preamplifier is a NMOS regulated cascode
amplifier for low 1/f noise based on previous work [7] which is shown in Figure 3.1. The
thermal noise of M1 is proportional to gm1 which is in turn proportional to the square root
of Cgs of M1, from equation 3.5. Therefore it is essential to minimize any parasitic
capacitances adding to Cgs of M1.
Miller capacitance from Cgd adds to Cgs by
multiplying Cgd with the gain of M1 [4]. Therefore by reducing the gain of M1 the
addition of the Miller capacitance is minimized. The gain of M1 is proportional to the
impedance seen at the drain of M1 [4]. The regulated cascode topology in Figure 3.1
inherently has a minimized impedance at the drain of M1 because of current sampling in
the negative feedback loop between M2 and M3.
Therefore the regulated cascode
preamplifier minimizes the addition of Miller capacitance to the total Cgs of M1 and in
turn helps optimize the noise of M1.
The design of the preamplifier relies heavily on the input MOSFET, in this case
M1, to dominate the noise of the system. It is therefore critical to optimize M1 for low
noise.
The optimization process defined in the previous section describes the
methodology. From the specifications, the target detector capacitance is 5 pF and, using
equation 3.6, yields a design parameter of 1.67 pF for Cgs of M1. Figure 3.2 shows the
parasitic capacitances that need to be included to consider the total contribution to Cgs of
M1.
10
VDD
Ibias1
Ibias2
Vout
M2
M3
Qin
M1
Figure 3.1 – Preamplifier schematic
Cgd
Cgb
Cgs
Figure 3.2 – Relevant MOSFET parasitic capacitances
11
The total input capacitance for M1 is calculated using
C tot = C gs + C gd + C gb
(3.7)
Equation 3.4 defines Cgs which includes a parameter Cox that is defined by
C ox =
ε ox
t ox
(3.8)
where εox is the dielectric constant of SiO2 which is approximately 3.45E-13 F/cm and tox
is the thickness of the SiO2 layer, approximately 7.8 nm for the TSMC 0.35-µm process
[9]. Calculating Cox yields 4.4E10-3 F. Equations 3.9 and 3.10 define Cgd and Cgb using
parameters CGDO and CGBO extracted from MOSIS [9].
C gd = (CGDO)(W)
(3.9)
C gb = ( CGBO)(L)
(3.10)
CGDO is the gate to drain overlap capacitance that is 206 pF/m and CGBO is the gate to
body overlap capacitance that is 1 pF/m. Combining equations 3.6 and 3.7 and solving
for W yields the optimal equation for W
W =
C tot − ( CGBO) ( L)
2 ε ox
L
+ CGDO
3 t ox
(3.11)
Therefore using a minimum L of 0.4 µm and a Ctot of 1.67 pF yields an optimized W
value of at least 1,191 µm. To accommodate layout issues a total W of 1,250 µm was
chosen comprised of 50 gate fingers, each with a width of 25 µm. This implementation
helped minimize parasitic gate resistance.
The input transistor will need to have a larger amount of bias current to maintain
strong inversion saturation than M2. Therefore an additional current source is introduced
to bias M1 without disturbing the bias of M2. The additional bias current was calculated
to be approximately 200 µA.
Figure 3.3 illustrates how the biasing of M1 is
accomplished.
12
VDD
200 µA
Ibias1
Ibias1
Vout
M2
M3
Qin
M1
Figure 3.3 – Preamplifier input MOSFET bias
M2 and M3 must also be optimized to contribute no more than 10% of the noise
of M1 at the noise corner frequency. The optimization process for these devices is as
follows:
1. First, fix L to be minimum of 0.4 µm and vary W
2. Next, pick an optimum W and then vary L
3. Finally, pick an optimum L
The M2 device is optimized first by choosing L = 0.4 µm and varying W with the
values 1 µm, 10 µm, 20 µm, and 30 µm. A bias current of 20 µA was used to bias M2
and M3 along with a 200 µA bias current for M1 to give a total bias current of 120 µA
for M1. The M3 device W and L were chosen to operate the device in strong inversion
saturation and will be optimized after M2. The results for varying W on M2 show that
even for a W = 1 µm the noise contribution is negligible; however by increasing W
further, the M2 noise contribution is lowered. The optimum W for M2 is chosen to be 30
µm. Figure 3.4 shows the results of the W optimization for M2.
13
Figure 3.4 – W optimization of M2
Once the optimum W for M2 was found, the next step was to vary L with the
values 0.4 µm, 1.2 µm, and 2.0 µm. The results in Figure 3.5 show that an L of 2.0 µm
gives the lowest noise contribution at the noise corner frequency. Therefore the W and L
of M2 were chosen to be 10 µm and 2.0 µm respectively with three gate fingers for a
total W of 30 µm.
The same steps taken to optimize M2 were used to optimize the M3 device. The
L of M3 was fixed at 0.4 µm and W was varied by 1 µm, 3 µm, 7 µm, and 10 µm. The
value W = 10 µm was the only size that allowed M3 to contribute no more than 10% to
the total noise, therefore a W of 10 µm was chosen for M3. Figure 3.6 illustrates the
results of varying W for M3.
Varying the values of L for M3 showed an improvement of approximately 1%
noise contribution when L is increased to 7 µm.
Figure 3.7 shows the results of
optimizing L for M3. The W and L of M3 were chosen to be 10 µm and 7 µm,
respectively, with one gate finger to match the current density of M2. Figure 3.8 shows
the final results of optimizing M1, M2, and M3.
14
Figure 3.5 – L optimization of M2
Figure 3.6 – W optimization of M3
15
Figure 3.7 – L optimization of M3
Figure 3.8 – Total noise of M1, M2, and M3
16
Two different current source topologies were investigated for supplying the
needed bias currents in the preamplifier. The first topology used was a simple current
mirror as seen in Figure 3.9. In order to reduce short channel effects and provide high
output impedance, a long L value must be used for the PMOS current source devices.
For each PMOS device an L of 6 µm was chosen. A mirror current of 40 µA was chosen
which required a W no more than 45 µm to remain in strong inversion. Each PMOS
device uses a W of 3 µm and multiple gate fingers to improve matching. Therefore the
final current mirror design used a diode connected PMOS device with a width of 3 µm,
an L of 6 µm, and fifteen gate fingers for a total W of 45 µm. An external bias resistor is
attached to the drain of M4 to produce 40 µA which is mirrored to the other PMOS
devices. Because the input MOSFET M1 requires a current bias of at least 200 µA, the
width of M5 must be at least five times larger than M4 which is accomplished by using
75 gate fingers. Current source devices M6 and M7 are sized to half the width of the M4
device to give 20 µA of bias current in each branch.
The second current source topology used was a cascode connection of the simple
current mirror as seen in Figure 3.10. The cascode current mirror provides a higher
output resistance which will increase the open loop gain of the preamplifier. Each
transistor is sized exactly the same as in the simple current mirror configuration with the
exception of M4 which has an L that is four times the other MOSFETs, or 24 µm, thereby
allowing a lower minimum voltage across the current source [4].
Both the simple and cascode current mirror configurations were compared to
study the effect of each on the preamplifier performance.
Figure 3.11 shows the
comparison of the total noise contribution of each current source configuration. It is
obvious that there is little difference in the total output noise; however the cascode
current mirror gives slightly more noise contribution.
Therefore the simple current
mirror configuration was chosen not only for the slightly lower noise, but for simplicity
and layout area consideration.
17
VDD
M4
M5
M6
M7
Vout
M2
M3
Qin
M1
Figure 3.9 – Simple current mirror topology
VDD
M9
M10
M11
M12
M13
M4
M8
M5
M6
M7
Vout
M2
M3
Qin
M1
Figure 3.10 – Cascode current mirror topology
18
Figure 3.11 – Preamplifier current mirror comparison
The regulated cascode amplifier inherently has a negative feedback loop between
M2 and M3 as seen in Figure 3.1. This negative feedback loop can pose instability issues
which must be explored.
In order to evaluate the loop transmission, the negative
feedback loop must be broken and a test input voltage must be applied and the output of
the loop can be analyzed. Figure 3.12 illustrates how to break the feedback loop.
The graph in Figure 3.13 shows the output gain of the feedback loop and the
phase. It is easily seen that the phase margin is approximately -30o which is very
unstable.
Therefore a compensation capacitor must be introduced to stabilize the
feedback loop. By connecting a 0.3 pF compensation capacitor between the drain of M2
and the drain of M3, the feedback loop phase margin was dramatically increased to
approximately 90o, which is seen in Figure 3.14.
transmission can be found in the Appendix.
19
All hand analysis for the loop
VDD
M4
M5
M6
M7
Vout
M2
40 µA
Vin
+
+
-
M3
M1
Figure 3.12 – Preamplifier loop transmission setup
20
Figure 3.13 – Preamplifier loop transmission w/o compensation
Figure 3.14 – Preamplifier loop transmission w/ compensation
21
Because this was a prototype design, there needed to be some features to adjust
the performance of the system. The preamplifier bias current circuit was designed to
mirror 20 mA; however a potentiometer could be used to change the bias current.
Another performance adjustment feature that was added was a gain adjustment. The
simplest solution was to provide a full-gain or half-gain adjustment. For example if the
feedback capacitor across the input and output of the preamplifier was 1 pF (which would
be designated full gain) then another 1 pF capacitor would be added in parallel with a
control switch (which would be designated half gain). Figure 3.15 illustrates how this is
accomplished. Transistors M1 and M2 both had a width of 2 µm and a length of 1 µm.
In order for the PMOS device, M2, to drive the circuit the same as the NMOS devices,
the width must be at least 2.5× larger or 5 µm with the length being the same. When the
Control signal goes high, Cf2 is grounded and no connection is made across the feedback.
However, when the Control signal goes low, then Cf2 is connected between the input and
output of the preamplifier.
The final part of the preamplifier design is to add a buffer to the output in order to
drive larger capacitances without affecting the preamplifier performance. The buffer is a
simple source follower PMOS device with a minimum length of 0.4 µm and a width of
10 µm and 5 gate fingers for a total width of 50 µm for driving larger capacitances.
Figure 3.16 is the final preamplifier circuit design without feedback which will connect
between the gate of M1 and the drain of M2 and will also be discussed in the next
section.
Input
Cf2
M1
M2
M3
Output
Control
Figure 3.15 – Preamplifier half gain adjustment
22
VDD
M4
M5
M6
M7
Vout
40 µA
Cc
M8
M2
M3
Qin
M1
Figure 3.16 – Final preamplifier circuit w/o feedback
23
Feedback Network Design
The feedback network for the preamplifier consists of a charge collecting
capacitor and a resistive feedback network to allow charge to bleed off of the feedback
capacitor. The charge gain needs to be low enough to keep the preamplifier output from
saturating. Saturating the output would cause ballistic deficit which is a reduction in
amplitude because the bandwidth has been degraded by the gain.
Therefore the
maximum output voltage was chosen to be approximately 600 mV and the maximum
input charge is approximately 120 fC [1]. Using equation 2.1, the feedback capacitor was
chosen to be 0.2 pF.
One solution for the charge bleed off would be to apply a resistor in parallel to the
feedback capacitor. Consequently the resistor adds a noise source to the input MOSFET
described in equation 2.2. In order to reduce the noise contribution, the resistance value
would have to be large which is not practical in terms of chip area, therefore an active
feedback network will allow for less area and can behave as a very large passive resistive
element. This section explores different active feedback topologies and describes the
design that was chosen.
Figure 3.17 illustrates one possible topology for the feedback network which is
based on previous work [12]. The single MOSFET feedback network provides minimum
thermal noise and high linearity, requires baseline stabilization, and can also be realized
in multiple stages [6]. A second possible feedback network topology is shown in Figure
3.18. The low frequency feedback loop topology can have high noise, requires baseline
stabilization at high rates, and loop transmission compensation with Cc can be an issue
[6]. Both circuits of Figures 3.17 and 3.18 have their advantages and disadvantages
which the designer must evaluate according to the specifications and constraints of the
system to be designed.
24
Vbias
Cf
VFigure 3.17 – Single MOSFET feedback network
Vdd
Ibias
Vref
Vdd
Cf
Cc
VFigure 3.18 – Low frequency feedback loop
25
The circuit topology used in the system presented here is in Figure 3.19 and is
based more on the circuit in Figure 3.18 than the circuit in Figure 3.17, however the idea
stems from the single MOSFET feedback design. The basic operation of the feedback
network in Figure 3.19 is when a charge pulse is introduced to Cf then there is a change
in voltage on the gate of M2 which in turn will introduce a change in current between the
drains of M1 and M4. The gate of M2 will stabilize back to the Vref voltage on the gate
of M1 because of the differential pair action of M1 and M2. This is effectively a resistor
since a change in voltage gives a proportional change in current. Of course linearity is a
concern and will be explored later in this section.
Biasing the feedback network is a challenge because in order to achieve a large
effective resistance the operation region of the MOSFETs has to be deeply in the linear
region. This is achieved by using bias currents ranging in the nanoampere region. The
design used to bias the feedback network here is an on-chip nanoampere current source
[3]. Figure 3.20 shows the circuit topology of the nanoampere current source.
Vdd
2 x Ibias
Vdd
Vref
M1
M2
Ibias
M3
M4
Cf
VFigure 3.19 – Feedback network
26
VDD
5
100 :1
M1
M2
14.8
10 :6
5
150 :1
M3
M4
14.8
10 :1
M10
2
2
:1
3
6
M9
Vout
:10
M11
2
2
:1
10 nA
M12
2
2
:1
M13
2
2
2
10
M5
:15
M6
2
10
:1
M8
M7
2
10
:5
:5
Figure 3.20 – Nanoampere current source
27
2
10
:1
VDD
From nA
current source
Vout
M1
M2
3
6
D0
M5
:1
D1
2
2
:1
M3
3
6
M6
:2
D2
2
2
M4
3
6
:1
:4
D3
M7
2
2
:1
M9
3
6
:8
M8
D0
2
2
:1
M10
3
6
M13
:2
D1
2
2
:1
M11
3
6
M14
:4
D2
2
2
M12
3
6
D3
M15
2
2
:1
:8
:1
3
6
:16
2
2
:1
M16
2x
Ibias
Ibias
Figure 3.21 – 4-bit D/A feedback network bias converter
The M8 and M9 branch produces a 10 nA current mirror that can be distributed to
other PMOS current sources to bias the feedback network. Because it is necessary to
change the feedback network biasing to measure the effects, a simple 4-bit D/A converter
was made to allow a feedback network bias between 1 nA and 15 nA for one bias branch
and between 2 nA and 30 nA for the other bias branch in Figure 3.19. Figure 3.21 above
shows the 4-bit D/A circuit topology used.
The Vref signal in Figure 3.19 is used mainly to establish a baseline for the output
of the preamplifier. It can also be increased or decreased to provide the maximum
dynamic range for either a positive or negative charge input to the preamplifier. Through
simulations the setting for maximum dynamic range for a positive charge input is
approximately 2 V and approximately 1.5 V for a negative charge input.
Adjusting the feedback network bias current via the 4-bit D/A converter also
compensates for detector leakage current. If more detector leakage current is suspected
then more bias current must be supplied to achieve proper operation since the leakage
current is pulling current directly from the drains of M1 and M4 in Figure 3.19. Because
only a 4-bit D/A converter was used, the maximum detector leakage current which the
feedback network can handle is 15 nA. The maximum compensation current can be
increased simply by increasing the bias current range that can be accomplished by using
larger PMOS widths for the bias current source or adding more bits to the D/A converter.
In order for the resistive feedback network to function as a resistor, a linear
relationship between voltage change and current change must exist. Simulations were
28
performed with Vref = 1.75 V, which is the midrange value between 1.5 and 2.0 V. A
small change in voltage was applied on the drain of M2, of Figure 3.19, while the current
flowing through M1 was monitored. The D/A converter settings were switched between
only DS0, of Figure 3.22, on and then all signals DS0-3, of Figure 3.23, on to show the
contrast between the largest and smallest effective resistance. What can be noticed is
when the change in voltage on the gate of M2 is positive, there is a small change in
current, thus effectively emulating a large resistance. However, when the change in
voltage on the gate of M2 is negative, there is a large change in current that yields a
smaller effective resistance.
y = 0.065x + 1.0369
2
R = 0.998
y = 8.823x - 14.639
2
R = 0.9983
1.14
Reff = 113 MΩ
Reff = 15 GΩ
1.04
Current (nA)
0.94
0.84
0.74
0.64
0.54
0.44
1.71
1.73
1.75
1.77
1.79
1.81
Volt (V)
Figure 3.22 – D/A setting 1 for largest effective resistance
29
1.83
1.85
14
y = 0.42x + 12.602
2
R = 0.9964
y = 113.11x - 186.74
2
R = 0.9976
13
Reff = 2.4 GΩ
Reff = 8.8 MΩ
12
Current (nA)
11
10
9
8
7
6
1.71
1.73
1.75
1.77
1.79
1.81
1.83
1.85
Volt (V)
Figure 3.23 – D/A setting 15 for smallest effective resistance
Pole/Zero Compensation Network Design
Pole/Zero Compensation in nuclear detector front end systems was introduced in
Chapter 2. Figure 2.4 showed the basic topology of the pole/zero compensation and
equation 2.5 described how the pole/zero compensation worked. The first real pole
required a time constant of 70 ns, therefore the value of Cf2 was 2 pF and the value of Rf2
was 35 kΩ. The first real pole also required a gain of 1.5, thereby requiring Cz to be 3 pF
which is 15× larger than Cf. In order to achieve proper pole/zero compensation, the value
of Rz must be approximately 15× larger than Rf. It was also desirable to have Rz
automatically track any changes in Rf, therefore the topology shown in Figure 3.24 was
used. The transistors which make up Rz use the same widths and lengths as those of the
preamplifier feedback only with 15× more gate fingers. Similarly, the biasing for the
tracking Rz network was an exact replica of Figure 3.21 with each PMOS current source
30
Vdd
Vdd
2 x Ibias
Vdd
30 x
Ibias
Vref
M1
Vref
M2
M6
Ibias
M3
Vdd
M5
15 x
Ibias
M4
M8
M7
Cf
Cz
Output
VFigure 3.24 – Pole/Zero compensation circuit topology
device having 15× more gate fingers than the PMOS current source devices biasing the
resistive feedback network across the preamplifier.
Figure 3.25 describes the tracking performance of the pole/zero compensation
network. When the D/A converter is set on the lowest setting, or highest resistive
feedback, the pole/zero compensation tracks very well.
However, when the D/A
converter is set on the highest setting, or lowest resistive feedback, the pole/zero
compensation does not track as well, meaning it undershoots when the pulse is falling
and there is slight ballistic deficit seen in the amplitude. Matching errors in the current
source devices biasing the resistive feedback networks can contribute to poor tracking
along with matching errors between the preamplifier resistive feedback and the pole/zero
compensation network. A pole/zero adjustment could be added to the circuit in order to
compensate for these matching errors in future work.
31
Figure 3.25 – Pole/Zero compensation tracking
32
First Real Pole Design
Chapter 2 described why the long time constant of the preamplifier had to be
compensated and a pole had to be created with a time constant desired for the shaping
system as seen in Figure 2.4. The first real pole for the system presented was constructed
using a basic operational amplifier (opamp) design with an RC closed loop feedback to
establish the desired time constant and gain needed for the input to the shaper system.
Figure 3.26 shows the circuit topology used for the basic opamp design. The basic opamp
design consists of a differential pair input, a secondary gain stage, and a buffered output
stage. The ideal opamp model requires that the open loop gain, AOL, be infinite so that
the gain can be controlled by the feedback and not the gain of the opamp itself.
Therefore it is critical that the opamp’s AOL be as high as possible. Equation 3.12
describes the AOL of the first two stages of the opamp in Figure 3.26.
A OL = g m1 (ro2 || r04 ) ⋅ [ − g m5 (ro5 || r09 )]
(3.12)
Vdd
3
6
:15
M7
3
6
M8
3
6
:40
3
6
:75
M9
Output
Cc
Ibias
V-
M1
3
1
3
1
:48
:48
M2
M6
V+
3
0.6 :48
Rz
M5
4
5
:2
M3
M4
4
5
4
0.6 :30
:2
Figure 3.26 – First pole opamp topology
33
:75
M10
Because gm is proportional to the square root of the tail current for strong
inversion saturation and the W to L ratio of the device, it is essential to have a large W
and tail current to maximize gm. The ro term is inversely proportional to the drain
current, therefore a lower bias current will yield a larger ro.
The differential input pair and current mirror were sized to achieve a high gain
while considering layout area. The same approach was taken with the second stage of
M5 and the buffer output stage of M6. Larger bias currents were used for the M5 device
to increase slew rate and bandwidth. The large bias current of M6 is used to increase
capacitive drive capability. The open loop gain, neglecting Cc and Rz for now, is shown
in Figure 3.27 which also illustrates the phase margin. The phase margin of the opamp is
approximately -60o which is highly unstable.
Figure 3.27 – First pole opamp AOL and phase
34
The addition of a compensation capacitor between the drain and gate of M5 can yield a
higher phase margin by shifting the point where AOL equals zero towards a lower
frequency. Equation 3.13 describes how to choose a value for Cc [4].
Cc =
g m1
2π f t
(3.13)
The ft term is the desired frequency that corresponds with a more desirable phase margin.
Normally, it is desired to have a phase margin of no less than 45o when compensating an
opamp [4]. Therefore, in order to achieve at least a 45o phase margin from Figure 3.27
the ft frequency should be around 30 MHz. By knowing the value of gm1 and ft, Cc is
calculated to be approximately 2 pF. Figure 3.28 shows the result of adding Cc between
the drain and gate of M5, neglecting Rz for now.
The phase margin can be increased yet again by using a technique called lead
compensation. Lead compensation is achieved by adding a series resistance with the
compensation capacitor which shifts the right-half plane zero associated with Cc to the
left-half plane therefore increasing the phase margin [4]. The value of Rz in Figure 3.26
needs to be larger than
1
, or approximately 550 Ω, to achieve lead compensation. The
g m5
value of Rz was chosen to be approximately 5kΩ which increased the phase margin to
approximately 55o. Figure 3.29 illustrates the resulting open loop gain of the opamp with
both Cc and Rz added to the drain and gate of M5.
CMOS Layout Techniques
Designing a circuit to be fabricated on a silicon chip requires knowledge about
parasitic elements that can greatly affect the performance of the circuit. Some of these
parasitics include capacitances, inductances, resistances, latch up, parasitic transistors,
etc. Fortunately CMOS IC circuit layout techniques exist which can greatly reduce the
effects of these parasitics.
35
Figure 3.28 – First pole opamp AOL and phase w/ Cc
Figure 3.29 – First pole opamp AOL and phase w/ Cc and Rz
36
One of the most prevalent parasitic elements in CMOS layout is latch up. Latch
up occurs when two parasitic BJTs are formed in the substrate, which given the right
conditions, can turn on and eventually short the power rail to the ground rail and
potentially destroy the chip [4]. Figure 3.30 shows how the parasitic BJT devices are
formed and Figure 3.31 shows the equivalent circuit schematic.
One way to help prevent latch up is to provide a guard ring of well contacts which
surrounds each transistor that effectively reduces the substrate or well resistance and can
prevent either of the parasitic BJT devices from turning on. Figure 3.32 is an example of
a guard ring layout.
For the prototype chip, a maximum height for each channel was 71 µm with 4 µm
between each channel. The chip length was 4 mm and the width was 2.5 mm to give a
total area of 10 mm2. Each channel consisted of a preamp, pole/zero compensation, first
real pole, and shaper stage. However, in order to conserve layout space, the biasing
networks for each branch were included in a separate channel and then paralleled down to
each functional channel. The preamplifier and shaper power rails were separated for ease
in measuring power consumption of each. Also, each pad on the padframe included
electrostatic discharge (ESD) protection circuitry. Figures 3.33, 3.34 and 3.35 illustrate
the layouts for the preamplifier, individual channel, and entire chip padframe,
respectively.
37
Substrate
surface
contact
Source of
n-channel
transistor
p+
vdd
n+
Source of
p-channel
transistor
p+
n+
n-well
p - epi
p+ substrate
Figure 3.30 – Substrate cross-section of latch up devices
vdd
Figure 3.31 – Latch up equivalent circuit
38
vdd
Well
contact
Figure 3.32 – Guard ring layout in an n-well
39
Figure 3.33 – Preamplifier layout
Figure 3.34 – Channel layout
40
Figure 3.35 – Padframe layout
41
CHAPTER 4
MEASURED RESULTS
This chapter presents the measured results of the preamplifier, the first real pole,
and some complete system measurements. All of the measurements were made using a
motherboard and daughterboard test setup.
The daughterboard was made to hold
individual chips which could then be interchangeable on the motherboard for testing. A
copper shielding box was used around each daughterboard to keep out light and RF
interference. The entire motherboard was encased in a steel box for further RF isolation.
All measurements were taken with an active FET oscilloscope probe with 2 pF input
capacitance, 1GHz bandwidth, 10× attenuation, and 1MΩ input impedance.
Preamplifier Measurements
The first preamplifier measurements that needed to be made were how rise time,
gain, and noise were affected by preamplifier bias current. This is important because all
of these parameters are dependent on the value of the bias current for the input MOSFET.
Figure 4.1 shows the results of the preamplifier rise time with changes in bias current and
for the full-gain setting. Figure 4.2 shows the same type of results for the half-gain
setting.
The rise time of the preamplifier shown in Figure 4.1 was expected to be
approximately 25 ns according to simulation results. The measured results show that at
40 µA bias current the rise time is approximately 260 ns and 170 ns for the full gain and
half gain settings respectively. The slow rise times are most likely caused by scope
loading and/or circuit board capacitance.
42
670
620
Chip 3 Pos
Chip 4 Pos
Chip 5 Pos
Chip 6 Pos
Chip 7 Pos
570
Chip 3 Neg
Chip 4 Neg
Chip 5 Neg
Chip 6 Neg
Chip 7 Neg
Rise Time (ns)
520
470
420
370
320
270
220
15
20
25
30
35
40
Preamp Bias Current (uA)
Figure 4.1 – Preamplifier rise time vs. input bias current (full gain)
450
Chip 3 Pos
Chip 4 Pos
Chip 5 Pos
Chip 6 Pos
Chip 7 Pos
400
Chip 3 Neg
Chip 4 Neg
Chip 5 Neg
Chip 6 Neg
Chip 7 Neg
350
Rise Time (ns)
300
250
200
150
15
20
25
30
35
40
Preamp Bias Current (uA)
Figure 4.2 – Preamplifier rise time vs. input bias current (half gain)
43
As the preamplifier bias current is increased, the rise time decreases which is
expected because the input MOSFET changes from weak inversion to strong inversion
saturation operation. Also, the input charge polarities were changed between positive and
negative input that show there is not much change in the rise time with either input
polarity. It is also expected that as the gain is decreased, the rise time should increase
because the gain bandwidth product (GBP) should remain constant.
The next measurement to consider was how the preamplifier gain changes with
bias current. Figures 4.3 and 4.4 illustrate the full-gain setting and half-gain setting,
respectively, as the bias current is changed. The gain is measured in mV per fC, which is
the charge gain of the preamplifier. It is easily seen that as the bias current is increased,
the gain decreases as expected since the rise time decreases as well. Also, chips 3 and 4
showed 10% less gain than all other chips, showing how parameters can change chip-tochip.
Another important measurement is how the noise changes with bias current.
Figure 4.5 shows the noise in rms electrons as the input MOSFET bias current is changed
with zero and 15pF detector capacitance. As expected, the noise is increased with an
increase in detector capacitance and the noise decreases with an increase in bias current.
The preamplifier active feedback network changes effective resistance using the
4-bit D/A converter. Figure 4.6 displays the output of the preamplifier in full gain mode
as the feedback settings on the D/A converter are changed with setting 1 being the largest
effective resistance and setting 15 being the smallest. Once the feedback setting is
between 5 and 15, an undershoot forms because of ballistic deficit. The output decreases
by approximately 10 mV and the undershoot increases to approximately 10 mV as well,
which further shows the effect of ballistic deficit on the full gain setting. Figure 4.7
displays the output of the preamplifier in half gain mode as the feedback settings are
changed. The ballistic deficit seen in the full gain mode is reduced to a minimum in the
half gain mode.
44
3.6
3.5
Gain (mV/fC)
3.4
3.3
3.2
3.1
Chip 3 Pos
Chip 4 Pos
Chip 5 Pos
Chip 6 Pos
Chip 7 Pos
3
Chip 3 Neg
Chip 4 Neg
Chip 5 Neg
Chip 6 Neg
Chip 7 Neg
2.9
15
20
25
30
35
40
Preamp Bias Current (uA)
Figure 4.3 – Preamplifier gain vs. input bias current (full gain)
2
Chip 3 Pos
Chip 4 Pos
Chip 5 Pos
Chip 6 Pos
Chip 7 Pos
1.95
Chip 3 Neg
Chip 4 Neg
Chip 5 Neg
Chip 6 Neg
Chip 7 Neg
1.9
Gain (mV/fC)
1.85
1.8
1.75
1.7
1.65
1.6
15
20
25
30
35
40
Preamp Bias Current (uA)
Figure 4.4 – Preamplifier gain vs. input bias current (half gain)
45
1200
0pF Detector
15pF Detector
1100
Noise (rms electrons)
1000
900
800
700
600
500
70
90
110
130
150
170
190
Bias Current (uA)
Figure 4.5 – Noise vs. input MOSFET bias current
46
210
2.0E-02
1.0E-02
0.0E+00
-1.0E-02
Voltage (V)
-2.0E-02
-3.0E-02
-4.0E-02
-5.0E-02
-6.0E-02
Setting 1
Setting 2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Setting 9
Setting 10
Setting 11
Setting 12
Setting 13
Setting 14
Setting 15
-7.0E-02
-8.0E-02
-1.00E-05
1.00E-05
3.00E-05
5.00E-05
7.00E-05
9.00E-05
1.10E-04
1.30E-04
Time (s)
Figure 4.6 – Preamplifier output vs. feedback settings (full gain)
5.0E-03
0.0E+00
-5.0E-03
-1.0E-02
Voltage (V)
-1.5E-02
-2.0E-02
-2.5E-02
-3.0E-02
-3.5E-02
Setting 1
Setting 2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Setting 9
Setting 10
Setting 11
Setting 12
Setting 13
Setting 14
Setting 15
-4.0E-02
-4.5E-02
-1.00E-05
4.00E-05
9.00E-05
1.40E-04
Time (s)
Figure 4.7 – Preamplifier output vs. feedback settings (half gain)
47
1.90E-04
First Real Pole Measurements
The first real pole sets the first shaping time constant after the pole/zero
compensation network. Measurements were taken to observe how well the first real pole
stage operates with changes in full or half gain mode of the preamplifier, feedback
settings on the D/A converter of the preamplifier feedback network, and positive or
negative input charge to the preamplifier.
Figures 4.8 and 4.9 illustrate the output of the first real pole with positive charge
input and full/half gain modes across all preamplifier feedback network settings. Figures
4.10 and 4.11 show the same outputs with a negative charge input setting. The pole/zero
compensation tracks well for the first few feedback network settings, however as the
setting increases the compensation does not track as well, especially in the full gain
mode. Many factors could be to blame for the poor tracking, such as transistor matching,
parasitic capacitances, poor capacitive matching, and current bias matching.
3.5E-02
3.0E-02
Setting 1
Setting 4
Setting 7
Setting 10
Setting 13
Voltage (V)
2.5E-02
Setting 2
Setting 5
Setting 8
Setting 11
Setting 14
Setting 3
Setting 6
Setting 9
Setting 12
Setting 15
2.0E-02
1.5E-02
1.0E-02
5.0E-03
0.0E+00
0.00E+00
5.00E-07
1.00E-06
1.50E-06
2.00E-06
2.50E-06
3.00E-06
Time (s)
Figure 4.8 – First real pole output vs. preamplifier feedback settings (positive charge
input and full gain)
48
2.5E-02
2.0E-02
Setting 1
Setting 2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Setting 9
Setting 10
Setting 11
Setting 12
Setting 13
Setting 14
Setting 15
Voltage (V)
1.5E-02
1.0E-02
5.0E-03
0.0E+00
0.00E+00
2.00E-07
4.00E-07
6.00E-07
8.00E-07
1.00E-06
1.20E-06
1.40E-06
1.60E-06
1.80E-06
2.00E-06
Time (s)
Figure 4.9 – First real pole output vs. preamplifier feedback settings (positive charge
input and half gain)
0.0E+00
-5.0E-03
Voltage (V)
-1.0E-02
-1.5E-02
-2.0E-02
-2.5E-02
Setting 1
Setting 2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Setting 9
Setting 10
Setting 11
Setting 12
Setting 13
Setting 14
Setting 15
-3.0E-02
-3.5E-02
0.00E+00
5.00E-07
1.00E-06
1.50E-06
2.00E-06
2.50E-06
3.00E-06
Time (s)
Figure 4.10 – First real pole output vs. preamplifier feedback settings (negative charge
input and full gain)
49
0.0E+00
-5.0E-03
Voltage (V)
-1.0E-02
-1.5E-02
Setting 1
Setting 2
Setting 3
Setting 4
Setting 5
Setting 6
Setting 7
Setting 8
Setting 9
Setting 10
Setting 11
Setting 12
Setting 13
Setting 14
Setting 15
-2.0E-02
-2.5E-02
0.00E+00
2.00E-07
4.00E-07
6.00E-07
8.00E-07
1.00E-06
1.20E-06
1.40E-06
1.60E-06
1.80E-06
2.00E-06
Time (s)
Figure 4.11 – First real pole output vs. preamplifier feedback settings (negative charge
input and half gain)
System Measurements
This section will show some important total system measurements that include the
shaper circuits. Noise performance measurements are of high interest because the total
system should be less than 1000 rms electrons noise with a detector capacitance of 5 pF.
Total system gain is of interest but is not as critical as noise performance. The system
response to either polarity input charge is also addressed in this section.
Figure 4.12 shows the results of noise measurements compared to simulation
results with increasing detector capacitance. These results show that the system is well
within the noise specification with a 5 pF detector capacitance. The total system noise
does not approach 1000 rms electrons until the detector capacitance is at least 18 pF.
Also note that the noise performance is better than the simulated values by approximately
80 rms electrons at the same detector capacitance.
50
1300
1200
1100
Noise (rms electrons)
1000
900
800
Measured
700
Simulation
600
500
400
300
0
5
10
15
20
25
Cdet (pF)
Figure 4.12 – Total system noise vs. detector capacitance
The next measurement of interest is the total system gain with either polarity
input charge and full or half gain mode of the preamplifier. Figure 4.13 shows the total
system gain across all sixteen channels on a single chip with the preamplifier feedback
network setting at the smallest effective resistance.
There is some relatively large
variation of gain across the channels that can stem from a variety of reasons such as
mismatch in channels, biasing mismatch, input capacitance, etc. Figure 4.14 illustrates
how much the gain can vary across multiple chips. The preamplifier feedback network
was also set to the smallest effective resistance, the input charge polarity was positive,
and the gain was on the full setting for the measurement in Figure 4.14. Varying the
input charge polarity or the gain setting yielded approximately the same results as seen in
Figure 4.14. The variation in gain across channels and across multiple chips can be quite
large which creates the need for individual channel threshold adjustments for the
discriminator on the future prototype chip.
51
10
9
Gain (mV/fC)
8
Positive Full
Negative Full
Positive Half
Negative Half
7
6
5
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Channel
Figure 4.13 – Total system gain across a single chip
9.8
Chip 3
Chip 4
9.6
Chip 7
Gain (mV/fC)
9.4
9.2
9
8.8
8.6
8.4
1
3
5
7
9
Channel
11
13
Figure 4.14 – Total system gain across multiple chips
52
15
16
CHAPTER 5
CONCLUSION
This thesis introduced why the project was needed, provided an overview of how
a nuclear detection system operates, discussed design of the front end components for this
project, and presented measured results. Following this project there are plans to revise
the shaper system and add the remaining components that include a discriminator on the
output of each individual channel, a D/A converter to control the threshold of each
discriminator on the individual channels, a discriminator mask, and low voltage
differential signaling (LVDS) output interface. The following three sections summarize
the performance of the preamplifier, first real pole, and overall system.
Preamplifier Conclusions
The preamplifier was introduced in Chapter 2 and the design was introduced in
Chapter 3. The main purpose of the preamplifier is to convert input charge from a
nuclear detector into a voltage output signal. In order to achieve high signal integrity, it
is critical that the preamplifier not introduce much noise into the signal and also dominate
the noise of the system.
Special design considerations were made to ensure stability of the preamplifier
and low noise operation as outlined in Chapter 3. Detector leakage current and detector
capacitance were both very critical components in the design process because the
capacitance determines the noise performance and the leakage current can greatly hinder
the preamplifier performance if not compensated properly. The active resistive feedback
network used in this project is a new approach to selectable feedback values, leakage
current compensation, and pole/zero compensation.
The measurement results shown in Chapter 4 are very encouraging, especially for
the first prototype chip of the neutron detector system. The preamplifier successfully
performed as it was designed and even achieved a lower noise performance than
53
simulations predicted. The active resistive feedback network was fully adjustable and the
on-chip nanoampere current source was fully functional.
First Real Pole Conclusions
Chapter 2 introduced why pole/zero compensation was needed along with a first
real pole to the shaper system. Because chip size and time was a factor in the first
prototype design, a simple basic opamp design was used to implement the amplifier for
the first real pole. The time constant for the first real pole was determined by the shaper
system design along with the gain, which also dictated the closed-loop feedback element
values.
The opamp designed for the first real pole was designed to meet all specifications
of the system. Compensating the opamp proved to be difficult but achievable with the
addition of a lead resistor to help achieve a proper phase margin.
Special layout
considerations were taken to reduce the effects of parasitic elements and matching errors.
The pole/zero compensation network, which feeds into the first real pole, had
some difficulty properly compensating in full gain mode as seen in Chapter 4. Matching
errors could be to blame, however an off-chip pole/zero compensation adjustment could
have been added therefore giving the user more control over the function. However, the
overall performance illustrated in Chapter 4 shows proper operation of the first real pole
and encouraging results for a future chip design.
System Conclusions
The overall measured system performance in Chapter 4 was very close to the
simulation predictions.
In some cases, such as the total noise performance, the
measurements were better than expected, however in other aspects, such as the pole/zero
compensation, the results were not as good. Tests have not been performed with a
detector or a live neutron source as of the writing of this thesis.
However, the
measurements are promising enough that the system should be fully functional with the
detector specifications for which it was designed. Therefore, in conclusion, the prototype
54
chip design presented in this thesis performed as well as, if not better, than expected and
is a milestone toward the final neutron detector system to be installed at the SNS in the
near future.
55
LIST OF REFERENCES
56
[1]
Douglas S. McGregor, “IMR-MIP: High-Detection-Efficiency and High-SpatialResolution Thermal Neutron Imaging System for the Spallation Neutron Source
using Pixelated Semiconductor Neutron Detectors,” NSF Proposal Number
0412208.
[2]
P.F. Manfredi, I. Kipnis, A. Leona, L. Luo, E. Mandelli, M. Momayezi, M. Nyman,
M. Pedralinoy, V. Re, N. Roe, F. Svelto, “The analog front-end section of the
BaBar silicon vertex tracker readout IC,” Nuclear Physics B (Proc. Suppl.), Vol.
61B, pp. 532-538, 1998.
[3]
Henri J. Oguey, Daniel Aebischer, “CMOS Current Reference Without Resistance,”
IEEE Journal of Solid-State Circuits, Vol. 32, No. 7, pp. 1132-1135, 1997.
[4]
R.J. Baker, H.W. Li, and D.E. Boyce, CMOS Circuit Design, Layout, and
Simulation, IEEE Press, 1998. ISBN 0-7803-3416-7.
[5]
Gianluigi De Geronimo, Paul O’Connor, “MOSFET Optimization in Deep
Submicron Technology for Charge Amplifiers,” Nuclear Science Symposium
Conference Record, Vol. 1, pp. 25-33, 2004.
[6]
Paul O’Connor, “Charge-Sensitive Front End Circuits,” IEEE Nuclear Sciences
Symposium Short Course, 2001.
[7]
C.L. Britton, Jr., L.G. Clonts, M.N. Ericson, S. S. Frank, J. A. Moore, M. L.
Simpson, G.R. Young, R. S. Smith, J. Boissevain, S. Hahn, J. S. Kapustinsky, J.
Simon-Gillo, J. P. Sullivan, H. van Hecke, “A 32-channel preamplifier chip for the
multiplicity vertex detector at PHENIX,” Review of Scientific Instruments, Vol. 70,
No. 3, pp. 1684-1687, 1999.
[8]
The MOSIS Service, http://www.mosis.org.
[9]
The MOSIS Service, http://www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/
tsmc-035/t59n_mm_epi-params.txt.
[10] The MOSIS Service, http://www.mosis.org/products/fab/vendors/tsmc/tsmc035/
[11] TSMC Ltd, http://www.tsmc.com/english/a_about/a05_literature/
a0501_brochures.htm.
[12] G. Gramegna, P. O’Connor, P. Rehak, S. Hart, “Low-Noise CMOS PreamplifierShaper for Silicon Drift Detectors,” IEEE Transactions on Nuclear Science, Vol.
44, No. 3, pp. 346-350, 1997.
[13] F. S. Goulding, D. A. Landis, “Signal Processing for Semiconductor Detectors,”
IEEE Transactions on Nuclear Science, Vol. 29, No. 3, pp. 1125-1141, 1982.
57
[14] C. H. Nowlin, J. L. Blankenship, “Elimination of Undesirable Undershoot in the
Operation and Testing of Nuclear Pulse Amplifiers,” Review of Scientific
Instruments, Vol. 36, pp. 1830-1839, 1965.
58
APPENDIX
59
PREAMPLIFIER LOOP TRANSMISSION
Cc
RLC1
RLC2
M2
Ii
Vout
Vin
M3
RL
Figure A.1 – Preamplifier loop transmission setup
Vt1
Vt2
Cc
gm2Vgs2
Ii
RLC2
ro2
+ V
gs2
-
RLC1
Vout
RL
Figure A.2 – Preamplifier loop transmission small signal model
I i = − g m3 Vin
⎡ 1 + sR LC2 C C ⎤
⎡ 1 ⎤
V t2 = V t1 ⎢
⎥ − Ii ⎢
⎥
⎣ sR LC2 C C ⎦
⎣ sC C ⎦
60
(A.1)
(A.2)
⎡ 1
⎤
⎡ 1
⎤
1
+ g m2 ⎥ = V t1 [g m2 − sC C ] + V t2 ⎢
+
+ sC C ⎥
VOUT ⎢
⎣ ro2
⎦
⎣ R LC1 ro2
⎦
(A.3)
⎡ r + R L + g m2 ro2 R L ⎤
⎡ 1 ⎤
V t1 = VOUT ⎢ o2
⎥ − V t2 ⎢
⎥
g m2 R L ro2
⎣
⎦
⎣ ro2 g m2 ⎦
(A.4)
Combining A.2 and A.4 and solving for Vt1 gives
⎤
⎡ r + R L + g m2 ro2 R L ⎤ ⎡
sR LC2 C C
V t1 = VOUT ⎢ o2
⎥
⎥⎢
RL
⎣
⎦ ⎣ 1 + sR LC2 C C (1 + ro2 g m2 ) ⎦
(A.5)
⎡
⎤
R LC2
+ Ii ⎢
⎥
⎣1 + sR LC2CC (1 + ro2g m2 ) ⎦
Combining A.2 and A.4 and solving for Vt2 gives
⎤
⎡ r + R L + g m2 ro2 R L ⎤ ⎡
1 + sR LC2 C C
V t2 = VOUT ⎢ o2
⎥
⎥⎢
RL
⎣
⎦ ⎣ 1 + sR LC2 C C (1 + ro2 g m2 ) ⎦
(A.6)
⎡
⎤
R LC2 ro2g m2
− Ii ⎢
⎥
⎣1 + sR LC2C C (1 + ro2 g m2 ) ⎦
Combining A.3, A.5, and A.6 gives
VOUT
= R LC2
Ii
⎡
⎤
1 + sR LC1 C C
⎢
⎥
⎣ 1 + s (R LC1 + R LC2 )C C ⎦
(A.7)
Combining A.1 and A.7 gives
⎡
⎤
VOUT
1 + sR LC1 C C
= − g m3 R LC2 ⎢
⎥
Vin
⎣ 1 + s (R LC1 + R LC2 )C C ⎦
61
(A.8)
VITA
Steven Bunch was born in Knoxville, TN on April 17, 1980. He grew up about
36 miles west of Knoxville in the small town of Kingston, TN. He attended high school
in Kingston at Roane County High School where he focused mainly in science and math
and graduated with honors in May 1998. His career at the University of Tennessee began
in the fall of 1998 when he started his undergraduate study with a major in Electrical
Engineering. Once he was taking courses in his major, he realized that he really enjoyed
analog circuit design and decided to focus on it as a career choice. He also enrolled in
the engineering co-op program and worked at Honeywell Space Systems in Clearwater,
FL for a year while pursuing his degree. Steven graduated with a Bachelor of Science
degree from the University of Tennessee in May 2003, Cum Laude.
Once finished with his undergraduate degree, Steven began work at the Spallation
Neutron Source (SNS) in Oak Ridge, TN for a year. While at SNS he was mainly writing
software and there wasn’t any circuit design to be done. Therefore he decided to go back
and pursue his Master of Science degree at the University of Tennessee in Electrical
Engineering focusing on analog circuit design. While working on his MS at UT, Steven
worked as a Graduate Research Assistant under the direction of Dr. Benjamin J. Blalock.
After the completion of his Master of Science degree, Steven is planning to work
at Ametek in Oak Ridge, TN performing analog circuit design and the occasional digital
design.
62