Signal Integrity Analysis of High-Speed Single-Ended and Differential Vias
Zuowei Shen, Jian Tong
Avago Technologies
350 West Trimble, San Jose, CA, USA, 95131
Abstract
As data communication speed increases beyond 10 Gbps,
designing for optimal signal integrity becomes critical to
ensure reliable data. In the high speed board/package design,
designers are trying to eliminate or minimize all the
impedance mismatches along the high speed signal path.
When multilayer board is used to increase the signal density,
via structures are unavoidable to connect the signal, ground
and power supply traces on different layers. High speed via
transitions usually bring impedance discontinuities with them
which will cause signal reflections and distortions
compromising signal integrity. The deterioration of signal
integrity will generate additional jitter and decrease the data
eye opening ultimately jeopardizing the reliability of the data.
This paper addresses designing for signal integrity at 10 Gbps
by comparing the signal integrity of single ended and
differential through-hole vias for the designer. In each case,
the impedance mismatch at the via transition can be
minimized by optimizing a few parameters such as pitch size,
via diameter, via height, excess via stub, antipad size and
ground via locations. The impacts of these parameters are
investigated with the help for a full-wave electromagnetic
simulation and verified by measurements.
Introduction
Given the increasing data rate and increasing operating
frequency of the high speed digital systems, rules of thumb are
no longer valid for designers, especially for 3-D structures like
vias. A thorough understanding of the impacts of the via
parameters and valid modeling is the key to minimize the
impedance mismatch caused by the vertical vias. In modem
PCB design, there are several types of vias structures which
include through-hole via, blind via, buried via and microvias
[1]-[ 11]. This paper focuses on the most common and
inexpensive via structure, which is through-hole via. The
critical mechanical parameters are via diameter (drill size),
pad diameter, via height, pitch size, antipad on ground/power
plane, ground via configurations, ground via locations and the
excess via stub. Additionally, signal integrity performance
optimization is limited by design rules such as stack up,
minimal pitch size, minimal drill size and room available on
the PCB boards.
In this paper, the via performance is evaluated by
comparing the scattering parameters . and S22 in frequency
domain and TDR in time domain. A 3D EM SOLVER is used
to moeh relcin ineto los an copln ofthoser
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', via iS investigated,,by varying
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"Coaxial-like" single ended vias
In the printed circuit board, high speed signals are usually
carried by 50 ohm transmission lines. The most popular
transmission lines are microstrip line and stripline, which
carries quasi-TEM or TEM wave between the two conductors,
which are the trace and reference plane. When the signal trace
need to go to another layer, via is usually used as the layer
interconnect. The signal vias, whose impedance is usually 2535 ohm, can result in a significant impedance discontinuity.
The discontinuity comes from the field discontinuity at the
transition from the two conductor transmission lines to the
single radial transmission lines. There is no signal return path
at the via except at the power and ground plane. If we use
inductance and capacitance to characterize transmission lines,
the impedance mismatch comes from the dramatic capacitance
changes at the via transition.
Fig. 1. coaxial-like" via composed of one signal via and four
g
round vias
Some analysis has been done on designing coaxial like via
impedance and minimize the impedance
mismatch in [12]. This new structure creates vertical coaxial
transmission line and its impedance is controlled by the via
center signal
diameter and the distance from ground vias toreturn
vias. The surrounding vias provide the signal
path. An
g
inductance loop is formed between signal vias and the ground
vias. The capacitance is also homogeneous vertically because
the antipad is connected with the ground vias, so that there is
no dramatic capacitance change at the ground/power plane.
Vias designed with this technique can control the impedance
mismatch
400, which reduce the reflections at the via
ineconcwithin
sinfcaty
to control the via
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But unfortunately, due to the increasing component density
on the printed boards, the 5-via coaxial-like structure can not
always be applied due to the space limitation. For example,
when 0.2mm diameter through hole via is used as the signal
via, the distance between the signal and ground vias need to be
0.8 mm to match 50 ohm microstrip line. And this coaxial
structure will need 1.8mm x 1.8mm room on PCB, which is
not favored in the modem high density board design. One
trade off can be done is to keep the vertical channels, but
reduce the surrounding ground via numbers.
I I+ i 115 -
0.16 mm wide. The drill hole size is 0.2 mm. The distances
between the ground vias and the signal vias are all 0.8mm in
the test board shown in Fig.2. One through trace on the left
without via is measured as a reference to demonstrate the
performance deterioration caused by vias.
Fig.3 shows the insertion loss S21 for the above 5 fixtures.
We can see clearly that the more ground vias used, the more
transparent the via transaction is. The four via coaxial like via
structure introduces less signal attenuation than other
structures. And when there is only one ground via, we can see
there are obvious resonances and reflections when the high
speed signal goes through vias. The four vias performs like an
electrical wall, which both provides signal return path and
electrical shielding which reduces vertical couplings between
:
S(1,1) indB
es
m
~~~~0
-10
-20
-30
-40
-50
- sl_14
S11_3
70
Fig.2. Test board, (a) through trace (b) 4 ground vias (c) 3
ground vias (d) 2 ground vias (e) 1 ground via
O.OE+00
1.0E+10
1.5E+10
Frequency /Hz
IS (2,)1 in dB
0
(a) Measured return loss at SMA connector for different via
configurations
-0.5
S-Parameter Magnitude in dB
-1
m
5.OE+09
-1.5
-10
-2
t5 1
-2.5
-2.
-Xll
l
---------------
S123
S12_3
-4
-4.5
O.OE+00
nDI
-20
45
.......-...
s I 1t 3 -16. 62
O114 -1736
-30
1.OE+10
1.5E+10
SI
-35 11
Frequency / Hz
,I
.,,,
1S12_1
5.OE+09
-----
0
5
1----------l
10
t
Frequency I GH2
Fig.3. Measured insertion loss (S21) when different number of
ground vias are used
(b) Simulated return loss for different via configurations
Fig.2 shows the test board for the four via configurations
with different numbers of ground vias surrounding the signal
via. They are used to connect the traces on the top and bottom
layers. The board is 1mm thick, and the high speed trace is
Fig.4. Return loss (S1l) when different number of ground vias
are used
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also the antipad for signal vias. [13] A lot of simulations have
been done to demonstrate how those parameters affect the
impedance with the help of a full-wave 3-D electromagnetic
solver.
Fig. 6 shows the differential via structure and the
parameter definitions. The G-S-S-G configuration via
transition is assumed to use 0.2mm diameter drill vias and
0.45 mm via pad. The 6-layer board is 1.5mm thick, and the
differential trace has 0.3 mm trace width and 0.5 mm spacing.
First the common mode and differential mode return loss and
insertion loss at the via transition with and without the ground
vias are compared in Fig.7 and Fig.8. Both gap and via pitch is
0.8 mm in this model. In the simulation, mode 1 is differential
mode and mode 2 is common mode. By adding the two
ground vias, the attenuation for both common mode
IS2(2),1(2)1 and differential mode signals JS2(1),1(1)J are
reduced, and less reflection occur at the transition too.
Fig.4 shows the return loss S1l. Fig.4 (a) is the measured
results for the above test fixture, and the return loss measures
the reflection and impedance mismatch at the SMA
connectors. It includes both the reflection at the vias and the
cavity resonance between the SMA pair. Even though, it is
easy to observe that the impedance discontinuity is smaller for
the 36mm signal path where more ground via is used. Fig.4
(b) is the simulation results of the return loss of the via
transitions. The 3-D EM model includes the via transition and
6mm high speed trace at each side. The simulation can
compare the via structure return loss better by eliminating the
impedance discontinuity at the SMA connectors. When more
ground vias are applied, the return loss is better. For example,
at 5 GHz, the return loss is -14.8 dB for one ground via
structure, and -17.4 dB for four ground vias structure. Besides
the S-parameter in frequency domain, the TDR are simulated
and measured too. Fig. 5 presents the impedances of the via
transitions with different numbers of ground vias. As the
number of ground vias increases, the measured impedance
drop from 60 ohm to 52 ohm. The simulated impedances show
_____
TDR
#70ogo d i
65
lgdidMeasurementsPme
Simuia
tion
~60
E 55
50
1
2
3
4
6
0
5
-o~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Fig. 6. Differential via structure and parameter definition
#of ground vias
S-Parameter
Magnituide in d
Differential vias .
Differential traces are widely used in high speed circuit
designs. They are very attractive because of their inherent
noise and common mode signal rejection feature and good
EMI performance with the field canceling at far field. Smiliar
to single ended vias, when differential traces need to route
from one layer to another one, differential vias are needed as
the interconnect. Different from single ended via, the
differential signal on one of the differential via pair will
actually return at the other via. The impedance discontinuity
here actually is better than the case for single via transition.
But when the common mode signal is considered, again, we
will find that the return path is missing. One realistic way to
improve this discontinuity is to add two ground vias close to
the differential signal vias. In this configuration as shown in
Fig.6, the impedance of the via transition is determined by
several parameters, which include the via drill size, via pad
size, pitch, distance between ground via and signal vias, and
-7
-20
/
-f
v
s
,
5
10
S
2_2_//2
Frequency / GHz
15
20
Fig.7. Comparison of the return loss Si1 at the via transition
with and without ground vias
The gap between the signal vias and ground vias are then
varied from 1.2 mm to 0.6 mm to optimize the via impedance.
By comparing the scattering parameters, it is found that when
the ground vias are closer to the signal vias, the insertion loss
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1~ ~ . .
is smaller, and so is the reflection. The ground vias help both
differential and common mode impedance matching. But gap
between ground and signal vias is limited by the via pad
diameter and the clearance requirement, so 0.6mm is the
smallest value we can use. If smaller via pads are available,
some optimal distance between signal via and ground via will
be found, and when the gap is smaller than this distance, the
differential return loss will become worse. So in packaging
design allowing micro-vias, trade off need to be made between
differential and common mode impedance matching when
design the gap between signal vias and ground vias.
\pitch 1.2
-0.2 --------------------r-------------
r-------------------
-0.4--
-06 ----
S-Parameter Magnitlde in dB
-o
S2, 1I in dB
-0
-0.8
-
-
15
S2(2,1(2_)
0
5
0
15
20
Frequency J GHz
Fig. 10. Comparison of the differential mode insertion loss
S21 at the via transition with pitch variations
- __
S2 ) I (1)
(t
->
385
-0'
_
_
.
'2(2>,1(2):
S2t','1' ) t(2''1') nognd -15832
3
0
X5
1
After the gap is fixed, the pitch size is varied to optimize
Ithe differential impedance, which is very critical in the high
3:09
-1
speed circuit design. From Fig.9 and Fig.10, a clear trend is
found that smaller pitch size results in better impedance
match. The differential return loss is smaller than -20dB up to
18GHz when pitch is 0.6mm and 8 GHz when the pitch size is
1.2mm. The insertion loss also doubles when the pitch size
change from 0.6 mm to 1.2 mm. But even the pitch is
decreased to the minimum allowed pitch 0.6mm, the
differential impedance is still smaller than 100 ohm with this
stackup. The 100 ohm differential impedance should be
achieved when the pitch size is smaller than the differential
trace spacing, we can not use that smaller pitch size due to the
02
Frequency / GHz
Fig.8. Comparison of the insertion loss S21 at the via
transition with and without ground vias
ISi,11 in dB
_5
~~~~~~~~~~~~~~~~~~~~~~~pitch
h-r C,=06
_
pitch
1.2
S (2)t(2) in
pit_h
-5
-30
1---
10
Frequency I GHz
15
~-~~-~
-----~~ ---------------~~-~
~-~~[T
---
-1o~~~~~~~~~~~~~~~~--~~~~~ ptc
--
~~~~~~~~~~~~~~~-20
/
--
-65
O5
_L
tie-25
20
2-
Fig.9. Comparison of the differential mode return loss
the via transition with pitch variations
Si1 at
0
-3
__
5
10
Frequency / GHz
15
2C
Fig. 11. Comparison of the differential mode return loss 51 1 at
the via transition with pitch variations
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1
132(2)1(2)1
12
______IS
pitch T, l
pitch =9
-----
0.85
o
Conclusion
In this paper, approaches to optimize the single ended and
differential via transitions are described. When two or more
vias are placed around the signal via, the impedance
discontinuity at the single ended via transition can be
improved significantly. For differential vias, to make its
differential impedance 100 ohm, parameters like pitch size,
gap between ground vias and signal vias, via diameter, and
antipad need to be optimized carefully through modeling.
Usually, limited by the printed circuit fabrication design rules,
smaller gap and pitch size and larger antipad bring better
impedance match.
cknow ledgm ent
The authors would like to thank A. Engel, C. Cummings,
and S. Hart from Avago Technologies, Inc., San Jose, CA, for
valuable discussions and great support on this research; and M.
Teman from Avago Technologies for laying out PCBs with
the via designs presented in this paper.
Reference
1. Richard,
Weng Yew Chang;
See, ofKyetheYak; Chua,of Eng
via
Kee, "Comprehensive
Analysis
Impact
Design on High-Speed Signal Integrity," Electronics
Packaging Technology Conference, 2007, pp.262-266, 1012 Dec. 2007
2. T. Wang, R. F. Harrington, and J. R. Mautz, "Quasistatic
analysis of a microstrip via through a hole in a ground
plane," IEEE Trans. Microwave Theory Tech., vol. 36, pp.
1008-1013, June 1988.
3. S H. Hall, G. W. Hall, and J. A. McCall, High-Speed
System Digital Design. New York: Wiley, 2000.
4. C. Schuster and W. Fichtner, "Parasitic modes on PCBs
and their effects on EMC and signal integrity," IEEE
0.95
0o9
differential vias pairs. Ground vias can be used to separate
differential vias pairs to reduce the vertical coupling.
8
75_____
Frequency I GHz
Fig.12. Comparison of the common mode insertion loss S21 at
the via transition with pitch variations
Fig. 1ad f ows ho the via pitch Ffet the
common mode performance at thertion
Fromp the
common mode return loss and insertion loss comparison,
differential via with smaller pitch can provide us better
differential impedance matching but will have worse common
mode performance.
Based on the above investigation on how those geometric
parameters affect the via impedance, we get the conclusion
that usually on PCB, smaller pitch gives better differential
performance and worse common mode performance. We need
to do trade off when we optimize the differential via
impedance and also need to meet common mode return loss
specification. On package design, vias are much shorter, and
their hole size and pad size are smaller too. The discontinuity
at the via transition on package is not as significant as those on
PCB, but the circuit density brings other potential issues at
vias.
Other possible high speed via issues
There are also other parameters that can affect the
reflection and attenuation at the via transition. For example,
longer via on multilayer PCB board will introduce more
discontinuity with larger insertion loss and reflection. Smaller
drill size and via pad can match the narrow differential trace
better but costs more. The via antipad, also called clearance
hole, is another key parameter designers need to optimize
during the design phase. Appropriate antipad usually results in
better impedance matching for both single ended and
differential vias by reducing the capacitance. Also, we need to
pay attention to the via stub, and try to eliminate it or keep it
short. The via transition stub usually looks capacitive when it
is short. The worst case is when the stub is quarter wavelength
at an important frequency, and the stub performs like a short
circuit at that frequency, then the reflected signal will cancel
OUt the original signals. In this way, a resonance shows up at
this critical frequency. [14] In package design where vias are
close, crosstalk may come from the vertical coupling between
Trans. Electromagn. Compat., vol.43, no. 4, pp. 416-425,
Nov. 2001.
5 J S. Pak and J. Kim, "3 GHz through-hole signal via
model considering power/ground plane resonance coupling
and via neck effect," in Proc. Electron. Compon. Technol.
Conf., 2003, pp. 1017-1022.
6. J. Kim, J. Kim, M. D. Rotaru, K. C. Chong, and M. K.
Iyer, "Via and reference discontinunity impact on highspeed signal integrity," in Proc. IEEE Int. Symp.
Electromagn. Compat., Aug. 2004, vol. 2, pp. 583-587.
7. J. S. Pak, J. Lee, H. Kim, and J. Kim, "Prediction and
verifcation of power/ground edge radiation excited by
through-hole signal via through balanced TLM and via
coupling model," in Proc. IEEE 12th Top. Meet. Electr.
Perform. Electron. Packag. 27-29, Oct. 2003, pp. 181-184.
8. J. S. Pak, M. Aoyagi, K. Kikuchi, and J. Kim, "Band-stop
effect of power/ground plane on through-hole signal via in
multilayer PCB," JEICE Trans. Electron., vol. 89-C, no. 4,
pp. 55 1-559, Apr.2006.
9M P
i
. jvcJ.
Yu'.Mljoi,"nlsso
Capacitance in Arbitrary Multilayer PCBs", IEEE Trans.
Elcrmg.Cma. o.4,n.3 p 2-2,Ag
20
207
2008 10th Electronics Packaging Technology Conference
69
Authorized licensed use limited to: MONTANA STATE UNIV BOZEMAN. Downloaded on January 10, 2010 at 18:40 from IEEE Xplore. Restrictions apply.
10. T. Wang et al., "The excess capcitance of a microstrip via
in a dielectric substrate," IEEE Trans. Comput.-Aided
Des., vol. 9, no. 1, pp. 48-56, Jan. 1990.
11. T. Wang et al., "Quasi-static analysis of a microstrip via
through a hole in a ground plane," IEEE Trans. Microw.
Theory Tech., vol. 36, no. 6, pp. 1007-1013, Jun. 1988.
12. Thomas Neu, "Designing controlled-impedance vias", pp.
67-72, EDN, Oct 2,2003
13. Lawrence Williams, Steve Rouselle, Bryan Boots,
"Circuit-board design for 10-Gbit XFP optical module",
pp.63 -70, EDN, May 29, 2003
14. Zaw Zaw Oo; Liu Enxiao; Wei Xing Chang; Li Erping;
Chua Eng Kee; Li Le-Wei, "Novel Co-Simulation Method
for Analysis of Power Integrity and EMI in Electronic
Packages with Large Number of Power/ground Vias,"
Electronics Packaging Technology Conference, 2007,
pp.421-424, 10-12 Dec. 2007
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