TLE2141-Q1
SLOS525 – SEPTEMBER 2011
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Excalibur™ LOW-NOISE HIGH-SPEED PRECISION OPERATIONAL AMPLIFIERS
Check for Samples: TLE2141-Q1
FEATURES
1
•
•
2
•
•
•
•
Qualified for Automotive Applications
Low Noise
– 10 Hz … 15 nV/√Hz
– 1 kHz … 10.5 nV/√Hz
10000-pF Load Capability
20-mA Min Short-Circuit Output Current
27-V/μs Slew Rate (Min)
High Gain-Bandwidth Product … 5.9 MHz
•
•
•
•
•
Low VIO … 500 μV (Max) at 25°C
Single or Split Supply … 4 V to 44 V
Fast Settling Time
– 340 ns to 0.1%
– 400 ns to 0.01%
Saturation Recovery … 150 ns
Large Output Swing …
VCC– + 0.1 V to VCC+ – 1 V
DESCRIPTION
The TLE2141-Q1 device is a high-performance, internally compensated operational amplifier built using the
Texas Instruments complementary bipolar Excalibur™ process. It is a pin-compatible upgrade to standard
industry products.
The design incorporates an input stage that simultaneously achieves low audio-band noise of 10.5 nV/√Hz with a
10-Hz 1/f corner and symmetrical 40-V/μs slew rate typically with loads up to 800 pF. The resulting low distortion
and high power bandwidth are important in high-fidelity audio applications. A fast settling time of 340 ns to 0.1%
of a 10-V step with a 2-kΩ/100-pF load is useful in fast actuator/positioning drivers. Under similar test conditions,
settling time to 0.01% is 400 ns.
The device is stable with capacitive loads up to 10 nF, although the 6-MHz bandwidth decreases to 1.8 MHz at
this high loading level. As such, the TLE2141-Q1 is useful for low-droop sample-and-holds and direct buffering of
long cables, including 4-mA to 20-mA current loops.
The special design also exhibits an improved insensitivity to inherent integrated circuit component mismatches as
is evidenced by a 500-μV maximum offset voltage and 1.7-μV/°C typical drift. Minimum common-mode rejection
ratio and supply-voltage rejection ratio are 85 dB and 90 dB, respectively.
Device performance is relatively independent of supply voltage over the ±2-V to ±22-V range. Inputs can operate
between VCC– – 0.3 V to VCC+ – 1.8 V without inducing phase reversal, although excessive input current may flow
out of each input exceeding the lower common-mode input range. The all-npn output stage provides a nearly
rail-to-rail output swing of VCC– – 0.1 V to VCC+ – 1 V under light current-loading conditions. The device can
sustain shorts to either supply since output current is internally limited, but care must be taken to ensure that
maximum package power dissipation is not exceeded.
The TLE2141-Q1 device can also be used as a comparator. Differential inputs of VCC± can be maintained without
damage to the device. Open-loop propagation delay with TTL supply levels is typically 200 ns. This gives a good
indication as to output stage saturation recovery when the device is driven beyond the limits of recommended
output swing.
The TLE2141-Q1 device is available in industry-standard 8-pin package. The device is characterized for
operation from –40°C to 125°C.
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
PACKAGE
SOIC – D (8 pin)
Reel of 2500
ORDERABLE PART NUMBER
TLE2141QDRQ1
TOP-SIDE MARKING
2141Q
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Excalibur is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TLE2141-Q1
SLOS525 – SEPTEMBER 2011
www.ti.com
SYMBOL
OFFSET N1
IN+
+
IN-
-
OUT
OFFSET N2
D PACKAGE
(TOP VIEW)
OFFSET N1
ININ+
VCC-
1
8
2
7
3
6
4
5
NC
VCC+
OUT
OFFSET N2
NC – No internal connection
2
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Copyright © 2011, Texas Instruments Incorporated
Copyright © 2011, Texas Instruments Incorporated
OFFSET N2
OFFSET N1
IN +
IN -
Q1
R2
Q3
R1
Q2
Q4
D1
Q7
Q6
R3
R5
Q12
Q11
R6
Q10
Q9
C1
Q5 Q8
R4
Q14
D2
R9
VCC -
Q18
Q19
R12
Q20
Q21
C4
24
8
4
1
Resistors
Diodes
Capacitors
Epi-FET
TLE2141-Q1
46
COMPONENT
R13
D4
C3
DEVICE COMPONENT COUNT
R11
C2
D3
Q22
R14
Q24
D5
Q25
R16
R15
Q23
Q29
D7
D6
Q28
R17
Q27
Q26
R18
D8
R20
Q33
Q32
Q31
Q30
R19
R22
Q35
Q36
R23
Q34
R21
Q37
OUT
R24
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Transistors
Q17
R10
Q16
Q15
R8
Q13
R7
VCC +
TLE2141-Q1
SLOS525 – SEPTEMBER 2011
Figure 1. EQUIVALENT SCHEMATIC
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SLOS525 – SEPTEMBER 2011
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
(2)
VALUE
UNIT
VCC+
Supply voltage
22
V
VCC–
Supply voltage
–22
V
VID
Differential input voltage (3)
±44
V
VI
Input voltage range (any input)
VCC+ to (VCC– – 0.3)
V
II
Input current (each input)
±1
mA
IO
Output current
±80
mA
Total current into VCC+
80
mA
80
mA
Total current out of VCC–
Duration of short-circuit current at (or below) 25°C (4)
θJA
Package thermal impedance (5)
TA
Tstg
(6)
Unlimited
97.1
°C/W
Operating free-air temperature range
–40 to 125
°C
Storage temperature range
–65 to 150
°C
260
°C
D package (8 pin)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
(4)
(5)
(6)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential voltages, are with respect to the midpoint between VCC+ and VCC–.
Differential voltages are at IN+ with respect to IN–. Excessive current flows, if input, are brought below VCC– – 0.3 V.
The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
VCC±
Supply voltage
VIC
Common-mode input voltage
TA
Operating free-air temperature
4
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VCC = 5 V
VCC± = ±15 V
MIN
MAX
UNIT
±2
±22
V
0
2.7
–15
12.7
–40
125
V
°C
Copyright © 2011, Texas Instruments Incorporated
TLE2141-Q1
SLOS525 – SEPTEMBER 2011
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ELECTRICAL CHARACTERISTICS
VCC = 5 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
αVIO
Temperature coefficient of
input offset voltage
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIO
Input offset current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
IIB
Input bias current
VO = 2.5 V, RS = 50 Ω, VIC = 2.5 V
VICR
Common-mode input
voltage range
TA
(1)
MIN
25°C
25°C
8
–0.8
–0.3 to
3.2
0 to 2.7
–0.3 to
2.9
3.9
4.1
3.8
4
IOH = –15 mA
3.2
3.7
IOH = –100 μA
3.75
RS = 50 Ω
25°C
Full range
25°C
μA
V
V
75
125
150
225
1.2
1.4
IOL = 100 μA
200
Full range
250
IOL = 10 mA
VIC = ±2.5 V, RL = 2 kΩ,
VO = 1 V to 1.5 V
nA
3.25
IOL = 15 mA
IOL = 1 mA
μV
3.65
IOL = 150 μA
IOL = 1.5 mA
–2
–2.3
Full range
Full range
100
250
25°C
UNIT
μV/°C
1.7
Full range
IOH = –10 mA
Low-level output voltage
1400
0 to 3
IOH = –1 mA
VOL
225
2100
Full range
25°C
IOH = –1.5 mA
High-level output voltage
MAX
Full range
IOH = –150 μA
VOH
TYP
1.25
25°C
50
Full range
5
220
mV
V
mV
V
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
70
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
f = 1 MHz
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
ICC
Supply current
VO = 2.5 V, No load, VIC = 2.5 V
(1)
25°C
25°C
85
Full range
80
25°C
90
Full range
85
25°C
118
dB
106
3.4
Full range
V/mV
dB
4.4
4.6
mA
Full range is –40°C to 125°C.
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OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
TYP
MAX
UNIT
SR+
Positive slew rate
AVD = –1, RL = 2 kΩ , CL = 500 pF
45
V/μs
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ (1), CL = 500 pF
42
V/μs
To 0.1%
0.16
To 0.01%
0.22
ts
Settling time
AVD = –1, 2.5-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
Vn(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.92
f = 1 kHz
0.5
THD+N
Total harmonic distortion plus noise
B1
f = 10 Hz
15
f = 1 kHz
10.5
VO = 1 V to 3 V, RL = 2 kΩ (1), AVD = 2,
f = 10 kHz
(1)
(1)
Unity-gain bandwidth
RL = 2 kΩ , CL = 100 pF
Gain-bandwidth product
RL = 2 kΩ (1), CL = 100 pF (1), f = 100 kHz
(1)
BOM
Maximum output-swing bandwidth
VO(PP) = 2 V, RL = 2 kΩ , AVD = 1
φm
Phase margin at unity gain
RL = 2 kΩ (1), CL = 100 pF (1)
(1)
6
0.0052
μs
nV/√Hz
μV
pA/√Hz
%
5.9
MHz
5.8
MHz
660
kHz
57
°
RL and CL terminated to 2.5 V.
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TLE2141-Q1
SLOS525 – SEPTEMBER 2011
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ELECTRICAL CHARACTERISTICS
VCC = ±15 V, at specified free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
VIC = 0, RS = 50 Ω
αVIO
Temperature coefficient of
input offset voltage
VIC = 0, RS = 50 Ω
IIO
Input offset current
VIC = 0, RS = 50 Ω
IIB
Input bias current
VIC = 0, RS = 50 Ω
VICR
Common-mode input
voltage range
TA
(1)
MIN
25°C
200
Full range
25°C
7
–0.7
25°C
–15 to –15.3 to
13
13.2
Full range
–15 to –15.3 to
12.7
12.9
13.8
14.1
13.7
14
Maximum positive peak
output voltage swing
IO = –15 mA
13.1
13.7
IO = –100 μA
13.7
25°C
IO = –1 mA
Full range
IO = –10 mA
–1.5
nA
μA
V
V
13.6
–14.7
–14.9
–14.5
–14.8
IO = 15 mA
–13.4
–13.8
IO = 100 μA
–14.6
IO = 1.5 mA
Maximum negative peak
output voltage swing
μV
13.1
IO = 150 μA
VOM–
100
–1.8
Full range
UNIT
μV/°C
250
25°C
IO = –1.5 mA
900
1.7
Full range
RS = 50 Ω
MAX
1700
Full range
IO = –150 μA
VOM+
TYP
25°C
IO = 1 mA
Full range
V
–14.5
–13.4
IO = 10 mA
25°C
100
Full range
20
450
AVD
Large-signal differential
voltage amplification
ri
Input resistance
25°C
65
MΩ
ci
Input capacitance
25°C
2.5
pF
zo
Open-loop output impedance
30
Ω
VO = ±10 V, RL = 2 kΩ
f = 1 MHz
25°C
CMRR
Common-mode rejection ratio
VIC = VICR(min), RS = 50 Ω
kSVR
Supply-voltage rejection ratio
(ΔVCC±/ΔVIO)
VCC± = ±2.5 V to ±15 V, RS = 50 Ω
IOS
Short-circuit output current
VO = 0
ICC
Supply current
VO = 0, No load, VIC = 2.5 V
(1)
VID = 1 V
VID = –1 V
25°C
85
Full range
80
25°C
90
Full range
85
25°C
25°C
108
dB
106
–25
–50
20
31
3.5
Full range
V/mV
dB
mA
4.5
4.7
mA
Full range is –40°C to 125°C.
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OPERATING CHARACTERISTICS
VCC = ±15 V, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SR+
Positive slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
27
45
V/μs
SR–
Negative slew rate
AVD = –1, RL = 2 kΩ, CL = 100 pF
27
42
V/μs
To 0.1%
0.34
To 0.01%
0.4
ts
Settling time
AVD = –1, 10-V step
Vn
Equivalent input noise voltage
RS = 20 Ω
Vn(PP)
Peak-to-peak equivalent input
noise voltage
f = 0.1 Hz to 1 Hz
0.48
f = 0.1 Hz to 10 Hz
0.51
In
Equivalent input noise current
f = 10 Hz
1.89
f = 1 kHz
0.47
THD+N
Total harmonic distortion plus noise
VO(PP) = 20 V, RL = 2 kΩ, AVD = 10, f = 10 kHz
0.01
B1
Unity-gain bandwidth
RL = 2 kΩ, CL = 100 pF
f = 10 Hz
15
f = 1 kHz
10.5
μs
nV/√Hz
μV
pA/√Hz
%
6
MHz
Gain-bandwidth product
RL = 2 kΩ, CL = 100 pF, f = 100 kHz
5.9
MHz
BOM
Maximum output-swing bandwidth
VO(PP) = 20 V, AVD = 1, RL = 2 kΩ, CL = 100 pF
668
kHz
φm
Phase margin at unity gain
RL = 2 kΩ, CL = 100 pF
58
°
8
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
VIO
Input offset voltage
Distribution
Figure 2
IIO
Input offset current
vs Free-air temperature
Figure 3
vs Common-mode input voltage
Figure 4
vs Free-air temperature
Figure 5
vs Supply voltage
Figure 6
vs Free-air temperature
Figure 7
vs Output current
Figure 8
vs Settling time
Figure 10
vs Supply voltage
Figure 6
vs Free-air temperature
Figure 7
IIB
VOM+
VOM–
Input bias current
Maximum positive peak output voltage
Maximum negative peak output voltage
vs Output current
Figure 9
vs Settling time
Figure 10
VO(PP)
Maximum peak-to-peak output voltage
vs Frequency
Figure 11
VOH
High-level output voltage
vs Output current
Figure 12
VOL
Low-level output voltage
vs Output current
Figure 13
Phase shift
vs Frequency
Figure 14
vs Frequency
Figure 14
AVD
Large-signal differential voltage amplification
vs Free-air temperature
Figure 15
zo
Closed-loop output impedance
vs Frequency
Figure 16
IOS
Short-circuit output current
vs Free-air temperature
Figure 17
CMRR
Common-mode rejection ratio
vs Frequency
Figure 18
vs Free-air temperature
Figure 19
vs Frequency
Figure 20
vs Free-air temperature
Figure 21
vs Supply voltage
Figure 22
vs Free-air temperature
Figure 23
kSVR
Supply-voltage rejection ratio
ICC
Supply current
Vn
Equivalent input noise voltage
vs Frequency
Figure 24
Vn
Input noise voltage
Over a 10-second period
Figure 25
In
Noise current
vs Frequency
Figure 26
THD+N
Total harmonic distortion plus noise
vs Frequency
Figure 27
SR
Slew rate
vs Free-air temperature
Figure 28
vs Load capacitance
Figure 29
Noninverting large signal
vs Time
Figure 30
Inverting large signal
vs Time
Figure 31
Small signal
vs Time
Figure 32
Unity-gain bandwidth
vs Load capacitance
Figure 33
Gain margin
vs Load capacitance
Figure 34
Phase margin
vs Load capacitance
Figure 35
Pulse response
B1
φm
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INPUT OFFSET CURRENT
vs
FREE-AIR TEMPERATURE
TLE2141
DISTRIBUTION OF
INPUT OFFSET VOLTAGE
20
24
18
IIIO
IO − Input Offset Current − nA
Percentage of Units − %
20
236 Units Tested From 1 Wafer Lot
VCC ± = ± 15 V
TA = 25°C
P Package
16
12
8
4
VO = 0
VIC = 0
16
14
12
10
VCC ± = ± 2.5 V
8
6
VCC ± = ± 15 V
4
2
0
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
0
−800
400
0
−400
VIO − Input Offset Voltage − µV
800
Figure 2.
Figure 3.
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT BIAS CURRENT
vs
COMMON-MODE INPUT VOLTAGE
−1000
0
VCC ± = ± 2.5 V
VO = 0
VIC = 0
−0.4
−0.6
TA = 125°C
−0.8
TA = 25°C
−1
−1.2
−1.4
−3
TA = − 55°C
−2.5 −2
−1.5 −1 −0.5
0
0.5
VIC − Common-Mode Input Voltage − V
Figure 4.
10
IIIB
IB − Input Bias Current − nA
uA
IIIB
IB − Input Bias Current − µA
−0.2
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1
−900
VCC ± = ± 2.5 V
−800
−700
VCC ± = ± 15 V
−600
−500
−75 −50 −25
0
25
50 75 100 125 150
TA − Free-Air Temperature − °C
Figure 5.
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MAXIMUM PEAK OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
MAXIMUM PEAK OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
15
RL = 2 kΩ
TA = 25°C
18
VCC ± = ± 15 V
V OM − Maximum Peak Output Voltage − V
V OM − Maximum Peak Output Voltage − V
24
12
VOM +
6
0
−6
VOM −
−12
−18
3
6
9
12
15
18
21
RL = ∞
14.2
VOM +
13.8
RL = 2 kΩ
−13.8
−14.2
RL = 2 kΩ
VOM −
−14.6
RL = ∞
−15
−75 −50 −25
0
25
50 75 100 125 150
TA − Free-Air Temperature − °C
− 24
0
14.6
24
VCC ± − Supply Voltage − V
Figure 6.
Figure 7.
MAXIMUM NEGATIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
14.6
VCC ± = ± 15 V
14.4
14.2
TA = 125°C
14
TA = 25°C
TA = − 55°C
13.8
13.6
−0.1
−0.4
−1
−4
−10
IO − Output Current − mA
Figure 8.
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− 40
−100
V OM − − Maximum Negative Peak Output Voltage − V
V OM + − Maximum Positive Peak Output Voltage − V
MAXIMUM POSITIVE PEAK
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
−13.4
VCC ± = ± 15 V
−13.6
−13.8
TA = 125°C
−14
−14.2
TA = − 55°C
−14.4
TA = 25°C
−14.6
−14.8
− 15
0.1
0.4
1
4
10
40
100
IO − Output Current − mA
Figure 9.
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MAXIMUM PEAK OUTPUT VOLTAGE
vs
SETTLING TIME
AVD = −1
VCC ± = ± 15 V
TA = 25°C
10
7.5
0.1%
0.01%
5
2.5
Rising
0
Falling
−2.5
0.01%
−5
0.1%
−7.5
−10
−12.5
0
100
200
300
400
500
V O(PP) − Maximum Peak-to-Peak Output Voltage − V
VVOM
OM − Maximum Peak Output Voltage − V
12.5
MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE
vs
FREQUENCY
ts − Settling Time − ns
30
VCC ± = ± 15 V
RL = 2 kΩ
25
TA = 25°C
20
TA = 125°C
15
10
TA = − 55°C
5
0
100 k
400 k
1M
4M
10 M
f − Frequency − Hz
Figure 10.
Figure 11.
HIGH-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
4.6
1400
VCC = 5 V
VOL
V
OL − Low-Level Output Voltage − mV
V OH − High-Level Output Voltage − V
VCC = 5 V
4.4
TA = 125°C
4.2 TA = 25°C
4 TA = − 55°C
3.8
3.6
1200
TA = 125°C
1000
800
600
TA = 25°C
400
200
TA = − 55°C
3.4
−0.1
−1
−10
IO − Output Current − mA
Figure 12.
12
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−100
0
0.1
1
10
100
IO − Output Current − mA
Figure 13.
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LARGE-SIGNAL DIFFERENTIAL
VOLTAGE AMPLIFICATION
vs
FREE-AIR TEMPERATURE
0°
110
20°
100
40°
90
60°
80 Phase Shift
80°
70
100°
60
120°
AVD
50
140°
40
160°
180°
30
VCC ± = ± 15 V
RL = 2 kΩ
CL = 100 pF
TA = 25°C
20
10
0
200°
220°
240°
− 10
1
10
100
1k
10 k 100 k
f − Frequency − Hz
1M
140
VCC ± = ± 15 V
VO = ± 10 V
AAVD
VD − Large-Signal Differential
Voltage Amplification − dB
120
Phase Shift
AAVD
VD − Large-Signal Differential
Voltage Amplification − dB
LARGE-SIGNAL DIFFERENTIAL VOLTAGE
AMPLIFICATION AND PHASE SHIFT
vs
FREQUENCY
RL = 10 kΩ
120
RL = 2 kΩ
100
260°
10 M
80
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 14.
Figure 15.
SHORT-CIRCUIT OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
CLOSED-LOOP OUTPUT IMPEDANCE
vs
FREQUENCY
60
100
VCC ± = ± 15 V
VO = 0
IOS − Short-Circuit Output Current − mA
z o − Closed-Loop Output Impedance − Ω
30 Ω
10
1
AVD = 100
0.1
AVD = 10
AVD = 1
0.01
0.001
1k
10 k
100 k
f − Frequency − Hz
Figure 16.
Copyright © 2011, Texas Instruments Incorporated
1M
10 M
50
VID = 1
40
30
VID = − 1
20
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 17.
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COMMON-MODE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
120
VCC ± = ± 15 V
TA = 25°C
CMRR − Common-Mode Rejection Ratio − dB
CMRR − Common-Mode Rejection Ratio − dB
140
120
100
80
60
40
20
0
100
1k
100 k
10 k
f − Frequency − Hz
VIC = VICRmin
VCC = 5 V
116
112
108
VCC ± = ± 15 V
104
100
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
1M
Figure 18.
Figure 19.
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREQUENCY
SUPPLY-VOLTAGE REJECTION RATIO
vs
FREE-AIR TEMPERATURE
110
kkSVR
SVR − Supply-Voltage Rejection Ratio − dB
kkSVR
SVR − Supply-Voltage Rejection Ratio − dB
160
140
kSVR +
120
kSVR −
100
80
60
40
20 VCC ± = ± 2.5 V to ± 15 V
TA = 25°C
0
10
100
1k
10 k
100 k
f − Frequency − Hz
Figure 20.
14
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1M
10 M
VCC ± = ± 2.5 V to ± 15 V
108
106
104
102
100
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 21.
Copyright © 2011, Texas Instruments Incorporated
TLE2141-Q1
SLOS525 – SEPTEMBER 2011
www.ti.com
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4
3.8
VO = 0
No Load
TA = 125°C
IIDD
CC − Supply Current − mA
IIDD
CC − Supply Current − mA
3.6
3.5
TA = 25°C
3
TA = − 55°C
2.5
VCC ± = ± 15 V
3.4
VCC ± = ± 2.5 V
3.2
3
VO = 0
No Load
2.8
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
2
0
4
8
12
16
20
|VCC ±| − Supply Voltage − V
24
Figure 22.
Figure 23.
INPUT NOISE VOLTAGE
OVER A 10-SECOND PERIOD
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
750
VCC ± = ± 15 V
RS = 20 Ω
VCC ± = ± 15 V
f = 0.1 to 10 Hz
TA = 25°C
500
200
Input Noise Voltage − nV
Vn − Equivalent Input Noise Voltage − nV/ Hz
250
TA = − 55°C
150
TA = 125°C
100
TA = 25°C
50
250
0
−250
−500
−750
0
1
10
100
f − Frequency − Hz
Figure 24.
Copyright © 2011, Texas Instruments Incorporated
1k
10 k
0
2
4
6
8
10
t − Time − s
Figure 25.
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NOISE CURRENT
vs
FREQUENCY
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
FREQUENCY
6
TA = − 55°C
4
TA = 25°C
2
TA = 125°C
0
1
10
100
1k
10 k
f − Frequency − Hz
THD + N − Total Harmonic Distortion + Noise − %
In − Noise Current − pA/ Hz
8
1%
VO(PP) = 20 V
VCC ± = ± 15 V
TA = 25°C
0.1%
AV = 10
RL = 600 Ω
AV = 10
RL = 2 kΩ
0.001%
10
100
100 k
SLEW RATE
vs
LOAD CAPACITANCE
60
50
50
40
40
SR −
30
20
VCC ± = ± 15 V
AVD = − 1
RL = 2 kΩ
CL = 500 pF
SR − Slew Rate − V/ µ s
SR +
SR − Slew Rate − V/ µ s
1k
10 k
f − Frequency − Hz
Figure 27.
SLEW RATE
vs
FREE-AIR TEMPERATURE
SR+
30
20
SR −
10 VCC ± = ± 15 V
AVD = − 1
TA = 25°C
0
−75 −50 −25
0
25
50
75 100 125 150
TA − Free-Air Temperature − °C
Figure 28.
16
AV = 100
RL = 2 kΩ
0.01%
Figure 26.
10
AV = 100
RL = 600 Ω
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0
0.01
0.1
1
CL − Load Capacitance − nF
10
Figure 29.
Copyright © 2011, Texas Instruments Incorporated
TLE2141-Q1
SLOS525 – SEPTEMBER 2011
www.ti.com
NONINVERTING
LARGE-SIGNAL
PULSE RESPONSE
INVERTING
LARGE-SIGNAL
PULSE RESPONSE
15
15
TA = 125°C
TA = 25°C
10
TA = 25°C
5
VO − Output Voltage − V
VO
V
VO
O − Output Voltage − V
10
TA = − 55°C
0
TA = − 55°C
−5
TA = 25°C
VCC ± = ± 15 V
AVD = 1
RL = 2 kΩ
CL = 300 pF
−10
TA = − 55°C
TA = 125°C
5
0
TA = 125°C
TA = 25°C
−5
VCC ± = ± 15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
−10
TA = 125°C
−15
−15
0
2
1
3
4
5
0
1
2
t − Time − µs
t − Time − µs
Figure 31.
4
5
UNITY-GAIN BANDWIDTH
vs
LOAD CAPACITANCE
100
7
VCC ± = ± 15 V
RL = 2 kΩ
B
B1
1 − Unity-Gain Bandwidth − MHz
TA = − 55°C
50
0
VCC ± = ± 15 V
AVD = −1
RL = 2 kΩ
CL = 300 pF
TA = 25°C
−50
3
Figure 30.
SMALL-SIGNAL
PULSE RESPONSE
V
VO
O − Output Voltage − mV
TA = − 55°C
6
TA = 25°C
5
TA = 125°C
4
3
2
−100
0
400
800
t − Time − ns
1200
1600
1
10
100
1000
10000
CL − Load Capacitance − pF
Figure 32.
Copyright © 2011, Texas Instruments Incorporated
Figure 33.
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PHASE MARGIN
vs
LOAD CAPACITANCE
GAIN MARGIN
vs
LOAD CAPACITANCE
14
12
TA = − 55°C
8
6
TA = 125°C
50°
TA = 125°C
40°
30°
10°
2
TA = 25°C
100
1000
CL − Load Capacitance − pF
Figure 34.
18
TA = 25°C
20°
4
0
10
TA = − 55°C
60°
φ m − Phase Margin
Gain Margin − dB
10
70°
VCC ± = ± 15 V
AVD = 1
RL = 2 kΩ to ∞
VO = − 10 V to 10 V
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10000
VCC ± = ± 15 V
RL = 2 kΩ
0°
10
100
1000
CL − Load Capacitance − pF
10000
Figure 35.
Copyright © 2011, Texas Instruments Incorporated
TLE2141-Q1
SLOS525 – SEPTEMBER 2011
www.ti.com
APPLICATION INFORMATION
Input Offset Voltage Nulling
The TLE2141-Q1 offers external null pins that can be used to further reduce the input offset voltage. If this
feature is desired, connect the circuit of Figure 36 as shown. If external nulling is not needed, the null pins may
be left unconnected.
IN+
IN-
3
2
+
6
OUT
–
5 5 kW 1
OFFSET N2
OFFSET N1
1 kW
VCC– (split supply)
GND (single supply)
Figure 36. Input Offset Voltage Null Circuit
Copyright © 2011, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TLE2141QDRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
8
2500
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-1-260C-UNLIM
(4)
-40 to 125
2141Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLE2141-Q1 :
• Catalog: TLE2141
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Enhanced Product: TLE2141-EP
• Military: TLE2141M
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
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