Hardware and Architecture - McGraw-Hill

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Chapter 1
Hardware and
Architecture
by Todd M. Warble
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n an industry accustomed to routers that utilize monolithic code bases and general
purpose CPUs, the Juniper Networks design team built a router that is capable of
handling the demands of Internet backbone traffic; yet it is also able to precisely control
traffic to a degree sufficient for cutting-edge applications. An innovative design approach,
backed by some of the best engineers in the business, has provided the Internet world
with a stable, line-rate router. By segmenting the functions of a router and attacking each
function with a purpose-built, high-performance piece of machinery, Juniper Networks
has redefined how routing is accomplished on the Internet.
Fundamental to Juniper Networks’ router design is the idea that the functions of a
router can be split into two distinct parts: one portion for handling routing and control
operations and another for forwarding packets. By separating these two operations, the
router hardware can be designed and optimized to perform each function well. This
chapter concentrates on this hardware design approach and the architectural characteristics
of Juniper Networks routers.
I
System Evolution
The various models of the Juniper Networks router are built consistently with respect
to system architecture and software. Each product builds upon the foundation that the
previous products have supported and proven, allowing a single coherent product line
to be enhanced with every new generation of code and hardware. From the release of the
M40 router in August 1998, the architecture of the Juniper Networks router has remained
essentially the same.
The value of such a consistent approach across all platforms is enormous. By enabling
software compatibility across all platforms, software upgrades and bug fixes are
immediately available across the entire product line. Commonality in system hardware
architecture allows new systems to be built on a proven foundation. New hardware
upgrades are also available to the entire line of routers with minimal individual
system concerns.
Router Functionality
The functions of a router can be split into two distinct areas. In essence, a router is required
to handle general routing operations and forward packets.
The portion of the Juniper Networks router that is designed to handle the general
routing operations is referred to as the Routing Engine (RE). The RE is designed to handle all
the routing protocols (Open Shortest Path First, OSPF; Intermediate System to Intermediate
System, ISIS; Border Gateway Protocol, BGP; and so on), user interaction, system
management, and OAM&P (Operations, Administration, Maintenance & Provisioning).
The second portion of the Juniper Networks router is referred to as the Packet
Forwarding Engine (PFE) and is specifically designed to handle the forwarding of
packets across the router. A representation of how the router is split into two distinct
areas is shown in Figure 1-1.
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Figure 1-1.
Hardware and Architecture
A graphical view of the RE/PFE relationship
The fundamental philosophy of this “divide and conquer” architecture is prevalent
throughout the Juniper Networks routers. Let’s begin by taking a look at each portion
of the router architecture.
Routing Engine
The RE is designed to be a robust, quick, PC-like host whose responsibility includes
operation of routing protocols, troubleshooting and provisioning operations, and
general management of the router. Its hardware consists of the following:
■ Intel Pentium-based compact Peripheral Component Interconnect
(PCI) platform
■ Non-rotating compact flash drive (often called a RAM disk)
■ Standard rotating hard drive
■ Removable media drive
The JUNOS operating system software resides on the compact flash drive, with
an alternate copy residing on the system hard drive. This is one of many reasons that
Juniper Networks routers include a hard drive as part of the RE. As you will see in
Chapter 2, the hard-drive copy serves as a backup copy of the operating system for
disaster-recovery situations.
The RE is primarily responsible for the protocol intelligence of the router. It is
therefore responsible for creating a routing table, which consists of all routes learned by
all protocols running on the router. The RE parses the routing table to generate a subset
of routes that will be used for all forwarding purposes, placing them in the forwarding
table. The forwarding table is in turn fed to the PFE so that proper decisions can be
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made for packet handling. As route updates come into the RE via the routing protocols,
the PFE’s forwarding table is incrementally updated.
The incremental update of route changes is important. Rather than flushing the
entire forwarding table and then replacing it with the new one, the RE sends a simple
add, delete, or modify message to update the forwarding table. When routing on the
Internet, it is common to see routing tables that consist of 100,000 routes or more. If a
single route were to disappear, it is obviously more simple to remove the single route.
The remaining functions performed by the RE revolve around user interaction. The
RE is responsible for the command-line interface (CLI), Simple Network Management
Protocol (SNMP) management, and craft interface interaction. The CLI is a user’s primary
method for performing OAM&P functions; it is accessed via a keyboard and a telnet
device, secured shell (SSH), or direct-console connection. SNMP is used to provide a
snapshot of the router’s current status. It is often combined with network management
software that can track the overall health of an entire network. The craft interface is
a series of light-emitting diodes (LEDs) and buttons that assist field technicians in
troubleshooting. The craft interface will be discussed in detail later in this chapter in
the section “The Craft Interface.” The remaining features will be discussed in detail
in Chapter 3.
For comparison purposes, Table 1-1 is provided to show the hardware components
of the different platforms.
In comparison to the M40s manufactured before mid-2001, the rest of the M-series
routers have been upgraded to improve processor speed, available memory, and the
external storage drive. Such upgrades are necessary because as time goes on, the RE
components that formed the basis of the original design are being replaced in standard
inventory by faster and larger components. For situations in which it is necessary,
a hardware upgrade is available for “original” M40s that will provide identical RE
hardware components to the rest of the M-series.
Upgraded M40 and
Other M-Series Routers
Original M40
Processor
Intel Pentium 333MHz
Intel Pentium, 233MHz
Memory
768MB
256MB
Solid State Flash
Storage
80MB
80MB
Rotating Storage
6.4GB
6.4GB
External Storage
PCMCIA drive
LS-120 drive
Table 1-1.
Comparison of M-Series RE Components
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Packet Forwarding Engine
The second half of a Juniper Networks router is the PFE, the portion of the router that
is specifically designed to forward packets. Due to the specific job functions that are
required of the PFE (such as packet encapsulation and route lookup), general-purpose
processors are not necessary or desired. By designing microchips, or application specific
integrated circuits (ASICs) specifically for these forwarding functions, the entire packet
forwarding process can be implemented in hardware. This design technique allows for
a more robust, consistent, and efficient packet forwarding implementation. The PFE is
therefore highly efficient hardware that is responsible for forwarding packets as quickly
as possible. It is also capable of delivering wire-rate packet filtering, rate limiting, and
accounting services with minimal impact on packet forwarding.
The PFE consists of four separate hardware components: Physical Interface Cards
(PICs), Flexible PIC Concentrators (FPCs), the midplane, and a control board. Each component
has its own ASIC or several that account for a single piece of the forwarding puzzle.
Only when all four components are brought together can a packet be received on one
port and forwarded out another. Let’s take a look at each component individually.
Physical Interface Card
The PIC port is the interface connecting the router to physical transmission facilities. In
other words, the PIC is where the network cable is plugged in. Located on each PIC is
an ASIC that is designed to handle media-specific functions, such as encapsulation,
checksums, and media-specific signaling. Separate ASICs have been designed for each
media type supported by Juniper Networks. For example, an ASIC has been designed
for Synchronous Optical Network (SONET) functions, for ATM functionality, and to
handle Fast Ethernet operations. Figure 1-2 shows the PIC and associated ASIC.
On some router models, PICs are equipped with an ejector lever. These PICs
are hot-swappable, which means that insertion and removal is accomplished without
significantly affecting the operation of the rest of the router.
PICs for some earlier router models do not have ejector levers and require that
the FPC be removed prior to PIC removal. While removal of this PIC will disrupt
the operation of any ports on that particular FPC, the rest of the router’s ports will
continue to operate without significant disruption.
Flexible PIC Concentrator
From the simplest viewpoint, the FPC is a chassis card that houses multiple PICs
(see Figure 1-3). Each FPC can hold between one and four PICs of any type (with the
exception of certain OC-192 and OC-48 PIC/FPC combinations that exist for certain
router models). For most models, the FPC also houses 128MB of buffer memory that is
utilized for storing data as it traverses the router, as well as a specially designed ASIC.
This ASIC will be described in detail in the “Packet Flow” section.
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Figure 1-2.
Graphical representation of the PIC and associated ASIC
A PowerPC 603e processor is located on every FPC. While this general-purpose
processor has nothing to do with the forwarding of packets, the 603e is used for
supervisory processes such as monitoring communication between the PFE ASICs
and bringing up and taking down PFE components. It also monitors items such as
the temperature sensors located on the FPC. This information is then relayed to the
JUNOS software for proper processing.
Figure 1-3.
Graphical representation of an FPC with PICs inserted
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FPCs are designed to be fully hot-swappable. To properly remove or insert an FPC
from the system, the router must first be notified of this intention. On the craft-interface
are online/offline buttons associated with each FPC. When a user wants to remove an
FPC from an operational router, he/she simply presses the button for 3 seconds until
the associated status light goes off. Once the status light goes off, it is safe to remove
the FPC from the router.
To activate a currently installed FPC, the craft interface button must again be
depressed for 3 seconds until the status light begins to flash green, indicating that the
FPC is coming online. This procedure is necessary only in the case of an FPC that has
been brought offline in the manner described in the preceding paragraphs; FPCs installed
at boot time will come online automatically, as will newly installed FPCs. Again, the
insertion or removal of any particular FPC will not significantly interrupt the operation
of the router as a whole. The craft interface and all associated LEDs will be discussed in
detail later in this chapter in the section “The Craft Interface.”
Midplane
When the FPC is inserted into the router chassis, its electrical connectors make contact
with mating connectors on the midplane. The midplane is nothing more than a passive
connection between the FPCs and the control board that makes mechanical interconnection
of the various components simple.
Control Board
The control board (which goes by different names, such as SCB, SSB, and SFM on the
different router models) contains the central decision-maker for the PFE, the Internet
Processor II ASIC (IP2). You will recall that the RE maintains a copy of the forwarding
table on the PFE, which allows the IP2 to reference this information to properly route
packets. The IP2, as well as some other important ASICs discussed in the “Packet
Flow” section, is resident on the control board.
Having this centralized forwarding decision-maker has several inherent benefits.
One key benefit is that all interfaces in the router will access the forwarding function
in the same way, leading to consistent latency and jitter statistics.
The IP2 is also where firewall filtering operations are implemented. As you will see
in Chapter 16, the IP2 contains a powerful filtering mechanism that allows the user to
control IP traffic based on many characteristics. Since it is centrally located, a firewall
filter can be implemented on any interface, flow, or traffic stream with the same level
of performance.
In addition to the IP2 processor, the control board also contains a 603e PowerPC
processor for supervisory functions. Again, this processor does not play any role in
forwarding packets across the router. It is used for monitoring the environmental
systems, maintaining communication between the RE and PFE, as well as managing
the FPCs and all PFE ASICs. It is also responsible for loading and maintaining the
forwarding table onto the IP2 and handling exception packets.
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Now that you have examined all four components that comprise the PFE, you’ll see
how a packet traverses the router. This will also allow you to take a much closer look at
the job responsibilities of the ASICs as well as how the components interact.
Packet Flow
Packet flow in the Juniper Networks M-series router is broken into components so
that each stage of the router hardware has a specific job to do and is able to function
efficiently. This section will discuss how the various router hardware components
work together to provide the entire packet-forwarding picture. Here is an example
in which we will follow a packet as it traverses a Juniper Networks router.
1. A packet arriving on a physical medium of some sort enters a PIC. That PIC
contains a specially designed ASIC that will handle issues such as link layer
errors and other physical layer issues. (See Figure 1-4.)
2. For this example, imagine that an L2 frame enters the router via a SONET link.
The frame located in the media-specific header enters the PIC and has its SONET
encapsulation removed. Then the stripped L2 frame is sent to the FPC.
Figure 1-4.
Packet flow overview
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3. When the packet leaves the PIC, it heads into the FPC as a Layer 2 PDU, such
as a PPP or frame relay frame. The I/O Manager ASIC located on the FPC
examines the L2 frame for errors and the CRC is recalculated. Any errors
detected will be dealt with appropriately. Most likely, a packet with errors will
be discarded and a notification will be sent to the JUNOS software to increment
the interface’s error counter.
4. After decapsulating the Layer 2 PDU and performing any necessary protocol
functions for that layer, the I/O Manager ASIC chops the resulting packet (L3)
into 64-byte chunks (called jcells) for efficient storage in memory. Memory for
data storage is located on the router’s installed FPCs, and all FPCs installed in
the router contribute the greater part of their memory to a single pool that is
used for this storage. This architecture insures that the router will never suffer
from insufficient buffer memory to handle incoming packets.
5. The allotment of memory on each FPC has been chosen to be more than sufficient
for any combination of four PICs inserted into the FPC. When more than four
PICs are added to the router, a new FPC must be inserted, and hence additional
memory is also added to handle the additional data load. The shared buffer
memory located on each FPC is therefore mapped by the PFE to look like a
single pool of memory.
6. Now that the I/O manager has divided up the incoming packet, the data is
ready to be stored in the shared buffer memory until it is time to transmit. The
64-byte chunks coming from the I/O manager are passed to the buffer manager
ASIC, which is located on the control board. The buffer manager is responsible
for extracting the key information that is used for a proper forwarding decision.
The buffer manager sends this “key cell” on to the IP2 for the route lookup. In
the meantime, the buffer manager writes all the jcells (64-byte chunks) to the
buffer memory slots in a round robin fashion, distributing the packet between
the installed FPC’s memory. (See Figure 1-5.)
7. Once the IP2 ASIC receives the key data, it references the forwarding table that
it obtained from the RE. Based on this information, it determines the next-hop
and outgoing interface information and stores this data in a result cell. The
result cell is sent to the buffer manager ASIC. This ASIC then routes the
notification to the appropriate FPC or, in the case of multicast, appropriate
FPCs. (See Figure 1-6.)
8. A packet notification, a subset of the result cell, is then queued by the I/O
manager ASIC until it is ready to be transmitted. When the packet notification
reaches the front of the queue, the I/O manager notifies the buffer manager that
the remainder of the packet is required. The buffer manager then reads the cells
of the packet from the packet memory and assembles them. After the assembly,
the L2/L3 header (re)write operation is done and the frame is streamed down
to the outgoing PIC. (See Figure 1-7.)
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Figure 1-5.
Packet flow diagram step 6
Figure 1-6.
Packet flow diagram step 7
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Hardware and Architecture
Packet flow diagram step 8
9. In this fashion, the packet is reassembled on the fly as it is being transmitted
onto the line. Given the shared memory architecture, the actual packet is written
to and read from memory only once. This saves precious time by minimizing
the number of memory reads and writes. Also, the ease with which the routers
can now multicast traffic out of multiple ports at the same time is rather significant.
When multiple ports are required to send a copy of the packet, multiple
notifications are sent to the appropriate I/O manager ASIC(s), which can in
turn send notification cells to each of the outgoing ports. When the packet is
ready to be transmitted, the 64-byte chunks are simply read from the packet
memory multiple times, once for each outgoing port.
Connecting the RE and PFE
The RE communicates with the PFE via a 100 Mbps Ethernet channel that is internally
referenced as fxp1. Any data that requires a response or a logical decision outside the
standard forwarding capability for the PFE is sent to the RE. These packets are referred
to as exception packets and are flagged as such in the IP2. Once a packet is identified as
an exception packet, it is sent to the PowerPC supervisory processor located on the
control board for forwarding to the RE.
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It is important that the fxp1 interface never be manually configured on a production
router. Any misconfiguration could cause the RE and the PFE to cease communicating.
Two types of packets generally require attention by the RE: network control packets
and local delivery packets. Some of the packets that would qualify as exception packets
include these:
■ Routing protocols
■ Local delivery packets (such as a locally destined ssh session)
■ Packets with IP options set, such as router alert
The fxp1 connection is rate limited and uses flow control (queuing and per-protocol
rate limits) to give priority to network control packets to ensure that the routing protocols
receive priority over less important traffic. This is a form of built-in protection against
denial of service (DoS) attacks, and at the same time it ensures that the router will attend
to network control matters first. In other words, the router will attend to a BGP update
message prior to answering a PING request if the two are in contention.
The Craft Interface
The craft interface lets you determine the status of the router by looking at the front
of the box. The craft interface consists of status LEDs, online/offline buttons for FPCs,
connectors for management communication with the router, and (on some models)
an LCD display for system status messages. The following illustration shows the craft
interface for the M160 router.
Maintaining Router Airflow
One of the most difficult challenges in high-performance electronic system design
is keeping the device cool during operation. The components must maintain optimal
operating temperature, even under the harshest of operating conditions.
The first step in controlling the operating environment is measuring its current
state, which is accomplished via the numerous temperature sensors located on the
router. These sensors provide data to the supervisory processors located on the
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FPC, control board, and the Routing Engine. The current environmental status is
reported to the JUNOS software so that the router can take any necessary actions.
Under normal operating conditions, recommended ambient room temperature
of 32°F (0°C ) through 104°F (40°C ), the routers fans will operate at half speed. Once
temperatures hit 129°F (54°C ) all fans in the router are increased to full speed and
a yellow alarm is generated. If the temperature should continue to increase to 167°F
(75°C ), the router will generate a red alarm and shut down the system.
To keep the system cool, the router chassis are equipped with high-powered fans
and impellers. (The power supplies have their own dedicated fans.) Controlling the
airflow for the rest of the chassis requires a push-and-pull system of fans working
together. The half-rack routers (the M40 and M160) employ a bottom-to-top cooling
method in which the air is sucked into the bottom front of the router and pushed
out of the top back side of the router.
The air enters the router via an air filter that must be cleaned or replaced every
180 days. An associated yellow alarm condition will trigger by default every 180
days as a reminder to perform this action.
The smaller routers employ a side-to-side cooling system, employing either one
or three sets of fans along the left side of the router.
Each of the field-replaceable units contains three high-powered fans that can direct
air immediately across the entire PFE.
Using the Craft Interface
On the craft interface, two status LEDs are used for visual notification of red and yellow
alarms. When a condition exists that triggers an alarm, the appropriate alarm notification
is sent and the associated LED will glow. Each LED is also associated with a set of dry
contact relays. These relays can trigger an external notification system, such as a siren
or gong. To enable a sound event each time a red alarm occurs, hook the trigger leads
for the gong to the dry contacts associated with the red alarm LED. POP technicians
may hate the noise, but they will never miss a router alarm.
Also located on the craft interface are a series of buttons used to start or stop FPCs.
Each FPC contains shared buffer memory. When a user wants to remove an FPC for
maintenance, the system must be notified to gracefully remove the FPC memory from
the system pool. This is accomplished by depressing the FPC’s associated button on
the craft interface for about 3 seconds.
The online/offline button is surrounded by two status LEDs of its own. A red
LED to the left lights to indicate that the associated FPC is in failed status. This is a
hardware error condition that indicates the router requires attention. On the right side
of the FPC button is a green LED light that indicates the associated FPC is online and
operating properly.
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A set of three connectors is also located on the craft interface. These connectors allow
out-of-band management for the router and provide a direct line into the Routing Engine.
The connectors consist of a 10/100 Mbps RJ-45 Ethernet port, and two RS-232 connectors.
One of the RS-232 connectors is designated as the console port and the second is the
auxiliary console port. The console port is enabled by default with standard 9600-8-N-1
terminal settings, whereas the auxiliary console must be enabled via configuration to
attach a modem or terminal device.
On the M160 and M40, you will find an LCD display that scrolls system status
messages. The display shows items such as the router name and uptime. The LCD will
also report the power supply status, fan speed, current temperature, and the current
load on the router in packets per second.
Product Features
Each Juniper Networks router is built upon the same basic foundation. While the
premise of using a dedicated PFE in conjunction with a physically separate RE for
handling routing protocols remains consistent, each product is slightly different
from its predecessors. This section examines the peculiarities of each box.
M40/M20
During initial product development, Juniper Networks’ largest potential customers
wanted a router that would provide line-rate performance on a stable platform, and
they wanted it immediately. With this in mind, optional features such as redundancy
and firewall capabilities were pushed aside to deliver the product to market in minimal
time. The result was the half-rack sized M40.
The large carriers who wanted to deploy the M40 insisted that if they desired
redundancy, they would deploy the routers in pairs. With this in mind, it is easy to
understand why the M40 has no redundancy when it comes to hardware, with the
exception of power supplies. Figure 1-8 shows the schematic of the M40 router.
The power supplies in an M40 can be either AC or DC (but not both simultaneously)
and are fully redundant. While a single power supply can provide sufficient power for
the entire router, if two are operating correctly, they will share the load. The DC power
supplies have a maximum output of 1500W and an input current rating of 35A @ –48V.
The input voltage can be in the range of –40 through –75VDC. The AC power supplies
also run a maximum of 1500W and have an input current rating of 8A @ 208V. The
acceptable input voltage range is from 180 to 264VAC.
The M40 has a single RE, a single board for PFE control, and can contain up to eight
FPCs. The control board for the PFE is referred to as the System Control Board (SCB) and
is located in the middle of the PFE. One significant difference between the M40 and the
remaining product line is the fact that the distributed buffer manager ASIC’s are located
on the backplane of the M40 rather than on the control board as in the other router models.
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Figure 1-8.
Hardware and Architecture
Schematic of the M40 router
The M20 platform was designed for greater port density and holds up to four FPCs
in a chassis that is only 14-inches high. It also addresses concerns over redundancy. The
router’s schematic is shown in Figure 1-9.
The power supplies in an M20 can also be either AC or DC and are fully redundant.
The DC power supplies have a maximum output of 750W and an input current rating
of 24A @ –48V. The input voltage can be in the range of –40 through –72VDC. The AC
power supplies also run a maximum of 750W and have an input current rating of 13A
@ 90V. The acceptable input voltage range is from 90 to 264VAC.
Figure 1-9.
Schematic of M20 router
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In the M20 platform the distributed buffer manager ASICs are moved from the
backplane to the control board. This causes the control board to be renamed to the
System Switching Board (SSB). The M20 also implements full redundancy with dual
REs and dual SSBs. Both the REs and the SSBs are redundant in that during normal
operation, one is operational while the second is in standby mode. In the event of a
failure, the second unit will assume control of the router.
M160
Like the M20, the M160 implements dual REs that provide failure redundancy. The
PFE, however, is handled in a completely different manner. To quadruple the throughput
of the M40, the M160 moved to a system that allows the forwarded traffic to be load
balanced over several control boards.
The M160 implements four control boards that work in concert to handle the traffic
transiting the router. The change in operation for the control board causes yet another
name change to Switching and Forwarding Module (SFM). In essence, each of the four
SFM’s does the job of a single SCB in an M40. Since the M160 FPCs have four times
the throughput of the M40 platform, each SFM is effectively handling one quarter of the
traffic on each FPC. Should one of the SFMs become inoperable, one quarter of the
router’s throughput would be lost, but it can still continue to forward packets at the
reduced rate until the failed SFM is replaced. Figure 1-10 shows a block diagram of
the M160 FPC.
When the serial stream of bits leaves the FPC, it must be directed to one of the four
SFMs. To accomplish this, two Packet Director (PD) ASICs are utilized. The PD ASICs
determine to which SFM to send the packet and direct the serial stream of bits to one
of four I/O manager ASICs that have been installed on each FPC. Each I/O manager is
assigned to a particular SFM and therefore directs packet chunks toward a designated
control board.
Figure 1-10.
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Block diagram of M160 FPC
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The M160 also improves on modularity in hardware, in part to make the replacement
of failed parts easier, but mostly due to centralizing operation of common components
found on the control board of other Juniper Networks routers. Because the M160 has four
SFMs that work together, it is necessary to centralize operations such as internal clocking
and system management. Figure 1-11 shows the schematic of the M160.
The Miscellaneous Control System (MCS) works in conjunction with the RE to monitor
communications among the internal router components and to provide clocking for
SONET interfaces. The MCS will monitor system components and sensors to gather
information to send to the RE for processing. It will also handle the power-up cycle for
components when the system is first started as well as the power-down sequence when
the user requests that the unit be taken offline. The master MCS is hot-pluggable, and
the backup MCS is hot swappable. In other words, the router does not need to be powered
down when inserting/removing the master MCS, but the routing will be interrupted.
The backup MCS can be inserted/removed without affecting the router operations.
The PFE Clock Generator (PCG) generates a clocking signal to synchronize the internal
components. The PCG supplies a 125-MHz clock to modules of the PFE including the
ASICs. The PCGs are also hot-pluggable.
Another key difference in the M160 architecture is the separation of the out-of-band
management ports. The Ethernet and RS-232 connectors are located on a separate card
on the left side of the FPCs.
This card is called the Connector Interface Panel (CIP), shown in Figure 1-12, and is
used for management connection to the M160s two REs. The upper set of connectors is
Figure 1-11.
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Schematic of M160 router
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Figure 1-12.
Diagram of the Connector Interface Panel
labeled Host0 and connects directly to RE0. The second set of connectors labeled Host1
connect directly to RE1.
The final key differentiator for the M160 is the DC-only power supplies. Mostly due
to the fact that AC power rectification produces a large amount of heat, the M160 does
not offer AC power modules.
The DC power supplies are fully redundant, but in the case of the M160, two options
exist for DC power. The original DC power supply provides a maximum output of 2600W
with an input current rating of 65A @ –48V. The nominal DC input voltage should be
in the range of –48 to –60VDC. The enhanced DC power supply provides slightly more
power at 3200W max with a slightly higher input current rating of 80A @ –48V. The
“enhanced” power supply is needed only in rare occasions when the M160 is loaded
with numerous high draw cards.
M5/M10
Just as the M160 represents an increase in modularity and throughput, the M5 and M10
routers are reduced in size to increase port density. The loss of space causes the smaller
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routers to move, combine, and even remove certain components that exist in the other
platforms.
When looking at the architecture of M5 and M10, the first thing that stands out is
the lack of a distinguishable FPC. The FPC has been combined with the control board
to form a single Forwarding Engine Board (FEB), which allows for consolidation of the
main PFE functions and saves valuable space. Figure 1-13 shows a diagram of the FEB.
The PICs used for an M5/10 router have their own ejector handle and can therefore
be installed or removed without powering down the router. This is necessary since the
PIC inserts directly into the router chassis. PIC offline/online buttons are located on
the front of the router. Figure 1-14 shows a schematic of the M10.
Since the M5/10 have a single RE, only a single set of the Ethernet and RS-232
connectors are required for out-of-band management. The dry relay contacts are no
longer present, and only the red and yellow alarm LEDs remain. Figure 1-15 shows a
view of the craft interface.
The only aspect that externally differentiates the M5 from the M10 is the number
of PICs that it can hold. The M5 router is capable of holding up to four PICs, while the
M10 can consist of up to eight. Considering that both routers are only 5.25-inches high,
this provides for outstanding port density.
Figure 1-13.
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Block diagram of the Forwarding Engine Board
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Figure 1-14.
Schematic of the M10 router
Finally, the power supplies in the edge access routers are again available in both
AC and DC and are fully redundant. The DC power supplies can provide up to 434W
maximum output with an input current rating of 13.5A @ –48VDC. The acceptable input
voltage range is from –42.5 through –72VDC. The AC power supplies also provide
a maximum of 434W output with an input current rating of either 8A @ 100VAC, or
4A @ 240VAC.
Figure 1-15.
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View of the M5 or M10 craft interface
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