LT1122
Fast Settling, JFET Input
Operational Amplifier
U
FEATURES
■
■
■
■
■
■
■
■
■
DESCRIPTIO
100% Tested Settling Time
to 1mV at Sum Node, 10V Step
Tested with Fixed Feedback Capacitor
Slew Rate
Gain Bandwidth Product
Power Bandwidth (20Vp-p)
Unity Gain Stable; Phase Margin
Input Offset Voltage
Input Bias Current
25°C
70°C
Input Offset Current
25°C
70°C
Low Distortion
340ns Typ
540ns Max
The LT1122 JFET input operational amplifier combines
high speed and precision performance.
60V/µs Min
14MHz
1.2 MHz
60°
600µV Max
75pA Max
600pA Max
40pA Max
150pA Max
A unique poly-gate JFET process minimizes gate series
resistance and gate-to-drain capacitance, facilitating wide
bandwidth performance, without degrading JFET transistor matching.
The LT1122 offset voltage of 120µV, and voltage gain of
500,000 also support the 12-bit accurate applications.
UO
APPLICATI
■
■
■
■
■
■
■
■
It slews at 80V/µs and settles in 340ns. The LT1122 is
internally compensated to be unity gain stable, yet it has a
bandwidth of 14MHz at a supply current of only 7mA. Its
speed makes the LT1122 an ideal choice for fast settling
12-bit data conversion and acquisition systems.
S
The input bias current of 10pA and offset current of 4pA
combined with its speed allow the LT1122 to be used in
such applications as high speed sample and hold amplifiers, peak detectors, and integrators.
Fast 12-Bit D/A Output Amplifiers
High Speed Buffers
Fast Sample and Hold Amplifiers
High Speed Integrators
Voltage to Frequency Converters
Active Filters
Log Amplifiers
Peak Detectors
UO
TYPICAL APPLICATI
Large-Signal Response
12-Bit Voltage Output D/A Converter
+
Cf
–
0mA TO 2mA
OR 4mA
LT1122
3
12-BIT CURRENT OUTPUT D/A CONVERTER
C f = 5pF TO 17pF
(DEPENDING ON D/A CONVERTER USED)
6
VOUT
0V TO 10V
+
LT1122•TA01
5V/DIV
2
200ns/DIV
AV = –1
1122 TA07
1
LT1122
W W
W
AXI U
U
ABSOLUTE
RATI GS
Supply Voltage .................................................... ± 20V
Differential Input Voltage ...................................... ± 40V
Input Voltage ........................................................ ± 20V
Output Short Circuit Duration .......................... Indefinite
Lead Temperature (Soldering, 10 sec.)................. 300°C
Operating Temperature Range
LT1122AM/BM/CM/DM .................... – 55°C to 125°C
LT1122AC/BC/CC/DC/CS/DS .............. – 40°C to 85°C
Storage Temperature Range
All Devices ....................................... – 65°C to 150°C
W
U
U
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VOS
TRIM
–IN
1
8
2
7
SPEED BOOST/
OVERCOMP
V+
LT1122
+IN
3
6
OUT
V–
4
5
VOS TRIM
N8 PACKAGE
J8 PACKAGE
8-LEAD PLASTIC DIP 8-LEAD HERMETIC DIP
TJMAX = 150°C, θJA = 130°C/W (N8)
TJMAX = 175°C, θJA = 100°C/W (J8)
ORDER PART
NUMBER
LT1122AMJ8 LT1122CCJ8
LT1122BMJ8 LT1122DCJ8
LT1122CMJ8 LT1122ACN8
LT1122DMJ8 LT1122BCN8
LT1122ACJ8 LT1122CCN8
LT1122BCJ8 LT1122DCN8
ORDER PART
NUMBER
TOP VIEW
7
SPEED BOOST/
OVERCOMP
V+
+IN
3
6
OUT
V–
4
5
VOS TRIM
VOS
TRIM
–IN
1
8
2
LT1122
LT1122CS8
LT1122DS8
PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SOIC
1122C
1122D
TJMAX = 150°C, θJA = 190°C/W
Consult factory for Industrial grade parts.
ELECTRICAL CHARACTERISTICS
VS = ± 15V, TA = 25°C, VCM = 0V unless otherwise noted. (Note 1)
LT1122CM/DM
LT1122CC/DC
LT1122CS/DS
MIN TYP MAX
SYMBOL
PARAMETER
VOS
Input Offset Voltage
120
600
130
900
IOS
Input Offset Current
4
40
5
50
pA
IB
Input Bias Current
10
75
12
100
pA
Input Resistance
Differential
Common Mode
CONDITIONS
LT1122AM/BM
LT1122AC/BC
MIN TYP MAX
1012
1012
1011
VCM = – 10V to + 8V
VCM = + 8V to + 11V
Input Capacitance
SR
GBW
AVOL
CMRR
PSRR
AV = – 1
Settling Time (Note 2)
+ 10V to 0V, – 10V to 0V
100% Tested: A and C Grades
to 1mV at Sum Node
B and D Grades to 1mV at Sum Node
All Grades to 0.5mV at Sum Node
340
350
450
VOUT = 20Vp-p
14
1.2
Gain Bandwidth Product
Power Bandwidth
Large Signal Voltage Gain
Common Mode Rejection Ratio
VCM = ± 10V
Input Voltage Range
(Note 3)
Power Supply Rejection Ratio
VS = ± 10V to ± 18V
Input Noise Voltage
Input Noise Voltage Density
0.1Hz to 10Hz
fO = 100Hz
fO = 10kHz
fO = 100Hz, fO = 10kHz
Input Noise Current Density
2
VOUT = ± 10V, RL = 2kΩ
VOUT = ± 10V, RL = 600Ω
60
180
130
500
250
83
99
± 10.5 ± 11
86
4
80
103
3.0
25
14
2
50
540
150
110
80
± 10.5
82
pF
75
350
360
470
µV
Ω
Ω
Ω
1012
1012
1011
4
Slew Rate
UNITS
V/µs
590
ns
ns
ns
13
1.1
MHz
MHz
450
220
V/mV
V/mV
98
± 11
dB
V
101
dB
3.3
27
15
2
µVP-P
nV/√Hz
nV/√Hz
fA/√Hz
LT1122
ELECTRICAL CHARACTERISTICS
VS = ± 15V, TA = 25°C, VCM = 0V unless otherwise noted.
LT1122AM/BM
LT1122AC/BC
MIN TYP MAX
SYMBOL
PARAMETER
CONDITIONS
VOUT
Output Voltage Swing
RL = 2kΩ
RL = 600Ω
± 12
± 12.5
± 11.5 ± 12
IS
Supply Current
Minimum Supply voltage
(Note 4)
±5
Offset Adjustment Range
RPOT ≥ 10k, Wiper to V+
±4
7.5
LT1122CM/DM
LT1122CC/DC
LT1122CS/DS
MIN TYP MAX
± 12
± 11.5
10
UNITS
± 12.5
± 12
7.8
V
V
11
mA
±5
± 10
±4
V
± 10
mV
VS = ± 15V, VCM = 0V, 0°C ≤ TA ≤ 70°C, unless otherwise noted. (Note 1)
SYMBOL
PARAMETER
VOS
Input Offset Voltage
CONDITIONS
Input Offset Current
IB
Input Bias Current
AVOL
Large Signal Voltage Gain
LT1122CC/DC
LT1122CS/DS
MIN TYP MAX
350
1400
400
2000
5
18
6
25
12
150
15
200
80
600
90
800
•
•
Average Temperature Coefficient
of Input Offset Voltage
IOS
LT1122AC/BC
MIN TYP MAX
VOUT = ± 10V, RL ≥ 2kΩ
CMRR
Common Mode Rejection Ratio
VCM = ± 10V
PSRR
Power Supply Rejection Ratio
VS = ± 10V to ± 17V
Input Voltage Range
VOUT
Output Voltage Swing
RL = 2kΩ
SR
Slew Rate
AV = – 1
•
•
•
•
•
•
•
•
100
µV
µV/°C
pA
pA
120
380
82
98
78
96
dB
84
101
80
99
dB
± 10
± 10.8
± 10
± 10.8
V
± 11.5
± 12.4
40
65
± 11.5 ± 12.4
50
70
340
UNITS
V/mV
V
V/µs
VS = ± 15V, VCM = 0V, – 55°C ≤ TA ≤ 125°C, unless otherwise noted. (Note 1)
SYMBOL
PARAMETER
VOS
Input Offset Voltage
CONDITIONS
Average Temperature Coefficient
of Input Offset Voltage
IOS
Input Offset Current
IB
Input Bias Current
AVOL
Large Signal Voltage Gain
VOUT = ± 10V, RL ≥ 2kΩ
CMRR
Common Mode Rejection Ratio
VCM = ± 10V
PSRR
Power Supply Rejection Ratio
VS = ± 10V to ± 17V
Input Voltage Range
VOUT
Output Voltage Swing
RL = 2kΩ
SR
Slew Rate
AV = – 1
The • denotes the specifications which apply over the full operating
temperature range.
Note 1: The LT1122 is measured in an automated tester in less than one
second after application of power. Depending on the package used, power
dissipation, heat sinking, and air flow conditions, the fully warmed up chip
temperature can be 10°C to 50°C higher than the ambient temperature.
Note 2: Settling time is 100% tested for A and C grades using the settling
time test circuit shown. This test is not included in quality assurance
sample testing.
•
•
•
•
•
•
•
•
•
•
LT1122AM/BM
MIN TYP MAX
LT1122CM/DM
MIN TYP MAX
650
2400
800
3400
6
18
7
25
0.5
6
0.6
9
nA
6
25
7
35
nA
UNITS
µV
µV/°C
70
230
60
200
80
97
76
94
dB
83
100
78
98
dB
± 10
± 10.5
± 10
± 10.5
V
± 11.3 ± 12.1
45
60
V/mV
± 11.3 ± 12.1
35
55
V
V/µs
Note 3: Input voltage range functionality is assured by testing offset
voltage at the input voltage range limits to a maximum of 4mV (A, B
grades), to 5.7mV (C, D grades).
Note 4: Minimum supply voltage is tested by measuring offset voltage to
7mV maximum at ± 5V supplies.
Note 5: The LT1122 is not tested and not quality-assurance-sampled at
– 40°C and at 85°C. These specifications are guaranteed by design,
correlation and/or inference from – 55°C, 0°C, 25°C, 70°C and/or 125°C
tests.
3
LT1122
ELECTRICAL CHARACTERISTICS
VS = ± 15V, VCM = 0V, – 40°C ≤ TA ≤ 85°C, unless otherwise noted. (Note 5)
SYMBOL
PARAMETER
VOS
Input Offset Voltage
CONDITIONS
•
•
Average Temperature Coefficient
of Input Offset Voltage
IOS
Input Offset Current
IB
Input Bias Current
AVOL
Large Signal Voltage Gain
•
•
•
•
•
•
•
•
VOUT = ± 10V, RL ≥ 2kΩ
CMRR
Common Mode Rejection Ratio
VCM = ± 10V
PSRR
Power Supply Rejection Ratio
VS = ± 10V to ± 17V
Input Voltage Range
VOUT
Output Voltage Swing
RL = 2kΩ
SR
Slew Rate
AV = – 1
LT1122AC/BC
MIN TYP MAX
LT1122CC/DC
LT1122CS/DS
MIN TYP MAX
450
1900
500
2700
6
20
7
28
30
600
40
900
230
2000
260
2700
80
98
76
96
dB
83
100
78
98
dB
± 10
± 10.6
± 10
± 10.6
V
± 11.3
± 12.2
V
35
60
45
65
74LS00
GROUND ALL
OTHER INPUTS
TTL
IN
6
1
2
7
–
LT1122
3
5
+
2
15
3
14
6
4
–15V
5
4
1
51
8
HA5002
+15V
2k
1%
1
16
V/µs
2k
1%
2
4
V/mV
DEVICE UNDER TEST
5pF
7
4
–15V
5.1k
1%
5.1k*
1%
V IN
(MEASURE INPUT
PULSE HERE)
13
LTC201A
3
2
5
12
6
11
7
10
8
9
+15V
–10V
(REGULATED)
7
1k
+15V
+
0.1µF
1µF TANT
TYPICAL SUPPLY
BYPASSING FOR
EACH AMP/BUFFER
SETTLING
TIME OUTPUT
(20 TIMES SUM
NODE OUTPUT)
1N5712
7
+15V
NO CONNECTION ON PINS
10, 11, 12, 14, AND 15
6
+
3
51
1
8
2
LT1223
4
1.5k –15V
HA5002
–
2
4
51
SUMMING
NODE
OUTPUT
5
–15V
79
1N5712
–15V
0.1µF
4
+
1µF TANT
pA
80
± 11.3 ± 12.2
300
pA
340
+15V
51
µV
µV/°C
95
Settling Time Test Fixture
+10V
(REGULATED)
UNITS
*THIS RESISTOR CAN BE ADJUSTED TO
NULL OUT ALL OFFSETS AT THE SETTLING
TIME OUTPUT. THE AUTOMATED TESTER
USES A SEPARATE AUTOZERO CIRCUIT.
LT1122•TA02
LT1122
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Settling Time
(Input From 0V to +10V)
1mV/DIV AT SUM NODE
1mV/DIV AT SUM NODE
Settling Time
(Input From +10V to 0V)
1mV/DIV AT SUM NODE
Settling Time
(Input From –10V to 0V)
100ns/DIV
100ns/DIV
1122 G01
100ns/DIV
1122 G02
Settling Time
(Input From 0V to –10V)
1122 G03
Undistorted Output Swing vs
Frequency
Large Signal Response
PEAK TO PEAK OUTPUT SWING (V)
5V/DIV
1mV/DIV AT SUM NODE
30
200ns/DIV
AV = +1
100ns/DIV
1122 G04
1122 G05
VS = ±15V
TA = 25°C
25
20
15
10
5
0
100k
1M
10M
100M
FREQUENCY (Hz)
LT1122•TPC01
Voltage Gain vs Frequency
Common Mode Rejection vs
Frequency
Gain, Phase vs Frequency
120
100
20
60
GAIN (dB)
GAIN (dB)
80
40
20
140
10
160
180
0
VS = ±15V
TA = 25°C
C L = 15pF
0
–20
200
–10
1
10
100
1k
10k 100k 1M 10M 100M
FREQUENCY (Hz)
1M
10M
100M
VS = ±15V
TA = 25°C
100
80
60
40
20
0
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
LT1122•TPC02
PHASE SHIFT (DEGREES)
120
COMMON-MODE REJECTION RATIO (dB)
VS = ±15V
TA = 25°C
100
–40
120
80
LT1122•TPC03
LT1122•TPC04
5
LT1122
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Distribution of Input Offset
Voltage
Input Bias and Offset Currents
Over Temperature
400
200
0
–900
30K
INPUT BIAS AND OFFSET CURRENT (pA)
600
VS = ±15V
TA = 25°C
(NOT WARMED UP)
INPUT BIAS AND OFFSET CURRENTS (pA)
3370 UNITS TESTED
IN ALL PACKAGES
NUMBER OF UNITS
120
100K
800
VS = ±15V
VCM = 0V
10K
3K
BIAS
CURRENT
1K
300
100
30
OFFSET
CURRENT
10
3
1
–100 100
–500
25
0
900
500
INPUT OFFSET VOLTAGE (µV)
50
75
VS = ±15V
TA = 25°C
(NOT-WARMED UP)
100
80
BIAS
CURRENT
60
40
OFFSET
CURRENT
20
0
–15
125
100
–10
–5
10
5
0
LT1122•TPC06
Warm-up Drift
15
COMMON-MODE INPUT VOLTAGE (V)
CHIP TEMPERATURE (°C)
LT1122•TPC05
LT1122•TPC07
Noise Spectrum
0.1Hz to 10Hz Noise
1000
VS = ±15V
TA = 25°C
VOLTAGE NOISE DENSITY (nV/√Hz)
SO PACKAGE
200
N PACKAGE
150
J PACKAGE
100
50
IN STILL AIR (SO PACKAGE
SOLDERED ONTO BOARD)
1
VS = ±15V
TA = 25°C
NOISE VOLTAGE (1µ V/DIV)
250
CHANGE IN OFFSET VOLTAGE (µV)
Bias and Offset Currents Over
The Common-Mode Range
100
10
1
0
2
3
1
3
10
TIME AFTER POWER ON (MINUTES)
30
100 300
1k
3k
0
10k
2
4
6
8
10
TIME (SECONDS)
FREQUENCY (Hz)
LT1122•TPC10
LT1122•TPC08
LT1122•TPC09
0.1
T A = 25°C
VS = ±15V
Z L = 5k//15pF
VO = 7V RMS
0.01
A V = –50
A V = –10
0.001
A V = –1
0.0001
20
100
1k
10k 20k
0.1
0.01
A V = +50
AV = +10
0.001
0.0001
20
A V = +1
100
T A = 25°C
VS = ±15V
Z L = 5k//15pF
VO = 7V RMS
1k
10k 20k
LT1122•TPC11
0.1
LF156
0.01
VS = ±15V
T A = 25°C
AV = –10
VO = 7V RMS
Z L = 5k//15pF
0.001
LT1122
0.0001
3k
10k
20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6
Intermodulation Distortion
(CCIF Method) vs Frequency
LT1122 and LF156*
INTERMODULATION DISTORTION (IMD) (%)
Total Harmonic Distortion
+ Noise vs Frequency
Non-Inverting Gain
TOTAL HARMONIC DISTORTION + NOISE (%)
TOTAL HARMONIC DISTORTION + NOISE (%)
Total Harmonic Distortion
+ Noise vs Frequency
Inverting Gain
LT1122•TPC12
*SEE LT1115 DATA SHEET FOR DEFINITION
OF CCIF TESTING
LT1122•TPC13
LT1122
U
W
U
UO
APPLICATI
S I FOR ATIO
Settling Time Measurements
Settling time test circuits shown on some competitive
devices’ data sheets require:
1. A “flat top” pulse generator. Unfortunately, flat top
pulse generators are not commercially available.
2. A variable feedback capacitor around the device under
test. This capacitor varies over a four to one range.
Presumably, as each op amp is measured for settling
time, the capacitor is fine tuned to optimize settling
time for that particular device.
The power supply connections to the LT1122 must maintain a low impedance to ground over a bandwidth of
20MHz. This is especially important when driving a significant resistive or capacitive load, since all current delivered
to the load comes from the power supplies. Multiple high
quality bypass capacitors are recommended for each
power supply line in any critical application. A 0.1µF
ceramic and a 1µF electrolytic capacitor, as shown, placed
as close as possible to the amplifier (with short lead
lengths to power supply common) will assure adequate
high frequency bypassing, in most applications.
V+
3. A small inductor load to optimize settling.
+
The LT1122’s settling time is 100% tested in the test
circuit shown. No “flat top” pulse generator is required.
The test circuit can be readily constructed, using commercially available ICs. Of course, standard high frequency
board construction techniques should be followed. All
LT1122s are measured with a constant feedback capacitor. No fine tuning is required.
Speed Boost/Overcompensation Terminal
Pin 8 of the LT1122 can be used to change the input stage
operating current of the device. Shorting pin 8 to the
positive supply (Pin 7) increases slew rate and bandwidth
by about 25%, but at the expense of a reduction in phase
margin by approximately 18 degrees. Unity gain capacitive load handling decreases from typically 500pF to
100pF.
Conversely, connecting a 15k resistor from pin 8 to
ground pulls 1mA out of pin 8 (with V+ = 15V). This
reduces slew rate and bandwidth by 25%. Phase margin
and capacitive load handling improve; the latter typically
increasing to 800pF.
2
7
0.1µF
1µF
0.1µF
–
6
LT1122
3
1µF
+
4
V–
+
LT1122•TA03
When the feedback around the op amp is resistive (RF), a
pole will be created with RF, the source resistance and
capacitance (RS, CS), and the amplifier input capacitance
(CIN ≈ 4pF). In low closed loop gain configurations and
with RS and RF in the kilohm range, this pole can create
excess phase shift and even oscillation. A small capacitor
(CF) in parallel with RF eliminates this problem. With
RS (CS + CIN) = RFCF, the effect of the feedback pole is
completely removed.
CF
RF
–
High Speed Operation
CIN
As with most high speed amplifiers, care should be taken
with supply decoupling, lead dress and component
placement.
RS
CS
OUTPUT
+
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
LT1122•TA04
7
LT1122
U
TYPICAL APPLICATIONS
Quartz Stabilized Oscillator With 9ppm Distortion
OUTPUT
–15V
4.7k
LT1004
2.5V
47k
4kHz
J CUT
5k
OUTPUT
AMPLITUDE 10 µ F
TRIM
+
4.7k
+15V
+
4.7k
LT1122
DISTORTION
TRIM
430pF
–
LT1010
–
LT1006
MOUNT IN CLOSE
PROXIMITY
50k
+
560k
470 Ω
+15V
2k
GROUND CRYSTAL CASE
–
1M
+15V
LT1122
560k
= VACTEC VTL5C10 OR
CLAIREX CLM410
+
–15V
Q1
2N3904
1/4 LTC201
100k
= 1N4148
LT1122•TA05
Wide-Band, Filtered, Full Wave Rectifier
1µ F
200k
1%
200k
1%
20k
1%
100k
1%
50k
1k
–
20k
1%
LT1122
–
VIN
EOUT DC
+
LT1122
+
OUTPUT DC = RMS VALUE OF INPUT
BANDWIDTH WITH 10Vp-p INPUT = 2MHz
U
PACKAGE DESCRIPTION
Please see the 1994 Linear Databook Volume III for package descriptions.
8
LT1122•TA06