FAST POWER CONVERTERS AND RAPID DIGITAL DESIGN
BY
GRANT PITEL
B.S., Cornell University, 2003
M.S., University of Illinois at Urbana-Champaign, 2005
DISSERTATION
Submitted in partial fulfillment of the requirements
for the degree of Doctor of Philosophy in Electrical and Computer Engineering
in the Graduate College of the
University of Illinois at Urbana-Champaign, 2008
Urbana, Illinois
Doctoral Committee:
Professor Philip T. Krein, Chair
Associate Professor Patrick Lyle Chapman
Professor P. R. Kumar
Professor Peter W. Sauer
ABSTRACT
Switching mode power supplies (SMPS) have a diverse history of analysis
techniques. Discrete controls introduce new techniques and software design steps that add
value through more features, advanced control algorithms, and reduced time-to-market.
These advantages can improve voltage regulation at the point of load in micro power
systems and can better organize massive projects in macro power systems via model
based design.
Voltage regulator modules (VRM) are micro power systems that supply clean lowvoltage high-current power to microprocessor loads. Minimum-time control algorithms
and active topological changes are proposed to reduce VRM parameter sensitivity—an
alternative to more sophisticated linear control algorithms and enlarged passive
components. Minimum-time control has an intuitive solution based on geometric
surfaces. Curved surfaces built from model parameters can achieve ―b
est‖ theoretical
control performance. When applications have unknown or poor parameter knowledge
they can implement system identification algorithms. Performance surpasses curved
surface control limits when converter topology actively changes. Augmented converters
with programmable conduction change their topology in a way that can completely
eliminate voltage transients.
Model-based design has revolutionized workflows in macro-scale engineering
projects. Digital control facilitates bottom-up workflows where hardware, software, and
design teams can work independently. These new workflows are tested for sending power
into the utility grid on the Grainger Center modular inverter.
ii
To my mother
iii
ACKNOWLEDGMENTS
I want to thank the Grainger Center whose generous support has allowed me to
pursue research with long-term impact. Their contributions to the University of
Illinois’extensive library collection and the resources made available through the
Grainger Center for Electric Machinery and Electromechanics have enriched my graduate
education. The National Science Foundation (NSF ECS 06-21643) is another generous
program that has funded my research.
I want to express thanks to Professor Krein who gave me the opportunity to study
under him. He has devoted personal attention to both his undergraduate and graduate
students, as demonstrated through his well structured lectures and his regular student
advisory meetings. He has patiently mentored me for five years both technically and
professionally, and instilled the importance of quality research and writing—two virtues I
hope to maintain always. I have largely Joyce to thank for helping me execute that last
virtue. Joyce committed countless hours of individual attention to hone my writing skills.
A feat no elementary school, high school, or college teacher was willing to perform.
Thank you Joyce.
Graduate school has been a taxing process; I want to acknowledge Sheryl for her
moral support. Having a more patient companion go through the same process helped me
finish what I started. You accepted me for who I am—idiosyncrasies and all. I promise,
once we get our degrees we will go on our first vacation where I leave my work behind.
Mom and Dad, I want to thank you for giving me the resources I needed to succeed: a
nurturing home, a college education, and some needed discipline.
iv
The Power and Energy Systems group provided a unique opportunity to work with
and learn from other students within same specialization. In particular, I want to thank
Jonathan for giving me his advice on hardware design, Wayne for helping me through my
first control classes, and Brett and Nick for their willingness to share their engineering
experiences with me. I want to especially thank all those who worked on the modular
inverter. It was a valuable piece of equipment that saved me a lot of time. Also, I want to
thank my friends, Brian, Rodney, Trishan, Matt, Zeb, Jason, Marco, Zack, Joe, Tim,
Angel, Linda, and Kate. It was difficult being away from family and friends; your
hospitality at BBQs and attendance at Power Hours helped Sheryl and me to feel at home.
Finally, I want to thank all my professors whose lessons taught me the necessary
background for writing this dissertation: Prof. Delchamps for teaching all my
fundamental DSP classes, Prof. Land and Dan Block for teaching me embedded
programming, Prof. Chapman for teaching my power electronics and machines classes,
Prof. Overbye and Gross for teaching me power systems, and Profs. Kumar, Sauer and
Spong for their lessons on advanced control and system analysis.
v
TABLE OF CONTENTS
1
INTRODUCTION......................................................................................................1
2
POWER ELECTRONICS MODELING.................................................................6
2.1 Voltage Source Buck Converter Model .......................................................... 8
2.2 Boost Converter Modeling ............................................................................ 12
2.3 Voltage Source Inverter Modeling................................................................ 14
3
FAST POWER CONVERTERS VIA CONTROL ...............................................17
3.1 Review of Line Switching Surfaces .............................................................. 22
3.2 Review on Curved Switching Surfaces......................................................... 24
3.3 N-Switch Edge Trajectories .......................................................................... 29
3.4 Minimum-Time Disturbance Recovery ........................................................ 32
3.4.1 Multiple line surface generation .......................................................... 37
3.4.2 Raster-surface generation .................................................................... 44
3.4.3 Sensitivity and transient analysis ......................................................... 54
3.5 Parameter Observers ..................................................................................... 61
3.5.1 A priori and posteriori knowledge ....................................................... 62
3.5.2 Nonparametric versus parametric models ........................................... 63
3.5.3 Candidate power converter model ....................................................... 66
3.5.4 Discrete-time model ............................................................................ 67
3.5.5 Review of recursive least square algorithm ......................................... 68
3.5.6 System identification performance metrics ......................................... 70
3.5.7 Simulated results.................................................................................. 72
3.5.8 Hardware experiment .......................................................................... 75
4
FAST POWER CONVERTERS ............................................................................81
4.1 System Performance ..................................................................................... 82
4.2 Unknown Load Disturbances........................................................................ 86
4.3 Known Load Disturbances ............................................................................ 88
4.4 Conclusions ................................................................................................... 90
5
RAPID PROTOTYPES USING MODEL-BASED DESIGN ..............................92
5.1 Single-Phase Grid Connected Control .......................................................... 95
5.2 Direct Digital Synthesis ................................................................................ 97
5.3 All Digital Phase-Lock Loop ........................................................................ 99
5.4 Software in the Loop Experiment ............................................................... 102
5.5 Rapid Control Prototypes and System Products ......................................... 104
6
CONCLUSIONS AND FUTURE WORK ...........................................................110
REFERENCES .............................................................................................................. 112
APPENDIX A MATHCAD SYMBOLIC MODEL DERIVATIONS ................... 121
A.1 Constant-Resistance Buck Converter ......................................................... 121
A.2 Constant-Current Buck Converter .............................................................. 126
vi
A.3
A.4
Boost Converter .......................................................................................... 129
Voltage Source Inverter .............................................................................. 133
APPENDIX B SIMULINK CONTROL BLOCKS ................................................. 139
B.1 Voltage Mode Control (No Error Integrator).............................................. 139
B.2 One Cycle Control (No Error Integrator).................................................... 139
B.3 Peak Current Mode Control (No Error Integrator) ..................................... 139
B.4 Minimum Time Control (No Error Integrator) ........................................... 140
APPENDIX C SURFACE GENERATION ............................................................. 141
C.1 Rotated Line Surface Generation ................................................................ 141
C.2 Minimum-Time Surface Generation ........................................................... 142
C.3 Surface Approximation ............................................................................... 143
C.4 Raster Surface Search Algorithm................................................................ 145
C.5 Simulink Blocks: Main Block ..................................................................... 147
C.6 Simulink Blocks: Physical Power Converter Target .................................. 147
C.7 Simulink Code Blocks: Experiment Timers ............................................... 148
APPENDIX D SYSTEM IDENTIFICATION......................................................... 149
D.1 Continuous-Time Transfer Function Coefficients ...................................... 149
D.2 RLS Derivation with Sensor Scaling .......................................................... 151
D.3 Embedded RLS Function ............................................................................ 153
APPENDIX E GRID CONNECTED VSI ................................................................ 155
E.1 Open-Loop Control Derivations ................................................................. 155
E.2 SIL Root Block Diagram ............................................................................ 156
E.3 All Digital Phase Lock Loop ...................................................................... 157
E.4 Digital Controlled Oscillator....................................................................... 158
E.5 SIL—Inverter Startup Waveforms .............................................................. 159
E.6 SIL—Inverter Steady-State Waveform....................................................... 160
E.7 SIL—ADPLL Startup Waveforms ............................................................. 161
E.8 Hardware Grid Connected Inverter Block .................................................. 161
AUTHOR’S BIOGRAPHY .......................................................................................... 162
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1
INTRODUCTION
Switching mode power supplies (SMPSs) are found in applications requiring small
volume and weight, and efficient energy conversion. These traits have helped SMPSs
establish presence in most areas of science. Their design requires multidisciplinary
experience in circuits, thermodynamics, mechanics, electromagnetics, and system and
control theory. As a result, SMPSs use a diverse and often jumbled collection of
frequency and time-domain analyses, each with its own merits in electrical and
mechanical systems. Digital control adds to the jumble with similar, but less intuitive
domains.
Frequency-domain analysis discerns steady-state stability using phase and gain
margins, and performance using bandwidth and resonance. These metrics work well in
passive circuits for frequency content systems (e.g., voice, data, and radio [periodic
signals]). Time-domain analysis through differential equations, i.e., state-space
representation, lends itself readily to numerical simulations and real-world performance
metrics such as rise time, under- and overshoots, and slew rate. These metrics help
describe systems with large-signal content (e.g., motors, cars, and planes [trajectory
motion]). Although SMPSs are circuits, their switching and transient behavior is
conveniently modeled in the time-domain. Time-domain is emphasized in this work. It is
a powerful predesign tool, quantifies dynamic performance, and contains more rigorous
stability and sensitivity tools.
The digital-domain has sample-time and complex frequency-domain equivalents
for the previously mentioned continuous-time/frequency analyses. Its strength lies not in
its ability to mimic analog domains but in its ability to reformulate design problems. For
1
example, consider a bench-top power supply with binary i/o signals (current limit,
voltage limit, faults, optical encoded knobs, etc). Simple interfaces built from discrete
components and logic devices are one way to solve the problem, but complicated
interfaces are best left to semantic programming languages. Using software functions to
handle hardware problems greatly increases the designer toolset.
Modern motion control functions are organized into five groups: communication,
auxiliary functions, data acquisition and processing, power circuit interface, and system
logic and control algorithms [1]. The first two groups are strong motivators in featurerich designs. The last three directly affect output performance. The same groupings are
adopted in this work to describe programmable SMPS functions. Commercial ICs rely
heavily on communication protocols such as SPI, I2C, and SMBUS, and on system-level
protocols such as CAN. Auxiliary functions handle processes not directly involved in
plant control, such as monitoring, display, user input, and diagnostics. Data acquisition
and processing samples signals. System-logic and control algorithms govern output.
Power circuit interface generates switching signals.
Data acquisition is a specific research interest as it is the only listed digital function
that interacts with mixed signals. Here a/d converters transform the plant into a sampled
data system [2]. The traditional rule of thumb for linear systems is to sample 10 or more
times faster than the plant frequency. The rule applies to power electronics when the
switching frequency is 10 or more times faster than the averaged model frequency. This
rate depends primarily on its energy storage elements. Low-power converters have small
energy storage and thus need fast samplers and processors to keep loop speed near the
averaged system dynamics—one reason it has taken nearly three decades for industry to
2
adopt fully digital control loops in micro power systems. This dissertation investigates
nonlinear converter model performance, where the switching/control loop criterion does
not apply. Control-loop speed depends on processor architecture, clock rate, instruction
sets, memory, and bus width. The most common embedded architectures, ranked by
increased processor performance, are microcontroller units (MCU), digital signal
processors (DSP), and programmable logic devices (PLD) [3]. Programmable
architecture cost and functionality, along with the five function groups previously listed,
help define how digitally controlled power electronics evolved.
The first generation of digitally controlled power electronics (1960-70) contained
communication, auxiliary functions, and power circuit interfaces that supervised analog
control loops [4] in processes called direct digital control [5] and direct digital synthesis
[6]. Here, logic devices stored sampled switching functions [7] that could reduce
harmonics sent onto the utility grid [8]. The second generation used data acquisition and
processing to emulate the analog control loop in the digital domain [9]. Here control loop
speeds could handle averaged dynamics, and engineers had design tools that were
essentially the same as the analog design tools.
The third generation has system logic and control algorithms that fully utilize
processor capabilities. Here, control executes computationally intensive nonlinear control
and observer algorithms, and engineers have sophisticated software-aided design tools for
algorithm testing. Similar classifications were devised for power electronics control [10],
where generations were distinguished by sampling/switching speed. This dissertation
organizes the classifications according to the five function groups and engineering design
tools.
3
Third-generation designers have tools with new coding and test methods. These
address the need to improve workflows in macro power system projects, reduce
development time, and test thoroughly and systematically. Software abstractions such as
very high-level programming (VHLL), rapid control prototypes (RCP) [11], and
software/hardware in the loop (SIL/HIL) testing make large-scale problems manageable
for engineering teams. Success with these tools has been shown for dc distribution on
electric ships [12], controls of automobiles [13], and electric locomotives [14].
Finally, third-generation digital control must add value over the previous
generations. The value propositions in the power supply industry—―
more features,‖
―
better performance,‖ and ―r
educed time to market‖—are evident in the micro power
systems sector for low-voltage regulation over a wide range of loads, temperatures, and
set points. Voltage regulator modules (VRM ) are ubiquitous in commercial products.
This dissertation researches minimum-time disturbance recovery, system identification,
and active topology change for low-voltage regulators. It also investigates new
design/test procedures, SIL and RCP, using a voltage-source inverter (VSI) that connects
to the ac system.
The dissertation is organized as follows. Chapter 2 covers power electronics model
performance as defined by its circuit parameters. Models are essential components
adopted in third-generation control algorithms. In Chapter 3, simple dc-dc converter
models serve as predictors in fast performance controllers and as storage mechanisms in
system identification algorithms. Minimum-time control via numerical trajectory paths—
the fastest a fixed topology converter can react to any control or system disturbances—is
introduced. Numerical solutions stored as curved surfaces are tested in hardware
4
experiments. Minimum-time results indicate that parameter knowledge affects how well a
controller can react to disturbances. Identification algorithms can handle situations with
poor knowledge. A power converter can achieve performance beyond minimum-time
only if its topology or parameters change, as demonstrated in Chapter 4, through a
concept called converter augmentation. Chapter 5 shows how macro power systems can
be designed either top down or bottom up, like computer software, as is exemplified on
the Grainger Center modular inverter.
5
2
POWER ELECTRONICS MODELING
Modeling is an important step toward understanding SMPS control and system
limitations. Models serve as an ideal environment to compare theoretical with hardware
results, act as SIL for developing and testing complicated control algorithms, and store
plant knowledge in third-generation digital controllers. This section gives an overview of
system types, defines variables, and introduces the three power-converter models used
throughout the dissertation.
A general dynamical circuit model depends on a parameter vector, 𝜆, composed of
passive circuit components, 𝑅; energy store elements, 𝐿 and 𝐶; and power sources, 𝐸 and
𝐼. A circuit can have a controlled input vector, 𝑢. Its output depends on its internal state
vector, 𝑥, that contains currents, 𝑖𝐿 , through 𝐿, and voltages, 𝑣𝐶 , across 𝐶. The circuit
dynamics are governed by the differential vector equation,
𝑥 = 𝑓(𝑡, 𝑥, 𝑢, 𝜆).
(1)
This equation can model nonlinear circuits. Approximations and constraints can make the
equation practical for switching-circuit modeling and simulations. The first
approximation assumes that all elements in 𝜆 are constants. The approximation makes the
model an autonomous system composed of basic ideal circuit elements. The second
approximation assumes the system has ideal 𝑁 switches that can configure 2𝑁 linear
circuit network combinations. The third lets control configure these combinations with an
switch index, 𝑖. These three approximations comprise an autonomous piecewise linear
(PWL) system,
𝑓(𝑥, 𝜆, 𝑖) = 𝐴𝑖 𝜆 𝑥 + 𝐵𝑖 𝜆 ,
6
(2)
convenient for power electronics time-domain simulation. Here, 𝐴𝑖 (𝜆) and 𝐵𝑖 𝜆 are
parameter-dependant matrices for any switch index. Switching describes the transition
between different 𝑖. Numerically integrating (2), or summing its state-space solution, (3),
over every switch period, simulates voltage and current state trajectories [15] and is the
foundation for trajectory-based control [16, 17].
𝑥(𝑡, 𝑥0 , 𝜆, 𝑖) = 𝑒 𝐴𝑖 (𝜆)𝑡 𝑥0 +
𝑡
0
𝑒 𝐴𝑖 (𝜆)(𝑡−τ) 𝐵𝑖 (𝜆)𝑑𝜏.
(3)
Piecewise solutions can model nonlinear power electronics phenomena such as
limit cycles (a.k.a., ripple), but do not fit the linear system framework. PWL equations
integrate with time steps shorter than the switching period—leading to slow simulations.
When the switched system satisfies certain switching/parameter criteria, averaging can
approximate state trajectories [18, 19]. Averaging (sometimes called the small-ripple
approximation [20]) is rooted in singular perturbation theory whose results are
generalized in the time domain using the Krylov-Bogoliubov-Miltropolsky method and in
the frequency domain using multifrequency averaging methods [21, 22]. Averaging was
popularized in power electronics with a less general technique called state-space
averaging (SSA) [23], which removes ripple entirely. SSA combines matrices 𝐴𝑖 and 𝐵𝑖
into averaged matrices 𝐴𝑎𝑣𝑔 and 𝐵𝑎𝑣𝑔 using duty cycle control. The SSA buck, boost,
and inverter models, presented in Sections 2.1-2.3, fit the bilinear equation
𝑥 = 𝐴𝑎𝑣𝑔 𝜆 𝑥 + 𝑢 𝐵𝑎𝑣𝑔 𝜆 𝑥 + 𝛾 𝜆
+𝛿 𝜆 ,
(4)
where vectors 𝛾 and 𝛿 contain the model power sources [24].
The next three sections present symbolic SMPS models with the following format.
First, a circuit schematic shows the topology and defines its parameters; second, a
piecewise model (2) is shown; third, a bilinear (4), and lastly, a steady-state equation
7
describing the range of static equilibriums (a.k.a., a load line) are presented. The models
were derived using Mathcad™; the code is listed in Appendix A.
2.1
Voltage Source Buck Converter Model
The constant resistance load (CR) buck converter model shown in Fig. 1 has a
voltage source 𝐸1 , ideal switches 𝑞1 and 𝑞2 , inductor 𝐿1 , with equivalent series resistance
𝑅𝐿1 , capacitor 𝐶1 with equivalent series resistance 𝑅𝐶1 , and load 𝑅1 . It has a PWL model
(2), where
𝐴0 =
−
1
𝑅𝐿1 +𝑅1 𝑅𝐶1
𝐿1
1
𝑅+𝑅𝐶1
𝑅1
𝐶1
1
−
𝐿1
−
𝑅1 +𝑅𝐶1
1−
1
𝐶1
𝑅𝐶1
𝑅1 +𝑅𝐶1
1
,
𝑅1 +𝑅𝐶1
𝐴1 = 𝐴0 ,
𝐵0 =
𝑥=
0
,
0
𝑖𝐿
𝑣𝐶
and
𝐵1 =
𝐸1
𝐿1
0
.
Fig. 1 Constant-resistance buck converter schematic
𝐴0 and 𝐵0 are the state matrices when 𝑞1 is open and 𝑞2 closed, and 𝐴1 and 𝐵1 are the
matrices when 𝑞1 is closed and 𝑞2 open. Its SSA model is (4), where
8
−
𝐴𝑎𝑣𝑔 =
1 𝑅1 𝑅𝐿1 + 𝑅1 𝑅𝐶1 + 𝑅𝐿1 𝑅𝐶1
𝐿1
𝑅1 + 𝑅𝐶1
1
𝑅1
𝐶1 𝑅1 + 𝑅𝐶1
Bavg =
1
𝑅1
𝐿1 𝑅1 + 𝑅𝐶1
,
1
1
−
𝐶1 𝑅1 + 𝑅𝐶1
−
0 0
,
0 0
𝐸
𝛾= 𝐿 ,
0
𝛿=
0
,
0
and
𝑢 = 𝑑.
Duty cycle 𝑑 is the duration during which 𝑞1 is closed. The SSA buck model has a
continuum of infinite switching frequency equilibrium points,
𝐸1
𝑥𝑒 (𝜆, 𝑢) =
𝑅1 +𝑅𝐿1
𝐸1 𝑅1
𝑅+𝑅𝐿1
𝑢
𝑢
,
(5)
defined over the duty cycle range, (0,1). The linear time invariant (LTI) model applies
directly to linear-system and control-theory frameworks, a property used extensively in
Section 3.5.
The constant current load (CC) buck converter, shown in Fig. 2, has constantcurrent output 𝐼0 . The approximation is popular for small-signal modeling. It simplifies
analysis and accurately approximates constant-resistance dynamics, but cannot accurately
approximate its large-signal equilibria, as will be shown mathematically. The CC buck
converter produces a PWL model (2), where
9
𝐴0 =
−
1
𝑅𝐿1 + 𝑅𝐶1
𝐿1
1
−
1
𝐿1
0
𝐶1
,
𝐴1 = 𝐴0 ,
𝐼0 𝑅𝐶1
𝐵0 =
𝐿1
𝐼0
–
,
𝐶1
and
𝐸1 + 𝐼0 𝑅𝐶1
𝐿1
𝐵1 =
𝐼0
–
𝐶1
The SSA produces the bilinear differential equation (4), where
𝐴𝑎𝑣𝑔 =
−
1
𝐿1
𝑅𝐿1 + 𝑅𝐶1
1
𝛾=
0
0
𝐸1
𝐿1
0
0
,
0
,
and
𝐼𝑜 𝑅𝐿1
𝛿=
1
𝐿1
0
𝐶1
𝐵𝑎𝑣𝑔 =
−
𝐿1
𝐼0
–
,
𝐶1
Fig. 2 Constant-current buck converter schematic
10
,
The SSA model has a continuum of infinite switching equilibria,
𝑥𝑒 (𝜆, 𝑢) =
𝐼0
,
𝐸1 𝑢 − 𝐼0 𝑅𝐿1
(6)
defined over the range of 𝑢.
The SSA buck converter models accurately approximate fast-switching PWL
models when 𝑞1 and 𝑞2 are bidirectional-conducting bidirectional-blocking (as with
synchronous buck converters), or 𝑞2 is forward-conducting reverse-blocking with
𝑖𝐿 𝑡 > 0 (as with continuous conduction mode (CCM) buck converters containing
freewheeling diodes). The CC and CR buck converter models were verified by simulating
CCM startup for a PWL model superimposed on its SSA approximation, as shown in Fig.
3 and Fig. 4, respectively.
More complicated SMPS modeling can become a tedious and time-consuming
endeavor. Modern simulation packages have somewhat alleviated modeling effort (e.g.,
Piecewise Linear Electrical Circuit Simulator [PLECS]) with functions that can extract
indexed state matrices from graphical circuit schematics. Unfortunately, these functions
lump components and evaluate them as numeric matrices. Symbolic matrices provide
Fig. 3 PWL / SSA CR buck converter comparison
(𝑅𝐿1 = 10 mΩ, 𝑅𝐶1 = 10 mΩ, 𝐸1 = 5 V, 𝑅1 = 1 Ω, 𝐿1 = 5 mH, 𝐶1 = 100 μF, and
𝑢 = 0.2)
11
Fig. 4 PWL/SSA CC Buck converter comparison (𝑅𝐿1 = 10 mΩ, 𝑅𝐶1 = 12 mΩ, 𝐸1 =
10 V, 𝐼𝑜 = 4.167 A, 𝐿1 = 0.8 mH, 𝐶1 = 1.29 mF, and 𝑢 = 0.313)
valuable insight into how components affect system performance. This dissertation
presents symbolic equations whenever possible. The symbolic derivations for CR and CC
buck converter models are given in Appendices A.1 and A.2, respectively.
2.2
Boost Converter Modeling
The boost converter model, shown in Fig. 5, has the same component variables as
defined in Section 2.1. This topology produces the PWL model (2), where
𝐴0 =
−
𝑅𝐿1
𝐿1
1
𝐶1
𝐴1 =
−
−
−
𝑅𝐿1
−
,
𝑅1 𝐶1
0
𝐿1
0
1
𝐿1
1
1
𝑅1 𝐶1
𝐸1
𝐵0 = 𝐿1
0
and
𝐵1 = 𝐵0 .
12
,
Fig. 5 Boost converter schematic
The SSA for the model produces the bilinear differential equation (4), where
𝐴𝑎𝑣𝑔 =
𝐵𝑎𝑣𝑔 =
−
𝑅𝐿1
0
𝐿1
1
0
𝑅1 𝐶1
1
0
−
𝛾=
𝛿=
,
𝐿1
𝑅1
0
𝑅1 𝐶1
,
0
,
0
𝐸1
𝐿1
0
,
and
𝑢 =𝑑−1
Duty cycle 𝑑 is the duration in which 𝑞1 is closed. The SSA model approximates the
PWL model under the same conditions specified for the CR and CR buck converters
described in Section 2.1.
𝐸1
𝑥𝑒 (𝜆, 𝑢) =
𝑅1 𝑢 2 +𝑅𝐿1
𝐸1 𝑅1 𝑢
𝑅1 𝑢 2 +𝑅𝐿1
(7)
Numerical integration easily simulates bilinear circuit models. The models were verified
by simulating the PWL and SSA model for a CCM startup condition, as shown in Fig. 6.
Linearization reduces the bilinear model to fit the linear control framework. Such a
13
reduction is useful for systematically defining linear feedback gains [25]. The process
discards large-signal behavior and approximates local dynamic behavior about 𝑥𝑒 . The
symbolic derivations for previous equations are shown in Appendix A.3
=
Fig. 6 PWL/SSA boost converter comparison (𝑅𝐿1 = 10 mΩ, 𝑅𝐶1 = 0 mΩ, 𝐸1 = 5 V,
𝑅1 = 1 Ω, 𝐿1 = 5 mH, 𝐶1 = 100 μF, and 𝑢 = 0.2)
2.3
Voltage Source Inverter Modeling
The voltage source inverter (VSI) model, shown in Fig. 7, has the same
components and variables as defined in Section 2.1. This topology produces the PWL
model (2), where
𝐴0 =
−
𝑅𝐿1
−
𝐿1
1
−
𝐶1
−
𝐴1 =
𝐴2 =
𝑅𝐿1
𝐿1
𝑅1 𝐶1
1
𝐿1
1
𝐿1
1
−
𝐶1
𝐵0 =
,
1
−
𝑅1 𝐶1
𝑅𝐿1
−
,
0
0
−
1
𝐿1
1
𝐸1
𝐿1
0
𝑅1 𝐶1
,
14
,
and
𝐵2 = 𝐵1 = 𝐵0 .
Here, 𝑖 = 0 when 𝑞1 and 𝑞2 are closed and 𝑞3 and 𝑞4 are open; 𝑖 = 1 when 𝑞1 and 𝑞2 are
closed and 𝑞3 and 𝑞4 are open; and 𝑖 = 2 when 𝑞1 and 𝑞2 are closed and 𝑞3 and 𝑞4 are
open. The circuit is classified as a switch matrix [26], which creates multiple power
converters based on index combinations. A system with 𝑖 = 0,2 is a two-level VSI
inverter. A system with 𝑖 = {0,1,2} is a three-level VSI. A system with 𝐸1 (𝑡) =
170sin⁡
(120𝜋𝑡) is a grid-connected VSI inverter. The three-level VSI produces the
bilinear differential equation (4), where
𝐴𝑎𝑣𝑔 =
−
𝑅𝐿1
0
𝐿1
1
0
𝑅1 𝐶1
0
𝐵𝑎𝑣𝑔 =
−
𝑅1
1
𝐿1
0
𝑅1 𝐶1
𝛾=
,
,
0
,
0
and
𝛿=
𝐸1
𝐿1
0
.
The input, 𝑢 = 𝑑 − 1, is the 𝑞2 duty cycle with values −1,1 , as was modeled in [27].
The SSA approximates the PWL model when devices switch quickly. The SSA model
has a continuum of infinite switching equilibrium points,
𝐸1
𝑥𝑒 (𝜆, 𝑢) =
𝑅1 𝑢 2 +𝑅𝐿1
𝐸1 𝑅1 𝑢
𝑅1 𝑢 2 +𝑅𝐿1
15
(8)
The bilinear VSI model was tested by simulating startup for a VSI that boosts grid
voltage. The converter drew an ac inductor current and produced a dc bus voltage that fed
a resistive load, as shown in Fig. 8. The symbolic derivations for all these equations are
shown in Appendix A.4.
Fig. 7 Grid-connected VSI schematic
The models presented in Chapter 2 are applied in various sections of this
dissertation. Section 3.4 uses them to create minimum-time solutions, Section 3.5 to store
parameter estimates, and Chapter 5 to emulate and test plant/control in model based
design.
Fig. 8 PWL/SSA VSI comparison (𝑅𝐿1 = 0.5 Ω, 𝑅𝐶1 = 0 mΩ,
𝐸1 (𝑡) = 170 sin 120𝜋𝑡 V, 𝑅1 = 500 Ω, 𝐿1 = 5 mH, 𝐶1 = 1 mF, and 𝑢 = 0.4)
16
REFERENCES
[1]
L.-H. Hoang, "Microprocessors and digital ICs for motion control," Proceedings
of the IEEE, vol. 82, pp. 1140-1163, 1994.
[2]
G. F. Franklin, J. D. Powell, and M. L. Workman, Digital Control of Dynamic
Systems, 3rd ed. Menlo Park, CA: Addison-Wesley, 1998.
[3]
R. Cravotta, "Processing options," Electronic News, 2006, pp. 42-50.
[4]
C. B. Casteel and R. G. Hoft, "Optimum PWM waveforms of a microprocessor
controlled inverter," in IEEE Power Electronics Specialist Conference, Syracuse,
NY, 1978, pp. 243-250.
[5]
W. G. Wilbanks, "50 years of progress in measuring and controlling industrial
processes," IEEE Control Systems Magazine, vol. 16, pp. 64-66, 1996.
[6]
J. Tierney, C. Rader, and B. Gold, "A digital frequency synthesizer," IEEE
Transactions on Audio and Electroacoustics, vol. 19, pp. 48-57, 1971.
[7]
S. R. Bowes, "New sinusoidal pulse-width modulated invertor," in IEE
Proceedings, 1975, pp. 1279-1285, vol. 122.
[8]
H. S. Patel and R. G. Hoft, "Generalized techniques of harmonic elimination and
voltage control in thyristor inverters: Part I harmonic elimination," IEEE
Transactions on Industry Applications, vol. IA-9, pp. 310-317, 1973.
[9]
H. Matsuo, F. Kurokawa, and K. Higashi, "Dynamic characteristics of the
digitally controlled DC-DC converter," IEEE Transactions on Power Electronics,
vol. 4, pp. 419-426, 1989.
[10]
J. Kimball, "Digital control techniques for switching power converters," Ph.D.
dissertation, University of Illinois at Urbana-Champaign, 2007.
[11]
A. Monti, E. Santi, R. A. Dougal, and M. Riva, "Rapid prototyping of digital
controls for power electronics," IEEE Transactions on Power Electronics, vol. 18,
pp. 915-923, 2003.
[12]
W. Ren, L. Qian, Y. Liu, M. Steurer, and D. Cartes, "Real time digital simulations
augmenting the development of functional reconfiguration of PEBB and universal
controller," in American Control Conference, 2005, pp. 2005-2010, vol. 3.
[13]
Q. Zheng, W. Chung, K. Defore, and A. Herman, "A Hardware-in-the-loop Test
Bench for Production Transmission Controls Software Quality Validation," in
SAE World Congress & Exhibition, Detroit, MI, 2007, pp. 1-11, vol. 2007-010502.
112
[14]
P. Terwiesch, T. Keller, and E. Scheiben, "Rail vehicle control system integration
testing using digital hardware-in-the-loop simulation," IEEE Transactions on
Control Systems Technology, vol. 7, pp. 352-362, 1999.
[15]
W. W. Burns and T. G. Wilson, "State trajectories used to observe and control dcto-dc converters," IEEE Transactions on Aerospace and Electronic Systems, vol.
AES-12, pp. 706-717, 1976.
[16]
W. W. Burns and T. G. Wilson, "Analytic derivation and evaluation of a state
trajectory control law for dc-dc converters," in IEEE Power Electronics
Specialists Conference, Palo Alto, CA, 1977, pp. 70-85.
[17]
W. W. Burns and T. G. Wilson, "A state-trajectory control law for dc-to-dc
converters," IEEE Transactions on Aerospace and Electronic Systems, vol. 14,
pp. 2-20, 1978.
[18]
P. T. Krein, J. Bentsman, R. M. Bass, and B. L. Lesieutre, "On the use of
averaging for the analysis of power electronic systems," IEEE Transactions on
Power Electronics, vol. 5, pp. 182-190, 1990.
[19]
B. Lehman and R. M. Bass, "Extensions of averaging theory for power electronic
systems," IEEE Transactions on Power Electronics, vol. 11, pp. 542-553, 1996.
[20]
R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics, 2nd ed.
Norwell, MA: Kluwer Academic, 2001.
[21]
R. M. Bass and J. Sun, "Large-signal averaging methods under large ripple
conditions," in IEEE Power Electronics Specialists Conference, 1998, pp. 630632, vol. 1.
[22]
J. W. Kimball and P. T. Krein, "Singular perturbation theory for dc-dc converters
and application to PFC converters," in IEEE Power Electronics Specialists
Conference, Orlando, FL, 2007, pp. 882-887.
[23]
R. D. Middlebrook and S. Ćuk, "A general unified approach to modeling
switched-converter power stages," in IEEE Power Electronics Specialists
Conference, 1976, pp. 18-34.
[24]
H. Sira-Ramirez, "Sliding motions in bilinear switched networks," IEEE
Transactions on Circuits and Systems, vol. 34, pp. 919-933, 1987.
[25]
C. Gezgin, B. S. Heck, and R. M. Bass, "Control structure optimization of a boost
converter: An LQR approach," in IEEE Power Electronics Specialists
Conference, 1997, pp. 901-907, vol. 2.
[26]
P. T. Krein, Elements of Power Electronics. New York: Oxford University Press,
1998.
113
[27]
H. Sira-Ramírez and R. Silva-Ortigoza, Control Design Techniques in Power
Electronics Devices. London, England: Springer-Verlag London Limited, 2006.
[28]
A. F. Rozman and K. J. Fellhoelter, "Circuit considerations for fast, sensitive,
low-voltage loads in a distributed power system," in IEEE Applied Power
Electronics Conference and Exposition, Dallas, Texas, 1995, pp. 34-42.
[29]
W. Pit-Leong, F. C. Lee, Z. Xunwei, and C. Jiabin, "VRM transient study and
output filter design for future processors," in IEEE Industrial Electronics Society
Conference Aachen, Germany, 1998, pp. 410-415, vol. 1.
[30]
E. Grochowski and M. Annavaram, "Energy per instruction trends in Intel
microprocessors," Technology @ Intel Magazine, 2006, pp. 1-8.
[31]
Intel Technical Staff, Enhanced Intel SpeedStep Technology for the Intel Pentium
M Processor, 2004.
[32]
Intel Technical Staff, Intel Core 2 Extreme Quad-Core Processor QX6000
Sequence and Intel Core 2 Quad Processor Q 600 Sequence, 2007.
[33]
Intel Technical Staff, Voltage Regulator-Down (VRD) 11.0 Processor Power
Delivery Design Guidelines, 2006.
[34]
Linear Technology Corporation, 3-Phase Buck Controller for Intel
VRM9/VRM10 with Active Voltage Positioning, 2004.
[35]
ON Semiconductor Technical Staff, Three−Phase VRM 9.0 Buck Controller,
2007.
[36]
Linear Technology, Active Voltage Positioning Reduces Output Capacitors, 1999.
[37]
K. Yao, Y. Ren, J. Sun, K. Lee, M. Xu, J. Zhou, and F. C. Lee, "Adaptive voltage
position design for voltage regulators," in IEEE Applied Power Electronics
Conference and Exposition, 2004, pp. 272-278, vol. 1.
[38]
M. Zhang, "Powering Intel Pentium 4 generation processors," in Intel Technology
Symposium, 2000, pp. 215-218.
[39]
R. Redl and N. O. Sokal, "Near-optimum dynamic regulation of DC-DC
converters using feed-forward of output current and input voltage with currentmode control," IEEE Transactions on Power Electronics, vol. 1, pp. 181-192,
1986.
[40]
B. C. Kuo, Digital Control Systems, 2nd ed. Ft. Worth, TX: Saunders College
Pub., 1992.
114
[41]
J. T. Mossoba and P. T. Krein, "Exploration of deadbeat control for dc-dc
converters as hybrid systems," in IEEE Power Electronics Specialists Conference,
2005, pp. 1004-1010.
[42]
W. Stefanutti, E. Tedeschi, P. Mattavelli, and S. Saggini, "Digital deadbeat
control tuning for dc-dc converters using error correlation," in IEEE Power
Electronics Specialists Conference, 2006, pp. 1-6.
[43]
B. Lehman and R. M. Bass, "Switching frequency dependent averaged models for
PWM dc-dc converters," IEEE Transactions on Power Electronics, vol. 11, pp.
89-98, 1996.
[44]
V. Utkin, "Variable structure systems with sliding modes," IEEE Transactions on
Automatic Control, vol. 22, pp. 212-222, 1977.
[45]
J. P. LaSalle, "Time optimal control systems," Proceedings of the National
Academy of Sciences of the United States of America, vol. 45, pp. 573-577, 1959.
[46]
K. M. Smedley and S. Cuk, "One-cycle control of switching converters," in IEEE
Power Electronics Specialists Conference, Cambridge, MA, 1991, pp. 888-896.
[47]
K. M. Smedley, "One-cycle controlled switching circuit " U. S. Patent 5,278,490,
January 11, 1994.
[48]
V. Utkin, J. Guldner, and J. Shi, Sliding Mode Control in Electromechanical
Systems: Taylor & Francis, 1999.
[49]
H. K. Khalil, Nonlinear Systems, 3rd ed. Upper Saddle River, NJ: Prentice Hall,
2002.
[50]
R. Munzert, "Boundary control, applied to dc-to-dc converter circuits," Ph.D
dissertation, University of Illinois at Urbana-Champaign, 1995.
[51]
H. Hermes and J. P. LaSalle, Functional Analysis and Time Optimal Control.
New York, NY: Academic Press, 1969.
[52]
A. Soto, A. de Castro, P. Alou, J. A. Cobos, J. Uceda, and A. Lotfi, "Analysis of
the Buck Converter for Scaling the Supply Voltage of Digital Circuits," IEEE
Transactions on Power Electronics, vol. 22, pp. 2432-2443, 2007.
[53]
G. Lafferriere and H. Sussmann, "Motion planning for controllable systems
without drift," in IEEE International Conference on Robotics and Automation,
1991, pp. 1148-1153, vol. 2.
[54]
H. J. Sussmann and W. Liu, "Motion planning and approximate tracking for
controllable systems without drift," in 25th Annual Conference on Information
Sciences and Systems, Johns Hopkins University, 1991, pp. 547-551.
115
[55]
C.-T. Chen, Linear System Theory and Design, 3rd ed. New York, NY: Oxford
University Press, 1999.
[56]
W. Kaplan, Advanced Calculus, 5th ed. Boston, MA: Addison Wesley, 2002.
[57]
D. Biel, L. Martinez, J. Tenor, B. Jammes, and J. C. Marpinard, "Optimum
dynamic performance of a buck converter," in IEEE International Symposium on
Circuits and Systems, Atlanta, GA 1996, pp. 589-592 vol.1, vol. 1.
[58]
D. Biel, J. López, Y. Pérez, L. Martinez-Salamero, B. Jammes, and J. C.
Marpinard, "Minimum-time control of a buck converter for bipolar square-wave
generation," in Fifth European Space Power Conference Tarragona, Spain, 1998,
pp. 345-349.
[59]
E. Fossas and D. Biel, "A sliding mode approach to robust generation on DC-toDC nonlinear converters," in IEEE International Workshop on Variable Structure
Systems, Tokyo, Japan, 1996, pp. 67-71.
[60]
K. K. S. Leung and H. S. H. Chung, "Derivation of a second-order switching
surface in the boundary control of buck converters," IEEE Power Electronics
Letters, vol. 2, pp. 63-67, 2004.
[61]
M. Ordonez, M. T. Iqbal, and J. E. Quaicoe, "Selection of a curved switching
surface for buck converters," IEEE Transactions on Power Electronics, vol. 21,
pp. 1148-1153, 2006.
[62]
J. Y. C. Chiu, K. K. S. Leung, and H. S. H. Chung, "High-order switching surface
in boundary control of inverters," IEEE Transactions on Power Electronics, vol.
22, pp. 1753-1765, 2007.
[63]
K. Au, C. Ho, H. Chung, W. Lau, and W. Yan, "Digital implementation of
boundary control with second-order switching surface for inverters," in IEEE
Power Electronics Specialists Conference, Orlando, FL, 2007, pp. 1658-1664.
[64]
V. Yousefzadeh, A. Babazadeh, B. Ramachandran, L. Pao, D. Maksimovic, and
E. Alarcon, "Proximate time-optimal digital control for dc-dc converters," in
IEEE Power Electronics Specialists Conference, Orlando, FL, 2007, pp. 124-130.
[65]
A. Costabeber, L. Corradini, P. Mattavelli, and S. Saggini, "Time optimal,
parameters-insensitive digital controller for DC-DC buck converters," in IEEE
Power Electronics Specialists Conference, Rhodes, Greece, 2008, pp. 1243-1249.
[66]
M. Greuel, R. Muyshondt, and P. T. Krein, "Design approaches to boundary
controllers," in IEEE Power Electronics Specialists Conference, St. Louis, MO
1997, pp. 672-678, vol. 1.
116
[67]
G. E. Pitel and P. T. Krein, "Trajectory paths for dc-dc converters and limits to
performance," in IEEE Workshops on Computers in Power Electronics, Troy,
NY, 2006, pp. 40-47.
[68]
G. E. Pitel and P. T. Krein, "Minimum-time digital control with raster surfaces,"
in IEEE Workshops on Computers in Power Electronics, Zurich, Switzerland,
2008, pp. 1-8.
[69]
E. Meyer and L. Yan-Fei, "A practical minimum time control method for Buck
converters based on capacitor charge balance," in IEEE Applied Power
Electronics Conference and Exposition, 2008, pp. 10-16.
[70]
Z. Zhao, V. Smolyakov, and A. Prodic, "Continuous-time digital signal
processing based controller for high-frequency dc-dc converters," in Applied
Power Electronics Conference, APEC 2007 - Twenty Second Annual IEEE, 2007,
pp. 882-886.
[71]
R. Kennel and A. Linder, "Predictive control of inverter supplied electrical
drives," in IEEE Power Electronics Specialists Conference, Galway, Ireland,
2000, pp. 761-766, vol. 2.
[72]
A. Khaligh and P. Chapman, "Reduction of output capacitance in dc-dc
converters using anticipated load transients," in IEEE Applied Power Electronics
Conference and Exposition, 2008, pp. 818-823.
[73]
K. K. S. Leung and H. S. H. Chung, "Use of second-order switching surface in the
boundary control of buck converter," in IEEE Power Electronics Specialists
Conference, 2004, pp. 1587-1593, vol. 2.
[74]
M. J. Laufenberg, "Dynamic sensitivity functions and the stability of power
systems with facts controllers," Ph.D. dissertation, University of Illinois at
Urbana-Champaign, 1997.
[75]
K. D. Young, V. I. Utkin, and U. Ozguner, "A control engineer's guide to sliding
mode control," IEEE Transactions on Control Systems Technology, vol. 7, pp.
328-342, 1999.
[76]
G. E. Pitel and P. T. Krein, "Real-time system identification for load monitoring
and transient handling of dc-dc supplies," in IEEE Power Electronics Specialist
Conference, Rhodes, Greece, 2008, pp. 3807-3813.
[77]
K. J. Astrom, "Adaptive control around 1960," in IEEE Conference on Decision
and Control, 1995, pp. 2784-2789 vol.3, vol. 3.
[78]
P. Wellstead, D. Prager, and P. Zanker, "Pole assignment self tuning regulator," in
IEE Proceedings, 1979, pp. 781-787, vol. 126.
117
[79]
C. C. Hang, Y. S. Cai, and K. W. Lim, "A dual-rate self-tuning pole-placement
controller," IEEE Transactions on Industrial Electronics, vol. 40, pp. 116-129,
1993.
[80]
L. Amoroso, M. Donati, X. Zhou, and F. C. Lee, "Single shot transient suppressor
(SSTS) for high current high slew rate microprocessor," in IEEE Applied Power
Electronics Conference and Exposition, Dallas, TX, 1999, pp. 284-288, vol. 1.
[81]
T. P. Duffy, R. Goodfellow, M. Trivedi, K. Mori, and B. Tang, "System, Device
and Method for Providing Voltage Regulation to a Microelectronic Device," U. S.
Patent 6,965,502, February 22, 2002.
[82]
G. E. Pitel and P. T. Krein, "Transient reduction of dc-dc converters via
augmentation and geometric control," in IEEE Power Electronics Specialists
Conference, Orlando, FL, 2007, pp. 1652-1657.
[83]
L. Ljung, System Identification: Theory for the User, 2nd ed. Upper Saddle River,
NJ: Prentice Hall PTR, 1999.
[84]
P. P. J. van den Bosch and A. C. v. d. van den Klauw, Modeling, Identification,
and Simulation of Dynamical Systems. Boca Raton, FL: CRC Press, 1994.
[85]
B. Johansson and M. Lenells, "Possibilities of obtaining small-signal models of
DC-to-DC power converters by means of system identification," in International
Telecommunications Energy Conference, 2000, pp. 65-75.
[86]
B. Miao, R. Zane, and D. Maksimovic, "System identification of power
converters with digital control through cross-correlation methods," IEEE
Transactions on Power Electronics, vol. 20, pp. 1093-1099, 2005.
[87]
B. Johansson and M. Lenells, "Possibilities of obtaining small-signal models of
DC-to-DC power converters by means of system identification," in Twentysecond International Telecommunications Energy Conference, Phoenix, AZ,
2000, pp. 65-75.
[88]
M. M. Peretz and S. Ben-Yaakov, "Time domain identification of PWM
converters for digital controllers design," in IEEE Power Electronics Specialists
Conference, Orlando, FL, 2007, pp. 809-813.
[89]
L. Lenhart and G. Svante, "Adaptation and tracking in system identification--A
survey," Automatica, vol. 26, pp. 7-21, 1990.
[90]
D. Paulo Sergio, Adaptive Filtering: Algorithms and Practical Implementation,
2nd ed. Nowell, MA: Kluwer Academic Publishers, 2002.
[91]
X. Yuncan, Y. Qiwen, and Q. Jixin, "Combined algorithm for systems with abrupt
but infrequent parameter changes based on robust minmax and EW-RLS
118
estimation," in IEEE International Conference on Systems, Man and Cybernetics,
2003, pp. 177-180, vol. 1.
[92]
Z. Xunwei, X. Peng, and F. C. Lee, "A novel current-sharing control technique
for low-voltage high-current voltage regulator module applications," IEEE
Transactions on Power Electronics, vol. 15, pp. 1153-1162, 2000.
[93]
Intersil Technical Staff, Digital Multiphase Controller, 2006.
[94]
Primarion Technical Staff, VR11 Digital Multiphase Controller, 2006.
[95]
S. R. Sanders, W. Albert, and R. Rossetti, "Active clamp circuits for switchmode
regulators supplying microprocessor loads," in IEEE Power Electronics
Specialists Conference, St. Louis, MO, 1997, pp. 1179-1185, vol. 2.
[96]
A. M. Wu and S. R. Sanders, "An active clamp circuit for voltage regulation
module (VRM) applications," IEEE Transactions on Power Electronics, vol. 16,
pp. 623-634, 2001.
[97]
P. Midya and P. T. Krein, "Feed-forward active filter for output ripple
cancellation," International Journal of Electronics, vol. 77, pp. 805-818, 1994.
[98]
G. F. Franklin, J. D. Powell, and A. Emami-Naeini, Feedback Control of Dynamic
Systems, 4th ed. Upper Saddle River, NJ: Prentice Hall, 2002.
[99]
P. T. Krein, "Feasibility of geometric digital controls and augmentation for
ultrafast dc-dc converter response," in IEEE Workshops on Computers in Power
Electronics 2006, 2006, pp. 48-56.
[100] B. Curtis, H. Krasner, and N. Iscoe, "A field study of the software design process
for large systems," Communications of the ACM, vol. 31, pp. 1268-1287 1988.
[101] C. A. Ayres and I. Barbi, "Power recycler for dc power supplies burn-in test:
Design and experimentation," in IEEE Applied Power Electronics Conference
and Exposition, 1996, pp. 72-78, vol. 1.
[102] E. A. Vendrusculo and J. A. Pomilio, "High-efficiency regenerative electronic
load using capacitive idling converter for power sources testing," in IEEE Power
Electronics Specialists Conference, 1996, pp. 969-974, vol. 2.
[103] S. Gupta, V. Rangaswamy, and R. Ruth, "Load bank elimination for UPS testing,"
in Industry Applications Society Annual Meeting, 1990, pp. 1040-1043.
[104] C. E. Lin, M. T. Tsai, W. I. Tsai, and C. L. Huang, "Consumption power feedback
unit for power electronics burn-in test," in 21st International Conference on
Industrial Electronics, Control, and Instrumentation, Orlando, FL, 1995, pp. 284289, vol. 1.
119
[105] F. Caricchi, F. Crescimbini, G. Noia, and D. Pirolo, "Experimental study of a
bidirectional DC-DC converter for the DC link voltage control and the
regenerative braking in PM motor drives devoted to electrical vehicles," in IEEE
Applied Power Electronics Conference and Exposition, Orlando, FL 1994, pp.
381-386.
[106] D. Logue and P. T. Krein, "The power buffer concept for utility load decoupling,"
in IEEE Power Electronics Specialists Conference, 2000, pp. 973-978, vol. 2.
[107] B. Singh, B. N. Singh, A. Chandra, K. Al-Haddad, A. Pandey, and D. P. Kothari,
"A review of single-phase improved power quality ac-dc converters," IEEE
Transactions on Industrial Electronics, vol. 50, pp. 962-981, 2003.
[108] J. Kimball, M. Amrhein, A. Kwasinski, J. Mossoba, B. Nee, Z. Sorchini, W.
Weaver, J. Wells, and G. Zhang, "Modular inverter for advanced control
applications," University of Illinois at Urbana-Champaign, Tech. Rep. UILUENG-2006-2504, May 2006.
[109] UL 1741, Inverters, Converters, and Controllers for Use in Independent Power
Systems, Underwriters Laboratory, 1999.
[110] IEEE Std. 1547-2003, Interconnecting Distributed Resources with Electric Power
Systems, IEEE, 2003.
[111] J. R. Rodriguez, J. W. Dixon, J. R. Espinoza, J. Pontt, and P. Lezana, "PWM
regenerative rectifiers: State of the art," IEEE Transactions on Industrial
Electronics, vol. 52, pp. 5-22, 2005.
[112] G. Escobar, D. Chevreau, R. Ortega, and E. Mendes, "An adaptive passivitybased controller for a unity power factor rectifier," IEEE Transactions on Control
Systems Technology, vol. 9, pp. 637-644, 2001.
[113] P. Mattavelli, G. Escobar, and A. M. Stankovic, "Dissipativity-based adaptive and
robust control of UPS," IEEE Transactions on Industrial Electronics, vol. 48, pp.
334-343, 2001.
[114] J. A. Sanchez, S. Vazquez, J. M. Carrasco, E. Galvan, E. Dominguez, M. Reyes,
and G. Escobar, "Digital implementation issues for a three-phase power converter
development using a repetitive control scheme," in IEEE International
Symposium on Industrial Electronics, 2007, pp. 667-672.
[115] L. Cordesses, "Direct digital synthesis: A tool for periodic wave generation (part
1)," IEEE Signal Processing Magazine, 2004, pp. 50-54,vol. 21.
[116] D. Xu, Y. W. Li, and B. Wu, "Direct PWM synchronization using an all digital
phase-locked loop for high power grid-interfacing converters," in IEEE Applied
Power Electronics Conference, Anaheim, CA, 2007, pp. 901-906.
120
121
APPENDIX A MATHCAD SYMBOLIC MODEL DERIVATIONS
A.1
Constant-Resistance Buck Converter
NON-IDEAL AVERAGED A BUCK CONVERTER WITH CONSTANT RESISTANCE LOAD
Full Model
Active switch on
substitute ,13
Vc + R esr · iL
= ----R+ Resr
--> 12
=
simplify
Vc- R· iL
R + Resr
state equations:
R· Resr"
Vc - R· iL
dYe
vc-R·iL
dt
C 2 · ( R + Resr )
dYe
-
dt
dve
expand,vc , iL ----+ -
=
dt
1
R
1
1
C
R+ Resr
C
R+ Resr
= -. - - - . iL - - . - - - , Yc
122
i
Active switch off
substitute ,13
vC+Resr"iL
= ----R + Resr
--> 12
=
simplify
dve
-
dt
dve
-
dt
dve
dt
1
1
C2
C2
= - . ic = 1
= -.
(
iL -
1
.12 = - .
C2
Vc + R esr · iL)
R + Resr
C2
vc-R·iL
C2
·
(i L -
13)
1
(
= - . iL C2
substitute,I2
dve
expand,vc , iL ----+ ( R + Resr )
cit
=
=
ve + R,~, .
iL)
----R + R,~,
Vc - R· iL
R + Resr
dve
----+ dt
=
Vc - R· iL
C 2 · (R + Resr)
dve
-
dt
123
1
R
C
R+ Resr
= -. - - - .
1
1
C
R+ Resr
iL - - . - - - . Vc
R . Rdcr + R . Resr + Rdcr . Resr
L . (R:
L· (R + Resr)
R
C. (R
R,~,) l
~ R,~,) J
BavgCE,L, d) :~ Mavg(B(E,L) ,d)
Bavg is
BavgCE, L, d) simplify
The L TI buck model is
dx avg
-- =
dt
Aavg . x avg
+ Bavg' u
where
u
=
d
The input duty to state transfer function H(s) is
H(s) = yes) = c . (s . 1- Af 1 B
U(s)
The input duty to voltage output transfer function is
R . Rdcr + R . Resr - Rdcr' Resr
L. (R - R",)
R
simplify
Hvc(T"R,r:,R,Rdcp Rcsps)
Icollect,s
F, . R
----)0 - - - - - - - - - - - - - . : . : . . . . . : . : . . . . - - - - - - - - - - - - -
(
) ,
(
)
C . L . R + C . L· Resr . ~,t + L + C . R· Reier + C . R· Resr + C . Rdcr' Resr .
S
+ R + Rdcr
Ii
~T" R, r:, n, Rdcp Rcsps) :- - - - : - - - . , - - - - - - - - , - - - - - - - - - - - - , - - - - - ; - - - . , -
C.L.(1 + R"').
s2+ (.1:.R + C.Rd _C.R + C· RduR .R~,) .s+ (1 + RJUj'
R
R
cr
eST
santlty check
Hvc(L,R,C,E,Rdcr,Re~r's) substitute,Re,r
=0
E·R
---+ - - - - - - - - - - - - - R + Rocr + L . s + C . R . Rdcr . S - C . L . R . ,,,2
124
same result as Ideal buck
The input duty to inductor current output transfer function is
,. (R: RoJ]'. [~:
R . Rdcr + R . Resr + Rdcr . Resr
L· (R + Resr)
R
HiL(L.R.C.E . Rd" . R,~,.s)
simplify
I 11
C. (R + R,~,) ]
E + s . (C. E· R + C . E· R,~,)
--> - - - - - - - - - - - - - - - - ' - - - - - - - - - = - ' - - - - - - - - - - - - -
co ect,s
2
(C . L . R + C . L . Resr) . S + (L + C . R . Rdcr + C . R . Resr + C . Rdcr . Resr) . S + R + Rdcr
E + s . (C. E· R + C . E· Resr)
~L.R.C.E.Rd".R,~,"s):~ - - - - - - - - - - - - - - - - ' - - - - - - - - = ' - - - - - - - - - - - 2
(C . L . R + C . L . Resr) . S + (L + C . R . Rdcr + C . R . Resr + C . Rdcr . Resr) . S + R + Rdcr
santity check
E+C·E·R·s
HiL(L.R.C.E.Rd,,"R,~,"s) substitute.R,~, = 0 --> - - - - - - - - - - - - - - - - - - 2 same result as ideal buck
R+
Rdcr
+ L . s + C . R· R dcr ·
+ C . L . R· s
S
time (ms)
BuckMdlCOmpare2. mdl
PLECS
Circuit
Circuit
Scope2
Vs'R1
L 1' C1 ' (R1 +rC1 )s2+(L 1 +C1 ' R 1' rL 1 +C1 ' R1 ' rC1 +C1 ' rL 1' rC1 )s+(R1 +rL 1)
DJty2'¥CTF
Steady state solution (Geometric Load Line)
lim Hvc(L,R,C,E,RdcpResps) simplify -----+
s --> 0
E· R· signum(R + RdcpO).
E·R
- - - ifR+Rdcr*O
R + Rdcr
We can quickly calculate the equalibrium by
X'
= A . xe + B
=0
Xo =
-(B + A- 1)
xe(E,L,R,C,Resr,Rdcr,d) :=
125
00
if R + Rdcr = 0
~I
[ j
R+
x~E,L,R, C ,R,""Rdcr,d) simplify
--->
iL = - - R + R dcr
Rdcr
v c = VCR.r
and the inductor current has to be
Vc
E · R ·d
R+
If the desired output voltage is
R dcr
then
E·R
E·d
simplify
RI
:~
2
126
V CRef
---> - -
R
A.2
Constant-Current Buck Converter
NON-IDEAL AVERAGED A BUCK CONVERTER WITH CONSTANT RESISTANCE LOAD
Full Model
10
Active switch closed
10
substitute ,13
~=~-~
diL
..
IslIllphfy
]
=10
~~=~-~
]
]
cit =L· YL =L{E]
]
- (ve + 12 ·R esr + 1].Rdcr )]
]
diL
]
= -{EI dt
L]
[ve + (iL -
IO)"Resr+ iL"R dcr]
=L{E] ]
[ve + (iL - 10)·Resr + iL·R dcr]
diL
expand,iL,vC ----+ dt
diL
E] + 10·Resr
]
= -{EI + IO·R esr - (Rdcr + Resr)"iL - vC] =
+
eli
L]
L]
dVe]
]]
-dt =-e]. i e =-.1
2 =-·(iL e]
e]
r:~
l
t
[-±.(Rdcr + Resr)
dvej -
]
cit
-i.
0
ve
E]
=-L] - -L]
10·Resr
Rdcr·i L
Res(iL
+ --- - --- - --L]
L]
L]
]
--.(R
dcr + Resr)"iL L
]
-·vC
L
]
13)
=-·(iL
e]
(IL
1
(I
10)
E] +
·lve) +
_
_
- x - A].x + B]
-10
l
e
~~.Resr 1
)
1
~
Active switch open
I]
L,
RL1 12
10
I]
=iL
12
diL
=iL -
]
13 13
=10
]
cit =L· YL =L{O ]
diL
]
cit =L{O ]
diL
]
]
(ve + 12 ·R esr + 1].Rdcr )]
=L{O ]
[ve + (iL - 10)·Resr + iL·Rdcr]
[ve + (iL - 10)·Resr + iL·R dcr] expand,iL,ve ~
diL
10·Resr
ve
Rdcr·i L
]
]
cit =-L-- - L - - L - - ]
]
10·Resr
]
]
-.~(IO·R ) - (Rd + R ).i L - ve] = - - + --.(R d + R ).i L - -·ve
Ll L
esr
cr
esr
Ll
L
cr
esr
L
-dt =
127
Res(iL
-L-]
rdt 1_-
l
dvc
cit
j
__
1
-10
Resr
diLI
[-I'L,(Rdcr + Resr) - 'L
I] (iL l
'
) +
2.
0
Vc
C
I~
(Io'
l
STATE SPACE AVERAGE FOR CONSTANT
- x - AI, x+ B I
~
RESISTA~Ir.I:: I
nAn
o
I :~E I ,L I 'C I ,Resr,IO):=
["Tl
LI
-10
o
The LTI buck model is
dx
-dtavg
- =Aavg 'xavg + B avg ,u
where
u
=d
f2(EI ,L I 'C I ,RespRdcr,IO,d ,xo,X I) := Aavg(LI ' C I
'Resr'Rdcr'lo'd){:~ J+ Bavg(EI ,L I ' CI ,Resr, IO ,d)
IO,Resr + EI ,d - Rdcr' xO - Res r'xO
128
xI
Solve equalibrium
substitute,xl = IO"Resr + Erd - Rdcr"XO - Resr" xO
I
10 -
10 - Xo
- - - - = 0 solve, xo
C1
----,io
C1
10
PWLSPACCLBuck.mdl
IfUll """""~
Puls e
Generat or
~
()
>
:I/~~
.
o
10
20
30
Xo
-->~--
simplifY
40
50
time (m s)
129
~
Constant
r-r-n
~
r-r-n
~
=0
A.3
Boost Converter
NON IDEAL STATE SPACE AVERAGE
when q1 = 0
ic=C·v'c
, _ 1
.
VC-C"lC
ic
Vc
=iL - R
FI
when q1 = 1
., _ 1
lL-L'"VL
ic = C·
ViC
, _ 1 .
Vc ·le
C
.i'L
Vc
ic=-R
V'c
=
-~. (:)
FI
130
fL 0 ) . (iL
J Vs
=( -i
Vc + L
v'c =
(0 __
1 ). (iLJ
R· C
Vc
The stage space average matrices are
,[-~ d~ll
M,", (A2(L,R,C,'L),d) 'impluy ~
d- 1
substitute u = d -1
1
--- --C
M,"i B 2(E,L),d) 'impluy
-+
c·
R
[~J
BILINEAR FORM
Consider the bilinear representation of a network with
synchronous switches [IOJ, [11 J:
d
drx=f(x)+ug(x)+h'=Ax+u(Bx+y)+~
(1)
where A and B are square constant matrices, and y and ~
are vectors representing constant power sources. We usulilly represent the vector fields f(x), g(x), and h as
Bilinear sliding motion from Ramiraz
(E
t2(R,L,C,]i,fT.,Ye,1T.'U) simplify ---+
I
l
L
vc+R.iL· u
131
SIMULATED RESULTS FOR NON-IDEAL BOOST
BoostMdICompare_OpenLoop.zip
iL (y ell ow - P\AL, purp le SPA)
100
50 1 ' \
0
0
0.05
O~(yellc!:5P"A'L PJOrple SPA~25
03
0.3 5
40 0 ~-~--~-'--~--~-~_ _~_~
~O ~p -~ ----~ ---~ ----~ ----:----~ --0
S L1J syste m1
%intialize variables
%see BoostDesign.xmcd for values
% power inductor
C l ~ 66 0 e -6;
filter capacitor
% source voltage
E ~ 125 ;
;
0. 05
01
0.15
0
0.05
01
0.15
02
0. 25
03
0. 35
,
02
0. 25
03
J
05
11=0.0 10 ;
Vd ~ 25 0
0
0
Time
desired output
% load
switching frequency
Rl ~ 1 0;
f s w ~30000;
rLl ~O.O;
D ~O. 5 0 1 ;
Vb ~ 25 0;
L
SOlv e 'i L----+ __=E-,--_
0=
Isimplify
L
Vc
R . u 2 + fL
= R· u· iL
E
substitute,i L = - - - - E· R· u _
R· u 2 + fL----+ Vc = ____
2
R u + fL
simplify
o
CI
:~
0.129
The equalibrium in
terms of u is
Ll
:~
0.126 RI
:~
I
EI
:~
2.5
rLl:~
0.044
ul
x,,(RI,Ll , C I ,E I ,rLl ,ul ) l1oal,3 -->
132
:~
0.2
29.8)
( 5.95
N I:~
10000
0. 35
to solve in terms of vC (i.e. geometric form )
E2 0R - 4 0fL 0v e
E+
ve
=
E oR ou
J
2
R
2
2
El 0Rl - 4 0fLl 0ve
f( v c) :=
El +
_---'-_ _ _R
_ l_ __
2 ve
2 ve
0
solve,u --+
0
2
R u + fL
0
f(10)
E2 0R - 4 0fL 0v e
E+
substitute , u
= 0.1 25 + 0.1 68i
2
J
R
= ----'!.------.::..:....---
2 ve
2
0
2 ve
--+ iL = -/-r==:=====::::::::~
E20R - 4orLove2 ]
R o E+
0
simplify
[ J
II
2· Vc
2
l
vCI :~ 5
The equalibrium in
terms of vC is
-->
(130)
5.0
20
x,~ Rl, Ll, Cl, El ,ILl, vc)
Example non-ideal load line
R
o
10
o ~~~-~--~
o
4
133
A.4
Voltage Source Inverter
BOOSTING VOLTAGE SOURCE INVERTER WITH
CIRCUIT DERIVATION
R,
EI
ic=C·v'c
I
_
VC-
1
.
C
"l C
ic = i L
Vc
--
R
EI
.i'L =
Vs
Vc + L
(-L"fL 0 ) . (iL)
v'c =
(0 __
1 ) .(i
R· C
., _ 1
lL-L'"VL
ic = C·
ViC
, _ 1 .
Vc ·le
C
V'c
=
-~. (:)
134
L
Vc
)
EI
ic=C·v'c
, _ 1
VC-
C
.
"l C
EI
diL
ic
= c· dve
dve
1
.
= - . Ie
C
ic
1
=-.
(vs L
Vc
= -R
135
iL"rd
SUMMARY
positive current into plus side of capacitor
charging inductor with lows ide switches
l
(lL) l
.
dx
dt
= A.
x + B
=
(lL)
Vc
c:::
=
positive current into minus side of capacitor
L
1
C
. C:::
dx
dt
= A.
x + B
=
Vc
=
charging inductor with highs ide switches
L
o
136
STATE SPACE AVERAGE WITH DUTY CONTROL
Suppose we are given two systems
X'
=Ao· x + Bo
and
x'
= Aj . x + B j
Than the average matrix is
and the system average is
if we let u = D - 1 and u is between 1 and -1 then
137
that alternate with duty cycle D
simulation file: VSICompare_RevF.zip
run lritvars to load syste m ard control parameters
IVoltage Source Inverter Model Comparisonl
run 5im r:l ot (Sco peData ) to piC(
Vv
'NO
"
Gain
Iv0-->
Averaged Sys tem
v.;
"
'"
,------,.
"
~ vC
Circuil 1
~
.1
"I"
Co rt rol
Contro ll er 2
~
00
vS
Vs
q
f
....
,,,
,,,
q"
q
qn
IV5':
Vv
PLECS
Circuil
,c
I
Sign al
General lY
138
Circuil2
iL~
,c
D
~
EQUALIBRIUM ANALYSIS
solve iL in equalibrium
0=(1
0) [AAV.(LoRoCorLou)
0
0
C~) + BAV.(vsoL)] solveoiL
--> Vs -r: Vc
0
solve vC in equalibrium
R . vC . u
2
- R . v S . U + fL· v C
CoR rL
0
R.vCou2_R.vSOU+fL"VC
R·u·ys
0= - - - - - - - - - - - solve,vc ----+ - - - C· R· fL
R. u 2 + fL
iL
=
Vs-U·Vc
substitute,vc
fL
=
R·u·vs
2
R .u +
fL
Vc
R .u
+
= ---------R D2 - 2 RoD + R + rL
0
= --'-2
Rovso(D-l)
----+ Vc
2
R u + rL
Vs
----+ iL
Rouovs
=
iL
Vs
=
2
----+ iL
R u + rL
fL
0
V des
=
R·
139
Vs
=-----'----R D2 - 2 RoD + R + rL
R·u·vs
2
U
substitute ,fL
+
fL
0
0
0
= 0 ----+
0
Vs
V des
= -;
solve, U
Vs
----+ V des