039 1 Improved Dynamic Performance of Multiloop Operation of Paralleled DC/DC Converters Using Fuzzy-Logic Control Idris Gadoura, Student Member, IEEE, Teuvo Suntio, Member, IEEE, Kai Zenger Abstract—In this paper we utilizes the design of robust PI/PID control for paralleled DC/DC converters that has been reported in our previous work in order to design PID-like FLC for voltage-loop and PI-like FLC for current-loop. The variations of power components have been taken into account as an uncertainty when designing the robust PI/PID control. The PIDlike FLC and PI-like FLC are designed to guarantee robust output voltage and to equalize the output currents, respectively. In the simulation the fuzzy-logic control has an advantage of less control effort over the conventional PI/PID control. Index Terms—DC/DC converter, uncertain system, PID control, fuzzy-logic. T and for parallel-connected DC/DC converters as in [5,7]. This paper is aim to design PI- and PID-like fuzzy-logic controllers using the parameters of robust PI and PID controllers that are presented in [6]. The design of fuzzy-logic controller by utilizing the well-tuned conventional controller has firstly been proposed in [9] and successfully applied to DC/DC converters in [3]. However, there are more methods of designing fuzzy-logic controller for DC/DC converters presented in [8,12,19,21,24] gives good results. The fuzzylogic control design procedure presented is verified by simulation of two-buck converters connected in parallel. he main control issues in parallel-connected converters are to equalize the output currents among converters and to ensure the robust output voltage at the load. Paralleling power converters adds complexity to the system and typically entails accepting some performance and cost compromises [20]. In practice, the control is needed to ensure proper current sharing and many effective control schemes have been proposed in previous studies [2,10,13-17]. The main purpose of this paper is to design a fuzzy control system of paralleled DC/DC converters, as shown in Fig. 1, based on our previous work, which is reported in [6]. In [6] we assumed that the overall system is composed of twoMIMO subsystems, for voltage-loop and current-loop. Also the voltage-loop consists of n-SISO subsystems, where n is the number of converters in parallel that can be designed separately. The actual plant models consist of nominal plant models and uncertainty models. Parametric uncertainty is modeled where the structure of the model is known, but some of the parameters are uncertain [18]. The robust PID and PI controllers are designed to achieve robust stability and robust performance for voltage-loop and current-loop, respectively. Also the robust µ-based control design has successfully been designed for single DC/DC converter as presented in [1,4,22] L1 Switch I. INTRODUCTION iL1 + PWM rL2 v_in2 iC2 PWM + + v2 r2 rp2 C2 rC2 v2 _ kv2 + vref iL2 + iref k1 L2 Switch i _out1 + + r1 rp1 rC1 v1 _ kv1 v1 iC1 C1 v_in1 i_out2 iref k2 + vref rpn 2 rp (1+ n 2 ) + vout R ig _ Ln Switch rLn iLn + v_inn iCn PWM I. Gadoura is with Control Engineering Laboratory, Helsinki University of Technology, P.O.Box 5400, 02015 HUT, Finland. (tel: +358 9 4515221, fax: +358 9 4515208, email: igadoura@cc.hut.fi). T. Suntio is with Electronics Laboratory/Power Electronics,University of Oulu, P.O. Box 4500, FIN-90401 Oulu, Finland. (tel: +358 8 5532889, fax: +358 8 5532700, email: teuvo.suntio@ees2.oulu.fi). K. Zenger is with Control Engineering Laboratory, Helsinki University of Technology, P.O.Box 5400, 02015 HUT, Finland. (tel: +358 9 4515204, fax: +358 9 4515208, email: kai.zenger@hut.fi). rL1 _ kvn + vref kn rpn rn Cn rCn vn + vn i_outn + iref Fig. 1. Paralleled DC/DC converters feeding a resistive load with cascaded fuzzy controllers for voltage- and current-loops. 039 d (s) 2 Gdv ( s ) Wd ( s ) r ( s) G pv ( s ) u∆ v ( s ) ∆ pv ( s ) yuv ( s ) Wr ( s ) r ( s) nv ( s ) Wr ( s ) Wnv ( s) + A/D Kv (s) D/A _ + + uv ( s ) + u ( s) G pv ( s) + _ + W pv ( s ) zv ( s ) Wpi ( s) zi ( s ) a K i (s) D/A Gdi ( s ) ui ( s ) G pi ( s ) u ∆i ( s ) Q Wni ( s) + + yv ( s ) A/D ni ( s ) + + u( s) + + ∆ pi ( s ) G pi ( s ) yui ( s ) + + + + yi ( s ) Fig. 2 - The control configuration of paralleled DC/DC converters including all uncertainties. The control of voltage-loop is considered when it is isolated from the current-loop by breaking the connection at point a. Note that Q block determines the active control scheme either democratic or master-slave scheme. II. CONTROL DESIGN From Fig. 1, the control system of “j” converter is a voltage controller, kvj, ensuring robust output voltage cascaded with current controller, kj, ensuring current sharing. The control law can be written as u j = kv j k j ei j + kv j ev j (1) = ki j ei j + kv j ev j where j = 1, 2, 3, ………., n. From the practical viewpoint, the controllers’ structure of either voltage-loop or current-loop can be presented as a diagonal transfer matrix as ( = diag ( k K v = diag kv1 , kv2 ," , kvn Ki i1 , ki2 ," , kin ) ) (2) (3) where Kv and Ki are used in control design procedure as shown in Fig. 2. Then, the control vector can be written in the general form as follows. u = K i ei + K v ev (4) where ei is a vector of current error and ev is a vector of voltage error. In order to model the uncertainty, we consider the worstcase model represented in state-space form as follows. x = A p x + B p u yv = C pv x and yi = C pi x (5) where A p = Ap + ∆ A , B p = B p + ∆ B , C pv = C pv + ∆ Cv , and C pi = C pi + ∆Ci . Also Ap, Bp, Cpv, and Cpi model the nominal system, however ∆A, ∆B, ∆Cv, and ∆Ci model the uncertainty. The uncertain perturbations are chosen into a block-diagonal matrix as follows. ( ) = diag(∆ A , ∆ B , ∆ C ) ∆ pv = diag ∆ A , ∆ B , ∆ Cv (6) ∆ pi (7) i In Fig. 2, y is the vector of output voltages and output currents, Gp is the plant model transfer matrix, u is the control commands vector, Gd is the disturbance model transfer matrix, and d is the disturbances vector. The subscript “v” stands for voltage-loop subsystem and “i” for current-loop subsystem. The high-pass filter matrices, Wnv(s) and Wni(s), are designed 039 3 to attenuate the measurement noise. The low-pass filter matrices, Wpv(s) and Wpi(s), are designed to specify the desired closed-loop performance for the voltage-loop and the currentloop, respectively. Also Wd(s) and Wr(s) are scaling matrices. III. FUZZY-LOGIC CONTROL Robust PID and PI controllers for voltage-loop and currentloop, respectively, are designed, as presented in [6], to achieve all robustness issues in the presence of uncertainty, i.e., nominal performance, robust stability, and robust performance for either a voltage-loop or the whole system. Next shows how to design FLC using the parameters of well-tuned controllers. A. PI-like FLC The FLC describes with the aid of fuzzy rules the relationship between the control co(k) on one hand, and the current error ei(k) and its change cei(k) on the other hand. The internal mechanism of the FLC translates this relationship into a mapping: co (k ) = f ( ei (k ), cei (k ) ) vo (k ) = f ( ev (k ), cev (k ) ) The integral part I(k)is added to the output because it is hard to write fuzzy rules for it [23]. The control law can be written as u (k ) = f ( ev (k ), cev (k ) ) + I (k ) The similarity between the conventional PID controller and PID-like FLC can obviously be seen: u (k ) = K P ev (k ) + K D cev (k ) + K I cui (k ) = K P ei (k ) + K I cei (k ) (9) where KP and KI are the parameters of the PI-controller and cui(k) is the change in the control. However the relationship between ei(k) and cei(k) on one hand, and ui(k) on the other hand is linear in conventional PI-controller and nonlinear in PI-like FLC. The reasoning mechanisms of the PI-like FLC and PD-like FLC work basically in the same manner. The only difference is the integrator located on the output in the case of PI-like FLC. PD-like FLC ei FLC - 2 1 - z-1 b2 cei ∑ e (k ) (12) v where KP, KD and KI are the parameters of the PID-controller. êv a1 1 - z-1 z-1 / (1 - z-1) a2 (11) b1 ev FLC - 1 cev ConstantVoltage Controller vo + u d1 + (8) The similarity between the classic PI controller and PI-like FLC can obviously be seen: êi (10) Current Controller co d2 cui z-1 / (1 - z-1) ui Fig. 3 - The structure of fuzzy current controller. The PI-like FL controller, which is k in equation (1), has been selected to equalize the output current of each converter to the current reference. B. PID-like FLC The FLC is the same as the PD-like FLC describes with the aid of fuzzy rules the relationship between the control vo(k) on one hand, and the incremental voltage error ev(k) and its change cei(k) on the other hand. The internal mechanism of the FLC translates this relationship into a mapping: c1 Fig. 4 - The structure of PID-like FLC. The PID-like FL controller has been chosen to regulate the voltage-loop in order to achieve the robust output voltage in spite of line and load disturbances. C. Tuning The fuzzy control design procedure of PID-like FLC, which is proposed in [9] can be simplified as follows. Use the parameters of robust PI and PID controllers that are presented in [6]. Replace the summation in robust PI and PID controllers, as shown in Fig. 3 and Fig. 4, respectively, by fuzzy controller, which has the following structure: o It has two inputs that are an error and change in error, and one output. o Five memberships are chosen for input and output variables, PB, PS, Z, NS, and NB, in order to smooth the control action. o Create the fuzzy rules in order to improve the converter output performance and based on the following criteria: When the output of the converter is far from the reference, the change of control signal must be large to bring the output to the reference quickly. When the output of the converter is moving closer the reference, the change of control signal is small. When the output of the converter is near the reference and is moving closer to it rapidly, the control signal must be kept constant to prevent overshoot. When the reference is reached and the 039 4 b1d1 = D = K PTd , so that b1 = a1Td . K a c1d1 = I = P , so that c1 = 1 . Ti Ti The construction of the fuzzy rules is the most difficult aspect of FLC design [11]. There are no systematic tools to write the fuzzy rules, however, it is based on intuitive knowledge and experience as shown in Table I. design than conventional ones presented in [6]. Also the dynamic performance and control efforts presented in this paper have good advantages over the results presented in [21]. 54.1 54.02 54 54.01 53.9 54 53.8 53.99 53.7 53.98 53.6 0.02 40 > The line disturbance in first channel by +20V and in second channel by -20V both at 0.02s. > The load disturbance +5A at 0.035s. 20 0 0.005 0.01 0.015 0.02 0.025 0.03 Time (sec) 5.5 9 5 8 LP LP LP LP Z SN SP LP SP SP Z SN Z SP Z Z Z SN SN SP Z SN SN LN LN SP Z LN LN LN 0.035 6 4 > The line disturbance in first channel by +20V and in second channel by -20V both at 0.02s. > The load disturbance +5A at 0.035s. 2 0 0 0.005 0.01 0.015 0.02 0.025 0.03 Time (sec) 0.035 0.04 0.045 0.05 Fig. 6 - The steady state and transient behavior of the output currents in the presence of line & load disturbances with uncertainty. 0.5 0.35 0.4 0.3 0.3 0.25 0.02 0.0205 0.021 0.2 0.03490.035 0.0350.03510.0351 20 Control commands In order to verify the control design procedure, the configuration of two-identical parallel-connected buck converters, as shown in Fig. 1, is considered with the following parameters. The input voltage Vin = 140V, output voltage Vo = 54V, maximum output power Po = 500W, switching frequency fs = 100kHz, inductor L = 100µH, capacitor C = 1000µF, output resistance R = 11Ω, equivalent series resistor of capacitor rC = 50mΩ, equivalent series resistor of inductor rL = 15mΩ, cable resistance r = 20mΩ. Also the controllers’ parameters are identical for both converters and as follows. PID-controller, Kp = 22.665, Ti = 0.745ms, Td = 0.169ms, N = 4, and b = 0.573. PI-controller, Kp = 2 and Ti = 0.2ms. The simulation results of the worst-case show that the system is robustly performed and stable as shown in Fig. 5 and Fig. 6. Fig. 7 shows control efforts of the cascaded fuzzy controllers providing more optimized control 0.035 8 0.4 IV. DESIGN EXAMPLE 0.035 10 Output currents (A) LN 0.05 5 0.02 0.0205 0.021 0.0215 0.022 SN 0.045 6 ce Z 0.04 7 4.5 3.5 SP 0.035 Fig. 5 - The steady state and transient behavior of the output voltage in the presence of line & load disturbances with uncertainty. 4 LP 0.0349 0.035 0.03510.0352 60 0 TABLE I THE FUZZY RULES OF FLC e 0.0205 0.021 0.0215 80 Output voltages (V) output is still changing, the change of control signal is very small preventing the output from moving away. When the reference is reached and the output is steady, the control signal is constant. When the output is above the reference, the sign of the change of control signal must be negative and vice versa. o Normalize all values of input and output variables by using the gains, a1, b1, c1, and d1, i.e. the universe of discourse is transferred into the normalized closed interval [-1,+1]. K a1d1 = P = K P , so that d1 = P . a1 15 10 5 0 -5 0 0.005 0.01 0.015 0.02 0.025 0.03 Time (sec) 0.035 0.04 0.045 0.05 Fig. 7 - The steady state and transient behavior of the control commands in the presence of line & load disturbances with uncertainty. 039 5 V. CONCLUSION The paper has presented a procedure to design fuzzy controllers for voltage-loop and current-loop of paralleled DC/DC converters. The PID-like FL controllers are designed to regulate the voltage-loop and the PI-like FL controllers are designed to regulate the current-loop of the system where the outputs are injected into their voltage-loops. The output voltages and output currents of two paralleled buck converters in the presence of uncertainty are presented in Fig. 5 and Fig. 6, respectively. Conclusively, the overall system has good rejection ability of line and load disturbances. Also the fuzzylogic controllers give the minimal needed effort to control the system as shown in Fig. 7. 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