Power MOSFET
Application Precautions
Power MOSFET in Detail
5.
Application Precautions
5.1
Precautions Concerning Drive Conditions for Shortening Switching Time
Bipolar transistors require a large base current to maintain the saturation area; however, power
MOSFETs are voltage-controlled devices and can therefore be driven by merely applying a small
power to the gate.
However, since the input capacitance Ciss of power MOSFETs is somewhat high, it is necessary to
quickly charge the input capacitor with low-impedance signal sources, especially for high-speed
switching.
Low-impedance drive is necessary to shorten the turn-ON time; however, the input capacitance Ciss
is overcharged when the voltage applied is increased and, conversely, td (off) becomes longer.
It is possible to turn OFF power MOSFETs by dropping the gate voltage to zero but, as with bipolar
transistors, it is also possible to turn a Power MOSFET OFF quickly by reducing the value of the
charge Q to zero. The charge Q which is built up by the gate-source and gate-drain voltage, will
quickly fall to zero after applying a reverse bias between the gate and source voltage (ig = dQ/dt).
Figure 5.1 shows the relationship
Test circuit
VDD (= 200 V)
between the magnitude of the reverse
bias and the switching time.
40 Ω
IG waveform
10 μs
In the case of N-channel MOSFETs, it
ID = 5 A
Output
5V
is possible to decrease the switching
IG
−VG
0
times tf and toff by using a negative
power supply, that is, by configuring a
low-impedance circuit.
To operate power MOSFETs at high
1000
speed, it is necessary to add a speed-up
600
circuit to increase the speed at which the
400
Switching time (ns)
equivalent input capacitance between the
gate and source is charged.
Figure 5.2 shows a speed-up circuit.
200
toff
100
60
40
tf
20
10
0
1
2
−VG
3
4
5
6
(V)
Figure 5.1 Switching Time − VG Characteristics
1
Power MOSFET in Detail
(b) Current path at rise
Speed-up circuit configured
with C1, Q2, D1, and D2.
Current flows in the direction
of the arrow when the power
MOSFET is turned ON,
instantaneously charging the
input capacitor (Cin)
Q1
Q1
When the power MOSFET is
turned OFF, the voltage
accumulated in C1 is used to turn
on Q2 and rapidly extract the
charge between the gate and
source.
D1
D1
D1
R4
NS
R1
R3
NP
T3
R3
R4
Q2
R5
D2
C1
Q2
NP
C1
C1
R4
NS
Q1
T1
R1
R2
R1
T1
R3
(c) Current path at fall
R2
(a) Speed-up circuit
D2
NS
NP
R5
D2
Figure 5.2 Gate Drive Speed-Up Circuit
5.2
The Influence of Wiring Inductance
Since the switching time for power MOSFETs is at least one order of magnitude faster than that of
bipolar transistors, they are very effective in fields where high-speed switch is required. However,
unless some countermeasure is taken in the circuitry, this high-speed switching characteristic may
give rise to a voltage surge due to stray inductance LS, which is impressed on the MOSFET. The
magnitude of this surge, Vsurge, is determined as follows:
Vsurge = −(LS + L’S)･di/dt + VDD
It is necessary that this value be given
LS
sufficient margin in relation to drain-source
breakdown voltage VDSS. To reduce this surge
VDD
voltage, it is necessary to reduce either di/dt or
the stray inductance; however, since the
reduction of di/dt does not agree with the original
purpose of high-speed switching, it is necessary
to reduce the stray inductance. This can be done
by using copper plates instead of wires, because
LS’
Figure 5.3 Circuit Stray Inductance
copper has lower inductance. Inserting the
capacitors shown in Figure 5.3 is also an effective way of reducing the magnitude of the generated
voltage surge.
2
Power MOSFET in Detail
5.3
Parasitic Oscillation
Parasitic oscillation is more prone to occur with power MOSFETs than with bipolar transistors.
This is caused by the high-frequency gain which is characteristically high with power MOSFETs.
Parasitic oscillation may occur when impedance became negative resistance for input which is caused
by strong coupling of input and output depending on gate-drain capacitance and stray capacitance.
The following methods can be used to avoid this situation.
Cs
Lower the gain by
inserting a resistor.
Insert a
ferrite bead.
Make the wires thick and short.
Figure 5.4 How to Prevent Parasitic Oscillation
(1) Make the wires thick and short. Twisted wires should be used not to connect the circuit to other
wiring.
(2) Insert a ferrite bead as close to the gate as possible.
(3) Insert a series resistor at the gate.
5.4
Source-Drain Diode Withstand Capability
Normally, for motor control circuits, power MOSFETs are used in a bridge configuration in which
the top and bottom power MOSFETs are turned ON and OFF alternately.
Now, Q1 and Q4 of the power MOSFETs shown in Figure 5.5 are turned ON and the current flows
as indicated by A. Next, when FET Q1 is turned OFF to control the motor speed, the current is fed
back through the freewheeling diode of FET Q2, as indicated by B. If FET Q1 is again turned ON after
that, a shorting current flows from FET Q1 to FET Q2 during the time (trr) until the freewheeling
diode of FET Q2 reverse recovers, and heat is generated due to the resulting power dissipation. Thus,
when a power MOSFET is used for motor control, the trr of the parasitic diode should be minimized.
Basically, it is possible to use the parasitic diode of a power MOSFET as a freewheeling diode;
however, depending on the usage conditions, it may be necessary to install an external diode, as
shown in Figure 5.6.
3
Power MOSFET in Detail
Q1
Q3
A
M
Q2
Q4
B
Figure 5.5 Motor Control Circuit Using Power MOSFET
D
SBD
FRD
Di
R
S
Figure 5.6 External Diode Connection
Figure 5.7 Parasitic Transistor of a Power
Method
MOSFET
Also, in a power MOSFET, the equivalent of a parasitic bipolar transistor exists between drain and
source (see Figure 5.7). Note that this parasitic transistor may be turned ‘ON’ by the base-emitter
resistor R’s voltage drop, during the transitional state while a power MOSFET switches from ‘ON’ to
‘OFF’, and the device may break down.
As illustrated in Figure 5.5, when using parasitic diodes between drain and source in motor control
circuits, power supply circuits and illumination circuits, it is recommended to use
high-breakdown-voltage devices (example: π-MOS V series and similar).
Parasitic Diode Breakdown Voltage (for high-performance parasitic-diode type device)
Testing Circuit
π-MOS V
(2SK2543)
No
destruction
600
*D.U.T.
VDS = 200 V/div
500
(A/μs)
di/dt
VGS
+15 V
VCS = 0
−15 V
IDR = 0
C2
C1
VDD
L1
IDR
π-MOS V (2SK2543)
400
300
ID = 10 A/div
200
Current type
destruction
100
di/dt =
500 A/μs
0
100 200 300
VDD
200 ns/div
(V)
@IDR = 8 A
*: D.U.T. = Device under test
4
Power MOSFET in Detail
5.5
Avalanche Resistance
At turn-OFF in power MOSFETs used as high-speed switching devices, high surge voltage can
occur between the drain and the source, caused by the inductance of the circuits themselves and by
drifting inductance. This voltage can exceed the maximum ratings of the MOSFET.
Previously, a surge absorption circuit was required to protect the MOSFET. Now, however, the
reduction in the number of components and the miniaturization of equipment are creating a growing
need to eliminate the absorption circuit and to absorb any surge in a power MOSFET even if it
exceeds the maximum ratings.
In response to this need, Toshiba has developed a product line of power MOSFETs usable up to the
point of self-breakdown voltage.
(1) Avalanche resistance guaranteed series
The following series guarantees avalanche resistance.
Voltage
Series
2
L -π-MOS V
π-MOS V
16 to 200 V
U-MOS I to IV
400 to 600 V
π-MOS V to VI
800 to 1000 V
π-MOS III to IV
(2) Guarantee method
The avalanche energy when Tch (max) reaches 150°C is listed in the maximum ratings column
of the individual product specifications.
When using the product, check that the actual energy impinging on the device does not exceed
its maximum rating.
Use the following procedure to check.
a)
Calculate the channel temperature Tch (max)
Calculate the total rise at avalanche in the channel temperature resulting from steady
power loss and switching loss according to the following equations, and confirm that the
maximum channel temperature value at avalanche doesn’t exceed Tch (max) = 150°C.
A. For a single pulse:
ΔTch = 0.473･V (BR) DSS･IAR･θch-a
in which
V (BR) DSS: Breakdown voltage between drain and source
IAR: Avalanche current
θch-a: Thermal resistance from channel to ambient air at avalanche
5
Power MOSFET in Detail
B. For a continuous pulse:
⎡T
⎤
T ⎞
⎛
ΔTchpeak = P0 ⎢ 1 θch-a + ⎜1 − 1 ⎟ ⋅ rth (T+ T1 ) − rth (T ) + rth (T1 ) ⎥
T
T
⎝
⎠
⎣
⎦
in which
P0: Peak value
T1: Pulse width
T: Cycle
θch-a : Thermal resistance from channel to ambient air
Note 1: For details of how to calculate Tchpeak of the continuous pulse see 6, Heat Sink
Design.
b)
Calculating avalanche energy EAS
Check that the energy at avalanche during actual operation does not exceed the maximum
rating, using the following equation:
1
E AS＝ ⋅ L ⋅ I 2
AR
2
⎛
⎞
V (BR ) DSS
⎟
⋅⎜
⎜ V (BR ) DSS − VDD ⎟
⎝
⎠
in which
EAS: Avalanche energy
IAR: Avalanche current
V (BR) DSS: Breakdown voltage between drain and source
VDD: Power supply voltage
Satisfying equations a) and b) above ensures that the device is used within its maximum
ratings.
Avalanche Voltage
Test result
@L = 200 μH,
VDD = 90 V
Test circuit
Test waveform
L
2SK2543
Peak avalanche current
2SK1352
VDS = 100 V/div
IO
VDS
25
VDD
(A)
2SK2543
ID = 2 A/div
20
Rg = 25 Ω
15
+15 V
10
5
ID max
−15 V
5 μs/div
0
6
Power MOSFET in Detail
5.6
Parallel Connections
Power MOSFETs have outstanding thermal stability and do not suffer thermal runaway; therefore,
parallel connection of them is easier than that of bipolar transistors.
Bipolar transistors are operated by the flow of base current; therefore, the current balance is
disrupted by fluctuations of the base-emitter voltage VBE, making parallel connections difficult.
Power MOSFETs, on the other hand, are voltage driven. Therefore it is only necessary to supply drive
voltage to each FET connected in parallel, making parallel connections relatively easy. However,
when controlling high power at high speeds, it is necessary to carefully consider selection of devices
and the range of possible fluctuations in their characteristics. The most important things to
remember when making parallel connections are to avoid current concentration, including
overcurrent during the transitional state, and to assure a well balanced, uniform flow of current to all
devices under all possible load conditions.
Normally, current imbalance appears during switching ON and OFF; however, this is caused by
differences in the switching times of the power MOSFETs. It is known that fluctuations in switching
times are largely dependent on the value of the gate-source threshold voltage Vth. That is, the smaller
the value of Vth the faster the switching ON; and the larger the value of Vth the slower the switching
ON. Conversely, when turning OFF, the larger the value of Vth the faster the cutoff. Because of this,
current imbalance occurs during both switching ON and OFF when the current concentrates in an
FET with a small Vth. This current imbalance can apply an excessive load to a device and result in
failure. Thus, when considering fluctuation in switching time during transition, it is preferable that
the Vth values of all power MOSFETs connected in parallel should be the same.
Q1
ID1
Due to smaller Vth of Q1 than the Vth of Q2.
Circuit with
symmetrical wiring
is preferable.
VDD
ID2
ID1
Q2
0
Input and output
should be
separated.
ID2
0
Figure 5.8 Imbalance of Current in Parallel Connection
7
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