LedSET
AN-DG-ICLSx Series
60W LED Bulb Retrofit Replacement
for E27 and GU-10 Sockets
Design Guide
Version 1.0, June 2011
Industrial & Multimarket
Edition June 2011
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
LEDSet
AN-DG-ICLSx Series
Revision History
Page or Item
Subjects (major changes since previous revision)
Version 1.0, June 2011
First edition
Trademarks of Infineon Technologies AG
AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, EconoPACK™, CoolMOS™, CoolSET™,
CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™,
EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™,
ModSTACK™, my-d™, NovalithIC™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™,
PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™,
SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™,
PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR
development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™,
FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG.
FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of
Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data
Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of
MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics
Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™
of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc.,
OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc.
RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc.
SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden
Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA.
UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™
of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of
Diodes Zetex Limited.
Last Trademarks Update 2011-02-24
Design Guide
3
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Table of Contents
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1
Intention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
Cross Reference List LED Designs versus LEDSet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4
ICLSx LEDSet Series . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
Design Description of the Single Stage for PFC and Flyback Operation . . . . . . . . . . . . . . . . . .
Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Mode (RUN Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Snubber Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Primary Current Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Factor Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Modes for Short Output and Floating Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EMI Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Blink-prevention Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Floating Load Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overall Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
10
10
10
10
10
11
11
11
11
11
11
12
6
6.1
6.2
6.3
Protection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage and Overtemperature Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Open Loop and Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auto Restart Mode (ARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
13
13
13
7
Design Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8
8.1
8.2
Mass Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Schematic for Mass Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bill of Material for Mass Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
9
Summary of Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
10
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Design Guide
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LEDSet
AN-DG-ICLSx Series
List of Figures
List of Figures
Figure 1
Figure 2
Figure 3
Schematic Bulb Replacement Primary-Controlled for Mass Production. . . . . . . . . . . . . . . . . . . . . . 7
General Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Schematic Mass Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Design Guide
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LEDSet
AN-DG-ICLSx Series
List of Tables
List of Tables
Table 1
Table 2
Table 3
Table 4
Cross Reference Selection Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
LEDSet Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Overall BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bill of Material for Mass Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Design Guide
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LEDSet
AN-DG-ICLSx Series
Intention
1
Intention
The new LEDSet high line LED driver ICLSx series was developed for crossover from high performance, including
a PFC stage, to cost down with a substantially reduced BOM for mass production – see Figure 1.
24V/350mA
R6
C7
D6
D5
C8
D4
T1
C6
L1
C3
BR1
C1
C2
7 VCC
R2
4 D
5 D
ICLS602xX
L2
1 SS
2 FB
Q1
C4
8 GND
3 CS
C5
R3
Figure 1
PWM
Control
R7
Schematic Bulb Replacement Primary-Controlled for Mass Production
This document describes the following:
1. The network and functionalities
2. The design procedure with an example for DESIGN IN
3. The design optimization for MASS PRODUCTION
The final LED board design for mass production meets all requirements of a dimmer-safe retrofit bulb design
regarding the following aspects:
•
•
•
•
•
•
High efficiency
Form factor
High power factor
THD
EMI
Low line regulation
The LEDSet system IC series combines a power control IC with integrated protection features and a high
avalanched rugged MOSFET - CoolMOS in 650 V or 800 V – within the one package.
For E27 bulb socket designs, the IC is available in PG-DIP-8-6 and PG-DIP-7 packages; for GU10 spot light socket
designs as an SMD device in a PG-DSO-16/12 package.
Design Guide
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LEDSet
AN-DG-ICLSx Series
Description
2
Description
The LED demo board design combines a conventional low cost single stage PFC and flyback converter topology.
This type of design is particularly suitable for retrofit lighting applications.
The ICLSx series LEDSet system driver IC is a current-controlled pulse width modulator together with a CoolMOS
power switch on board. Special efforts have been made to compensate temperature dependency in order to
achieve a very high accuracy of switching frequency. Short output and floating load protection are implemented
by controlling the feedback voltage. Depending on the error case, the IC works in Auto Restart (ARM) or Floating
Load Protection (FLPM) mode. For constant power, Infineon Technologies patented functionality is integrated.
Design Guide
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LEDSet
AN-DG-ICLSx Series
Cross Reference List LED Designs versus LEDSet
3
Cross Reference List LED Designs versus LEDSet
Select the right LEDSet for your dedicated bulb or spot replacement.
Table 1
Cross Reference Selection Table
4
ICLSx LEDSet Series
Overview of existing products, drain source voltage rating of the power mos CoolMOS inside, fixed operating
frequency, drain source on-resistance of the CoolMOS inside, nominal power rating and packaging. No heat sink
is required for TA = 80 °C.
Table 2
LEDSet Product Overview
Design Guide
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LEDSet
AN-DG-ICLSx Series
Design Description of the Single Stage for PFC and Flyback Operation
5
Design Description of the Single Stage for PFC and Flyback
Operation
24V/350mA
R6
C7
D6
D5
C8
D4
D1 / DR1
T1
C6
R5
L1
C3
BR1
C1
C2
7 VCC
R2
D2 /
DR2
1 SS
Q1
2 FB
Q2
D3
R3
General Schematic
5.1
Startup
5 D
ICLSxX
L2
Figure 2
4 D
R4
C4
PWM
Control
8 GND
3 CS
C5
R7
CY1
From the high line voltage, the chip supplies itself via the integrated startup cell. During this phase, the startup cell
charges the VCC cap C6 with a constant current of 1 mA up to 18.0 VCCtyp. The IC current consumption is about
300 µA during this phase. After reaching VCCONtyp = 18.0 V the startup cell is shut off to save energy and increase
efficiency during normal operation.
5.2
Soft Start
The soft start controls the input current, the duration of the soft start phase and also defines the response time in
the case of an error via the external C4 capacitor during the startup and RUN modes. When the soft start ends
(the feedback signal is lower than the soft start signal), the feedback takes over control of the primary current.
5.3
Operation Mode (RUN Mode)
During operation, the VCC pin is supplied via a separate transformer winding with associated rectification diode D4
and C6. C3 is a filter capacitor in order to prevent glitches for a proper working VCC stage. The IC consumes about
3 mA with active gates.
5.4
Snubber Network
R6, C7 and D5 dissipate the energy of the leakage inductance and clamp the drain source voltage below the
maximum drain source voltage of VDSmax = 650 V @ 110 °C.
Note: The snubber network is optional and depends on the VDSmax and transformer design.
5.5
Primary Current Limitation
The CoolMOS source current is sensed with an external shunt resistor R7. When the voltage at R7 exceeds the
internal current limit threshold, the gate driver shuts off immediately.
Design Guide
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Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Description of the Single Stage for PFC and Flyback Operation
5.6
Output Voltage
Power is coupled out on the secondary side via a fast-acting Schottky diode D6. The capacitor C8 (low ESR)
performs energy buffering.
5.7
Power Factor Correction
Output voltage is controlled for constant power and defined by the LED module used: LEDON 24 V 350 mA.
The feedback signal regulates the power factor via the network R2, R3 and Q1 in combination with R7. The
feedback pin is internally connected to the current sensing, which regulates the waveform of the input current as
a mirror of the feedback signal.
5.8
Protection Modes for Short Output and Floating Load
Together with the soft start capacitor C4, the feedback also senses errors in order to protect the design against
external impacts. In the case of a short output, the IC falls into the Auto Restart Mode (ARM). If an open load event
occurs, the IC enters the Floating Load Protection (FLP) mode.
Note: For FLP, the network DR2, R4 and Q2 has to be assembled (optional).
5.9
EMI Network
For conducted EMI issues, L1, C1 and L2 filter at a frequency up to 1 MHz, CY1 filters from 1 MHz up to 30 MHz.
5.10
Blink-prevention Network
This network – consisting of D1, D3 and R5 – prevents flickering light during the first switch on.
Note: Remove D1, D3 and R5 if not needed; replace D1 with a jumper (0 Ω).
5.11
Floating Load Protection Network
In the case of an open load, the output voltage rises dramatically and also at the same time increases the chip
supply voltage @ pin 7 VCC. When VCC exceeds 26 Vmax, the IC will be destroyed by destruction of the VCC stage.
The network R4, D2 and Q2 prevents this destruction. D2 (a 22 V Zener diode) becomes active when VCC rises
above 22 V, Q2 pulls the feedback to GND and limits the power. D2 can be replaced by a resistor DR2 (voltage
divider).
Note: An open load (LED) is equivalent to a broken bulb; the customer has to decide if spending time, space and
money on this network is justified.
Design Guide
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LEDSet
AN-DG-ICLSx Series
Design Description of the Single Stage for PFC and Flyback Operation
5.12
Overall Bill of Material
Table 3
Overall BOM
Design Guide
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Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Protection Mode
6
Protection Mode
6.1
Overvoltage and Overtemperature Protection
See LED Demoboard Description AN-EVAL-ICLS6021J-LED-Demoboard.
6.2
Open Loop and Overload Protection
See LED Demoboard Description AN-EVAL-ICLS6021J-LED-Demoboard.
6.3
Auto Restart Mode (ARM)
See LED Demoboard Description AN-EVAL-ICLS6021J-LED-Demoboard.
Design Guide
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Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
7
Design Procedures
For driving an LED module from LEDON 24 V/350 mA using ICLS6021J.
Procedure
Example
Define input parameters
Max. AC Input Voltage
VACmax
254 V
Max. AC Input Voltage
VACmax
254 V
Output Voltage
VOUT
24.0 V
Output Current
IOUT
350 mA
Auxiliary Voltage
VAux
22.0 V
Max. Output Power
POUTmax
10.5 W
Nom. Output Power
POUTnom
9.0 W
Preferred Efficiency
ηP
80 %
Max. Reflected Output Voltage
VRmax
100 V
Line Frequency
fAC
50/60 Hz
Fwd. Voltage of Output Diode
VFDIODE
0.85 V
Fwd. Voltage of Aux. Output Diode
VFaux
0.85 V
Ambient Temperature
TA
80 °C
LedSET
ICLS6021J
Switching Frequency
f
67 kHz
Breakdown Voltage
VBR_DSS
650 V
Typ. Peak Current Limitation
Vcsth
1.06 V
Typ. Feedback Resistance
RFB
14 kΩ
Typ. Trimmed Ref. Voltage
VREF
5.0 V
Min. Soft Start Resistance
RSS
30 kΩ
Min. Activation Limit of C3
VSoftSC3
3.85 V
Max. Start-up Current
IVCCstart
450 µA
Max. VCC Current Act. Gate
IVCCsup3
3.6 mA
Typ. VCC On/Off Hysteresis
VCChys
7.7 V
Typ. VCC Turn-On Threshold
VCCon
18.0 V
Typ. Drain Source On Resistance
RDSon25°C
6.45 Ω
Design Guide
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Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Typ. Eff. Output Capacitance:
Co(er)1
3.65 pF
Max. Thermal Resistance J-A:
RthJA
90
Typ. PWM-OP Gain:
AV
3.2
Max. Operating FB Voltage:
VFBmax
4.3
Power Factor:
cosφ
0.90
K/W
V
This design procedure calculates an LED module with
83 lm/W (≈ 830 lm for a 60 W bulb replacement) and
defined parameters (page 15, 16).
Max. Input Power:
PIN max =
POUT max
ηP
10.50W
= 12.35W
85%
(Eq. 1)
PIN max =
(Eq. 2)
I ACRMS =
Input Diode Bridge (BR1):
Input RMS Current:
I ACRMS =
PIN max
V AC min ⋅ cos ϕ
12.35W
= 66.30mA
207V ⋅ 0.9
Max. DC Input Voltage:
VDC max = VAC max ⋅ 2
(Eq. 3)
VDC max = 254V ⋅ 2 = 359.21V
(Eq. 4)
VDC min = 207V ⋅ 2 = 292.74V
Min. DC Input Voltage:
VDC min = VAC min ⋅ 2
Design Guide
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Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Transformer Design
Max. Duty Cycle (preliminary):
Dmax _pre =
VR max
VR max + VDC min
(Eq. 5)
Dmax _pre =
100V
= 0.255 [1]
100V + 292.74V
(Eq. 6)
I LPK _ pre =
2 ⋅ 12.35W
= 330.88mA
292.74V ⋅ 0.255
(Eq. 7)
RNP / NS _ pre =
(Eq. 8)
I LRMS _ pre = 330.88mA ⋅
(Eq. 9)
LP _ pre =
Peak Current of Primary Inductance (pre.):
I LPK _ pre =
2 ⋅ PIN max
VDC min ⋅ Dmax_ pre
Winding Ratio from Reflected Voltage
versus Output (pre.):
RNP / NS _ pre =
VR max
VOUT + VFDIODE
100V
= 4.02 [1]
24V + 0.85V
RMS Current of Primary Inductance (pre.):
I LRMS _ pre = I LPK _ pre ⋅
Dmax_ pre
3
0.255
= 96.47mA
3
Primary Inductance within the limit of Max.
Duty Cycle (pre.):
LP _ pre =
Dmax_ pre ⋅ VDC min
I LPK _ pre ⋅ f
Select Core Type and Inductance Factor (AL) from
Epcos "Ferrite Databook".
Fix Max. Flux Density:
Typically, Bmax ≈ 0.2T…0.4T for Ferrite Cross
depending on Core Material
We choose 300mT for Material N87.
Design Guide
0.255 ⋅ 292.74V
= 3.37mH
330.88mA ⋅ 67kHz
Select Core: E 16/8/5
Material = N87
AN = 22.3 mm2 lN = 34 mm
Ae = 20.1 mm2 K1 = 42.2
le = 37.6 mm
K2 = –0.701
PV = < 0.36 W/Set @ 100 °C, 100 kHz, 200 mT
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Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Air Gap:
Example
Gap
0.2
mm
(Eq. 10)
AL = 42.2 ⋅ (0.2mm )
(Eq. 11)
N P _ cal =
Inductance Factor:
AL = K1 ⋅ Gap K 2
−0.701
= 130.40nH
Number of Primary Inductance (cal.):
LP _ pre
N P _ cal =
AL
Number of Primary Turns:
3.37 mH
= 160.76Turns
130.40nH
NP
161
(Eq. 12)
N S _ cal =
NS
40
(Eq. 13)
V / Turn =
(Eq. 14)
N Aux _ cal =
NAUX
37
Turns
Number of Secondary Turns (cal.):
N S _ cal =
N P ⋅ (VOUT + VFDIODE )
VR max
Number of Secondary Turns:
161 ⋅ (24V + 0.85V )
= 40.01Turns
100V
Turns
Turn Voltage (Voltage per Turn Ratio of the
Secondary Winding):
V / Turn =
VOUT + VFDIODE
NS
24V + 0.85V
V
= 0.62
40Turns
Turns
Number of Auxiliary Turns (cal.):
N Aux _ cal =
N P ⋅ (V Aux + VFAux )
VR max
Number of Auxiliary Turns:
161 ⋅ (22V + 0.85V )
= 36.79Turns
100V
Turns
Eff. IC Auxiliary Supply Voltage (cal.):
V Aux _ cal
N
= Aux ⋅ (VOUT + VFDIODE ) − VFAux
NS
Design Guide
(Eq. 15)
VAux _ cal =
17
37
⋅ (24V + 0.85V ) − 0.85V = 22.14V
40
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Eff. Primary Inductance (cal.):
LP _ cal = N P2 ⋅ AL
(Eq. 16)
LP _ cal = (161) ⋅ 130.40nH = 3.38mH
(Eq. 17)
I LPK _ cal =
2 ⋅ 12.35W
= 330.26mA
3.38mH ⋅ 67kHz
RSense _ cal =
1.06V
= 3.21Ω
330.26mA
2
Primary Peak Current before RSense chosen
(cal.):
2 ⋅ PIN max
LP _ cal ⋅ f
I LPK _ cal =
Sense Resistor (R7):
The sense resistance can be used to define the max.
peak current individual and define the max. output
power.
Caution:
When calculating the max. peak current, short term
peaks in output power must also be taken into
consideration.
Sense Resistor (cal.):
RSense _ cal =
Vcsth
I LPK
(Eq. 18)
Choose Sense Resistor with 1% accuracy
Sense Resistor:
Design Guide
RSense
3.0
18
Ω
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Final Calculation:
Transformer Design:
Eff. Primary Peak Current:
I LPK _ SR =
Vcsth
RSense
1.06V
= 353.33mA
3.0Ω
(Eq. 19)
I LPK _ SR =
(Eq. 20)
POUT max_ SR = 12 ⋅ 67 kHz ⋅ 3.38mH ⋅ (353 .33mA ) ⋅ 85 % = 12 .02W
(Eq. 21)
VR =
(Eq. 22)
RNP / NS =
(Eq. 23)
Dmax =
(Eq. 24)
I PRMS = 353.33mA ⋅
(Eq. 25)
PSR = (106.59mA) ⋅ 3.0Ω = 34.08mW
Eff. Max. Output Power:
ax_ SR
2
= 12 ⋅ f ⋅ LP ⋅ I LPK
_ SR ⋅η P
2
Reflected Voltage:
VR =
(VOUT + VFDIODE ) ⋅ N P
NS
(24V + 0.85V ) ⋅ 161 = 100.02V
40
Winding Ratio from Reflected Voltage
versus Output:
R NP / NS =
VOUT
VR
+ V FDIODE
100.02V
= 4.02 [1]
24V + 0.85V
Max. Turn-On Duty Cycle:
Dmax =
LP ⋅ I LPK _ SR ⋅ f
VDC min PK
3.38mH ⋅ 353.33mA ⋅ 67kHz
= 0.273 [1]
292.74V
Eff. Primary RMS Current:
I PRMS = I LPK _ SR ⋅
Dmax
3
0.273
= 106.59mA
3
Power Rating of Sense Resistor:
2
PSR = I PRMS
⋅ RSense
Design Guide
2
19
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Primary Inductance within the limit of Max. Duty Cycle:
LP =
Dmax ⋅ VDC min PK
I LPK _ SR ⋅ f
(Eq. 26)
LP =
0.273 ⋅ 292.74V
= 3.38mH
353.33mA ⋅ 67kHz
Number of Primary Inductance:
LP
AL
N P _ cal =
Final Number of Primary Turns:
N P _ cal =
(Eq. 27)
NP
161 turns
(Eq. 28)
N S _ cal =
NS
40
3.38mH
= 160.99Turns
130.40nH
Number of Secondary Turns (cal.):
N S _ cal =
N P ⋅ (VOUT + VFDIODE )
VR max
Final Number of Secondary Turns:
161 ⋅ (24V + 0.85V )
= 40.01Turns
100V
turns
Turn Voltage (Voltage per Turn Ratio of the Secondary
Winding):
V / Turn =
VOUT + VFDIODE
N S _ cal
(Eq. 29)
V / Turn =
24V + 0.85V
V
= 0.62
40.01Turns
Turns
(Eq. 30)
N Aux _ cal =
161 ⋅ (22V + 0.85V )
= 36.79Turns
100V
NAUX
37
(Eq. 31)
VAux =
Number of Auxiliary Turns (cal.):
N Aux _ cal =
N P ⋅ (V Aux + VFAux )
VR max
Final Number of Auxiliary Turns:
turns
Eff. IC Auxiliary Supply Voltage:
V Aux =
N Aux
⋅ (VOUT + V FDIODE ) − V FAux
NS
Design Guide
20
37
⋅ (24V + 0.85V ) − 0.85V = 22.14V
40
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Real Eff. Primary Inductance after all values set:
LP = N P2 ⋅ AL
LP = (161) ⋅130.40nH = 3.38mH
(Eq. 32)
2
Output Rectifier Diode (D8):
The output rectifier diodes in Flyback converters are
subjected to large peak and RMS current stress. The
value depends on the load and operating mode. The
voltage requirements depend on the output voltage and
transformer winding ratio.
Max. Reverse Voltage:
⎛
N ⎞
VRDiode = VOUT + ⎜⎜VDC max PK ⋅ S ⎟⎟
NP ⎠
⎝
Design Guide
(Eq. 33)
40 ⎞
⎛
VRDiode = 24V + ⎜ 359.21V ⋅
⎟ = 113.24V
161 ⎠
⎝
21
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Clamping/Snubber Network (R6, C7, D5):
Clamping Voltage:
VClamp = VBR _ DSS −V DC max PK −VR
VClamp = 650V − 359.21V − 100.02V = 190.77V
(Eq. 34)
For calculating the clamping network, it is necessary to
know the leakage inductance. The most common
approach is to have the leakage inductance value given
as a percentage of the primary Inductance.
If it is known that the transformer construction is very
consistent, measuring the primary leakage inductance
by shorting the secondary windings will give an exact
number (assuming the availability of a good LCR
analyzer).
Leakage Inductance Ratio:
LIR
5
%
(Eq. 35)
LLK = 5% ⋅ 3.38mH = 169.0μH
Leakage Inductance:
LLK = LIR ⋅ LP
Clamping Capacitor (cal.):
CClamp _ cal ≥
2
I LPK
_ SR ⋅ LLK
(V
R
+ VClamp ) ⋅ VClamp
RClamp _ cal =
(Eq. 36)
(190.77V + 100.02V )2 − (190.77V )2
2
0.5 ⋅ 169.0 μH ⋅ (353.33mA) ⋅ 67 kHz
= 380.33 pF
Clamping Capacitor:
CClamp
390 pF
(Eq. 37)
RClamp _ cal =
Clamping Resistor (cal.):
RClamp _ cal =
(V
Clamp
+ VR ) − VR2
2
2
0.5 ⋅ LLK ⋅ I LPK
_ SR ⋅ f
(190.77V + 100.02V )2 − (190.77V )2
2
0.5 ⋅ 169.0 μH ⋅ (353.33mA) ⋅ 67 kHz
= 68.15kΩ
Clamping Resistor:
Design Guide
RClamp
68.1 kΩ
22
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Output Capacitor (C8):
Output capacitors are highly stressed in flyback
converters. Normally, capacitors are chosen on the
basis of 3 major parameters: capacitance, low ESR
and ripple current rating.
To calculate output capacitors, the max. voltage
overshoot in the case of switching off at max. load
condition must be set.
Max. Voltage Overshoot:
∆VOUT
0.5
V
20
V
After switching off the load, the control loop needs about
10…20 internal clock periods to reduce the duty cycle.
Number of Clock Periods:
nCP
Max. Output Current:
I OUT max =
POUT max
VOUT
(Eq. 38)
I OUT max =
(Eq. 39)
I Ripple =
(Eq. 40)
COUT _ cal =
COUT
220 µF
10.50W
= 437.50mA
24V
Ripple Current:
2
2
I Ripple = I SRMS
− I OUT
max
(0.73 A)2 − (437.50mA)2
= 584.37 mA
Output Capacitance (cal.):
COUT _ cal =
I OUT max ⋅ nCP
ΔVOUT ⋅ f
Output Capacitor (flow ESR Type):
Design Guide
23
437.50mA ⋅ 20
= 260.90μF
0.5V ⋅ 67kHz
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Feedback Filter Capacitor (C5):
The C Filter at the Feedback pin is designed to suppress Typical value:
any noise which may coupled in on this track.
C5: 2.2 nF
Note that the value of C5 interacts with the internal
Feeback Resistance (RFB) of the LedSET create a
filter.
Soft-Start Capacitor (C4):
The voltage at the soft-start pin together with feedback
voltage control the overvoltage, open loop and
overcurrent protection functions.
The soft-start capacitor must be calculated in such a
way that the output voltage and the feedback voltage is
within the working range (VFB ≤ 4.3 V) before the
overcurrent threshold (typ. 1.06 V) is reached.
Soft-Start Time (cal.):
t SS _ cal = (VOUT ) ⋅
2
Soft-Start Time:
Design Guide
COUT
POUTmax_SR − POUTnom
(Eq. 41)
t SS _ cal = (24V ) ⋅
tSS
42 ms
2
24
220 μF
= 41.96 ms
12.02W − 9W
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Soft-Start Capacitor (cal.):
C SS _ cal =
1
⋅ t SS ⋅
2
1
⎛ VSoftSC 3 ⎞
⎟
− RSS ⋅ ln⎜⎜1 −
VREF ⎟⎠
⎝
C SS _ cal =
(Eq. 42)
1
⋅ 42 ms ⋅
2
1
= 476.29 nF
⎛ 3.85V ⎞
− 30 kΩ ⋅ ln⎜1 −
⎟
5.0V ⎠
⎝
Use table E12, find the closest higher value
Choose Soft-Start Capacitor:
CSS
470 nF
VCC Capacitors (C3, C6):
The VCC capacitor needs to ensure the power supply of
the IC until the power can be provided by the auxiliary
winding.
In addition, it is recommended to use a 100 nF ceramic
capacitor very close between pins 7 & 8 in parallel to the
VCC capacitor. Alternatively, an HF-type electrolytic with
low ESR and ESL may be used.
VCC Capacitor (cal.):
CVCC _ cal =
I VCC sup1 ⋅ t SS 2
⋅
VCChys
3
(Eq. 43)
CVCC _ cal =
CVCC
10
2.5mA ⋅ 42ms 2
⋅ = 9.09μF
7.7V
3
Use table E12, find the closest higher value
VCC Capacitor:
Design Guide
25
µF
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Design Procedures
Procedure
Example
Losses:
Diode Bride Forward Voltage:
VF
1.0 V
(Eq. 44)
PDIN = 2 ⋅ 66.30mA ⋅ 1.0V = 132.60mW
(Eq. 45)
PDDIODE = 350mA ⋅ 0.85V = 297.50mW
Input Diode Bridge Loss:
PDIN = 2 ⋅ I ACRMS ⋅VF
Output Rectifier Diode Loss:
PDDIODE = I OUT ⋅VFDIODE
Clamping Network Loss:
2
PClamp = 12 ⋅ LLK ⋅ I LPK
_ SR ⋅ f ⋅
VClamp + VR
PClamp = 12 ⋅169.0 μH ⋅ (353.33mA) ⋅ 67 kHz ⋅
2
(Eq. 46)
VClamp
190.77V + 100.02V
190.77V
= 1.08W
Design Guide
26
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Mass Production
8
Mass Production
8.1
Schematic for Mass Production
The only case which leads to destruction of the IC is a floating load. In this case the IC destroys itself via Vcc
overvoltage exeeding Vccmax = 27 V. From this point of view, there is no need for protection against floating loads
if the LED is broken – the bulb is damaged anyway. All other protections are still activated.
24V/350mA
R6
C7
D6
D5
C8
D4
T1
C6
L1
C3
BR1
C1
C2
7 VCC
R2
4 D
5 D
ICLS602xX
L2
1 SS
2 FB
Q1
C4
8 GND
3 CS
C5
R3
Figure 3
PWM
Control
R7
Schematic Mass Production
Design Guide
27
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Mass Production
8.2
Bill of Material for Mass Production
Table 4
Bill of Material for Mass Production
Design Guide
28
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Summary of Nomenclature
9
Summary of Nomenclature
AL
Inductance Factor
PSR
Power Rating of Sense Resistor
AV
Typical PWM-OP Gain
RClamp
Clamping Resistor
Bmax
Magnetic Inductance
RDSon
Resistance of switching CoolMOS™
Transistor (On – Operation)
BW
Bobbin Width
RFB
Internal Feedback Resistor (CoolSET™)
CClamp
Capacitance of Clamping – Capacitor
RNP/NS
Winding Ratio from Reflected Voltage
versus Output
COUT
Output Capacitor
RSense
Sense Resistor
CO(er)1
Typical Effective Output Capacitor
RSS
Minimum Soft Start Resistor
CSS
Soft Start Capacitor
RthJA
Maximum Thermal Resistor J-A
CVCC
Capacitance of VCC Capacitor
Ta
Ambient Temperature
D
Duty Cycle
TSS
Soft Start Time
Dmax
Maximum Turn-On Duty Cycle
VAC min
Minimal AC Input Voltage
f
Operating Frequency of LedSET™
(f = 67 kHz)
VAC max
Maximal AC Input Voltage
fAC
Line Frequency (Germany FAC = 50Hz)
VAux
Auxiliary Voltage
IACRMS
Root Mean Square Current through the
Bridge Rectifier
V(BR)DSS
Drain Source Breakdown Voltage
ILPK
Peak Current through the Primary
Inductance
VCChys
VCC Turn-On/Off Hysteresis
ILRMS
Root Mean Square Current of Primary
Inductance
VCCon
Turn On Threshold for CoolSET™ @ Vcc
pin
IOUT
Output Current
VClamp
Maximum Voltage overshoot @ Clamping
Network
IOUT max
Maximum Output Current
Vcsth
Typical Peak Current Limitation
IRipple
DC Ripple Current
VDC max
Maximum DC Input Voltage
IVCCstart
Maximum Start-Up Current
VDC min
Minimum DC Input Voltage
IVCCsup3
Maximum Supply Current with active Gate
VDDIODE
Reverse Voltage Rectifier Diode (secondary
side)
LP
Primary Inductance
VF aux
Forward Voltage of Auxiliary Output Diode
LLK
Leakage Inductance
VFB max
Maximum Feedback Voltage (CoolSET™)
LIR
Leakage Inductance Ratio
VFDIODE
Output Diode Forward Voltage
nCP
Number of Clock Periods
VFD
Forward Diode Voltage (Optocoupler)
NP
Number of Primary Turns
VOUT
Output Voltage (secondary Side)
NS
Number of Secondary Turns
VR
Reflected Voltage (from secondary side to
primary side)
NAux
Number of Auxiliary Turns
VR max
Maximum Reflected Output Voltage
PClamp
Clamping Network Loss
VREF
Reference Voltage TL431
PDIN
Power Losses Input Diode
VSoftSC3
Minimum Activation Limit of C3
Design Guide
29
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
Summary of Nomenclature
PDDIODE
Power Losses Rectifier Diode (secondary
side)
∆VOUT
Maximum Voltage Overshoot
PIN MAX
Maximum Input Power
V/Turn
Voltage per Turn Ratio of the Secondary
Winding
POUT max
Maximum Output Power
ƞP
Preferred Efficiency
POUT nom
Nominal Output Power
cosφ
Power Factor
Design Guide
30
Version 1.0, June 2011
LEDSet
AN-DG-ICLSx Series
References
10
[1]
References
LED Demoboard Description: AN-EVAL-ICLS6021J-LED-Demoboard
Design Guide
31
Version 1.0, June 2011
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Published by Infineon Technologies AG