Resonant Tunneling Devices:
physics, technology and
applications
Alessandro Cidronali
Dept. Electronics and Telecomm. Univ. of
Florence
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
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Outline
• motivations
• RTD basics
• RTDs physics and models
• Applications
Š Exploitation of the NDR
Š Digital applications (gate logic, memory)
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Beyond the MOSFET
Moore's laws
•
• Integration has quadrupled every
three year
• Minimum dimension has been
scale by 0.7
•
•
Mesoscale :
Š An intermediate scale, on the order of ~10
nm,
Š Materials have some properties of bulk
material, but surface effects are important,
Š And more quantum phenomena become
important
Bulk :
Š Materials & structures fabricated using bulk
processes with atomic precision
Electronics :
Š Electron states are used for primary
information-processing operations
ƒ not photons (optical), or whole atoms
(mechanical)
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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What happens @ mesoscale?
• MOSFET scaling hampered by quantization of:
Š charge:
ƒ becomes important @ L ≈ 10 nm in all materials
Š energy levels:
ƒ important in semiconductors @ L ≈ 10 nm
• Can alternative device operating principles exploit these
quantization effects rather than be hampered by them?
• Some approaches:
Š Single-electron transistors
Š Quantum wells / wires / dots, quantum-dot CAs
Š Resonant tunneling diodes / transistors
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Resonant Tunneling Diodes
•
Usually based on quantum wells or wires
Š 1-2 effectively “classical” degrees of freedom
Source
Drain
Island (narrow bandgap)
Tunnel barriers (wide bandgap)
Electron tunnels
through barrier
Quantized momentum state
Electron flow
Occupied states in
conduction band
Unoccupied states
Energy
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Resonant Tunneling Transistors
•
Like RTDs, but an adjacent gate electrode helps adjust the energy
levels in the island
Gate
Source
Electron reflection
Drain
Gate controlled charge induction
Occupied states in
conduction band
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Why RTDs?
• Intrinsic bistability and high-speed switching
capability (e.g., 1 ps switch, fmax~1 THz)
• Low power consumption
• Small device footprint
• Increased functionality
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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How does an RTD work?
Peak current density: IP=ION
Peak-to-valley current ratio (PVCR)
= ION/IVALLEY
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Valley Current
Š Theory underestimates valley current
because of:
I
IP
ƒ (i) scattering by phonons and impurities
ƒ (ii) extra tunneling via impurity states in the
barriers
ƒ (iii) tunneling via X and L states/bands
IV
ƒ (iv) disorder in alloy barriers
V
ƒ (v) interface steps and roughness
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Typical RTD structures
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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III-V RTDs
•
GaAs family
Š AlGaAs/GaAs/AlGaAs
•
InP family (IP=500 kA/cm2, PVCR=52)
Š InGaAs/AlAs/InAs
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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RITDs
•
p-n type I heterojunction double quantum well RITD
PVCR = 144
H. H. Tsai, et al., IEEE EDL, Vol. 15, no. 9, Sep. 1994
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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RTDs in other materials systems:
Molecular RTDs
• Small (~1.5 nm): ultra-dense IC based on polyphenylene
• Natural nanometer-scale structure: identical in vast
quantities
methylene
James C. Ellenbogen, “A brief overview of nanoelectronic devices”
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Conventional Methods of Device Modeling
•
•
•
•
Electrons are waves. de Broglie wavelength of an electron is:
h/p,
where p is the momentum
Device dimensions are much larger than the electron wave length
Transit time through the device is much larger than the scattering
time
Diffusion equation for semiconductors
Diffusive
Ballistic
Phase-coherent
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Transport processes in RTD
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Quantum device modeling
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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coherent approach: Scroedinger eq.
Boundary conditions !
The system is open since there is a current flux.
Usual boundary conditions, like infinite barrier or periodic repetition of the system, cannot be
used.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Transfer Matrix: envelope function
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Tunneling current
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Self-consistent calculations
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Wigner function
i=
∂
ψ ( x, t ) = Hˆ ψ
∂t
ρ ( r, s, t ) = ψ ( r, t ) ⋅ ψ ( s, t )
1.Change of basis
Density matrix
2.Fourier transform
+∞
n (r ) =
∫
f W (r , k )dk
−∞
+∞
J (r ) = −q ∫ k ⋅ f W (r , k )dk
−∞
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Wigner function: results
Simulated GaAs RTD structure: equilibrium
selfconsistent conduction band, Fermi levels,
and doping. The 0.3 eV Al0.3 Ga0.7 As tunnel
barriers are 3 nm thick, and the GaAs
quantum well width is 5 nm. The center 17 nm
of the device (including 3 nm outside each
tunnel barrier) are undoped.
Self-consistent, steady-state RTD I-V curve
showing negative differential resistance,
hysteresis, and bistability.
The RTD is unstable (oscillates perpetually) in
the plateau between 0.239 V and 0.254 V, and
it is marginally stable (oscillates with slow
damping) in the remainder of the plateau.
Biegel and Plummer IEEE TED-44, 733 (1997)
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Wigner function: results
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Applications
•
•
Analog circuits ------ NDR & I\V square law
Digital Logic ------ Bistability
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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the HITFET structure for uW
Applications: QMMIC
HITD grown by MBE on top of HEMT layers
improved Esaki diode (+1 well\1barrier): higher
Jp/Jv and Fmax
better
reliability
because InP substrate, PVCR~50, Fmax~60GHz
drain
p++
source
gate
n++
Ohmic
InAlAs Schottky
InAlAs Spacer
InGaAs channel
InAlAs buffer
InP substrate
p+ - InGaAs
Top contact layer (anode)
nid - InAlAs
Barrier
nid - InGaAs
Well
n++ - InAlAs
Ohmic contact
n+ InGaAs
Bottom contact layer (catode)
nid - InAlAs
Schottky contact (gate)
n- InGaAs
Si δ-doping
nid - InAlAs
Spacer
nid - InGaAs
Channel
nid - InAlAs
Buffer
InP
Substrate
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
H
I
T
D
H
F
E
T
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The drain-HITFET reflection
coefficients
at 6.2GHz, Vdrain=500mV as seen from the:
8
CD-HITFET
7
6
dB(Γ)
bias
5
4
3
Γ
2
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
Vgs
Γ
-50
bias
phase(Γ)
CS-HITFET
-60
-70
-80
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
Vgs
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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HITFET based VCO
topologies\prototypes
Common-Drain (CD) VCO
Common-Source (CS) VCO
V_DC
Lr
V_DC
Cr
HITD
HITFET
RF-Port
HEMT
HITD
Ca
Rc
HITFET
HEMT
Lr
Cr
Rc
RF-Port
V_T
V_T
prototypes, all working at the bias voltage Vdc=0.5V :
‘A’ : CD-VCO @ 6.1GHz
‘B’ : CS-VCO @ 6.3GHz
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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6.3
-14
6.25
-17
6.2
-20
6.15
-23
6.1
-26
6.05
-29
6
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1 0.2 0.3 0.4 0.5
Power Output [dBm]
Oscillation Frequency [GHz]
HITFET based VCO prototype ‘A’
-32
Tuning Voltage [V]
output frequency
6.18 GHz
output power
-16dBm
tuning range
140 MHz
SSCR
-105dBc/Hz @ 5MHz
efficiency
3%
power supply
850µW
supply voltage
500mV
die size
450x550µm2
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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HITFET based VCO prototype ‘B’
-14
-17
6.378
-20
6.376
-23
6.374
-26
6.372
6.37
-29
-0.5 -0.4 -0.3 -0.2 -0.1
0
0.1
0.2
0.3
0.4
0.5
Power Output [dBm]
Oscillation Frequency [GHz]
6.38
to S.A.
Rc=1KΩ
Lext
V_dd=0.5mV
V_T
-32
Tuning Voltage [V]
output frequency
6.37 GHz
output power
-17dBm
tuning range
3 MHz
SSCR
-97dBc/Hz @ 230KHz
efficiency
3%
power supply
850µW
supply voltage
500mV
die size
450x550µm2
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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figure of merit (4-6.5GHz)
⎛f
FOM = ⎜⎜ 0
⎝ fn
175
[11]
170
[13]
[12]
165
[this work: prot.’B’ ]
Figure of Merit, dB
[this work: prot.’C’ ]
160
[10]
150
[5]
145
[6]
[8]
[7]
[2]
140 [1]
[4]
135
2.
Kinget, 0.35um CMOS, proc. ISSC 1998
3.
Shealy, GaN FET, IEEE MWCL 2001
4.
Yu, InP HBT, IEEE MWCL 2001
5.
Mostafa, 0.35um CMOS sub-1V, IEEE T-CS-II 2001
6.
Mostafa, 0.35um CMOS, proc. IEEE CS 2001
7.
Loo, BJT differential, 2000 Canadian Conf.
8.
Liu, 0.35um CMOS, proc. ISSC 1998
9.
Vaananen, 0.35um BiCMOS, IEEE JSSC 2001
11. Ellinger, classE GaAs VCO, IEEE T-MTT 2001
[3]
12. Deval, Synchronous CMOS VCO, IEEE RFIC Sym. 2001
125
4
Arhens, MOS w/ resonator, proc. ISSC 1996
10. Van de Ven, LC MOS, 2001 Sym. VLSI
Si - devices
III-V - devices
130
1.
[this work: prot.’A’ ]
[9]
155
⎞⎟2
1
⎟⎟
⎠ PDC ⋅ SSCR ( fn )
4.5
5
5.5
freq, GHz
6
6.5
13. Klepser, SiGe BiCMOS, IEEE RFIC Sym. 2001
HITFET-VCOs
HITFET-VCOsshow
showthe
thelowest
lowestpower
powersupply
supply
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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the QMMIC limitation
• Not all the active functions can be replaced; e.g.
difficult to replace LNA, PA, Switch
• On a one-to-one basis, the individual functions in
QMMIC could be more effective than conventional
ones (e.g. VCOs and mixers)
• In the overall budget, however, the benefit might
be marginal
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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the QMMIC as enabling technology
How to improve the effectiveness taking advantage of
the unique features of QMMIC technology?
By introducing appropriate architectures whose
application is enabled by the features of QMMIC
technology
- enabling technology approach the Quantum Bi-Directional Amplifer (QBDA) for
Tagging Applications
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Bi-directional amplifier based on HITD
The basic idea:
The reflection coefficient (Γ) of a device exhibiting a NDR is >1
Combining by a 90° directional coupler two HITDs, the output
signal is Γ times the input one
The scattering matrix
is of the form:
Γa*0.5+Γ(j*j)a*0.5=0
a/ 2
input:a
NDR
device
Γ(a / 2)
ouput:
ja / 2
Γja*0.5+Γja*0.5
Γ(ja/ 2)
S =
Sr
St
St
Sr
NDR
device
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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QBDA prototype
10
5
dB(S(1,2))
dB(S(2,1))
dB(S12), dB (S21)
A Quantum MMIC bi-directional amplifier has been
demostrated @ 5.8GHz; main characteristics:
450mV\0.5mA power supply, gain 4.7dB. More work to
control the HITD parameters is required.
0
-5
-10
-15
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
dB(S11), dB (S22)
freq, GHz
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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An application of the QBDA: the PM
reflective TAG
Terminating a port of the QBDA by a two-state load (e.g. a HITD
properly biased) a reflection equal to 2 times the QBDA gain is
obtained with a phase swing of 180°
QBDA
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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An application of the QBDA:
the PM reflective TAG
0.02
150
ref, V
10*inc
0.01
100
0.00
50
-0.01
d3, mV
0
-0.02
-50
8
10
12
14
time, nsec
430
200
420
d3, mV
150
d2, mV
d1, mV
Terminating a
port of the
QBDA by a twostate load (e.g. a
HITD properly
biased) a
reflection equal
to 2 times the
QBDA gain is
obtained with a
phase swing of
180°
200
100
50
410
400
390
380
0
370
-50
0
20
40
60
80
100
8
9
10
time, nsec
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
11
12
13
14
15
time, nsec
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QMMIC Summary
Highlights:
– TDs may be considered as an optimizing technology for
extremely low power (<500mV) RF electronics, (e.g. VCO).
– new circuit functionalities are enabled by Tunnel Devices.
– at system and circuit levels, TDs introduce new degree of
freedom, (e.g. BDA).
Next steps:
– Tight control of series resistance and parasitics.
– Device engineering at quantum mechanic level.
– Application to millimeter-wave transceiver
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Applications — Digital Logic
• Logic circuits ------ Bistability
• Integration with transistors (HEMT, HBT, CMOS) is a
requirement for a complete IC technology based on RTDs
Š Transitors: Input/output isolation, controllable gain
Š RTDs: increased functionality, enhanced circuit speed,
reduced power consumption
• It’s all about Load lines!
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Inverter
I
VDD
I
VIN=LO
VOUT=HI
VIN
VOUT
VIN=HI
VOUT=LO
•
•
VOUT
Concept: A digital inverter cell with a low on-state current for low
static power dissipation
Evaluation: The low on-state current also reduces the switching speed
because the current stays low until the RTD again reaches resonance
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Monostable-bistable transition
two stable states
RTD latch:
Iin
RTD load
RTD drive
•
•
•
Voltage biasing two RTD’s in series results in a bistable circuit.
The state of a bistable pair is given by the voltage of the DATA NODE
(OUT).
the stable equilibrium states are labeled as “0” STATE and “1” STATE.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Non-equilibrium RTD-latch switching
‘0’ state
time
‘1’ state
• To establish a new state in a latch, it must first be brought to a monostable bias and returned quickly to
the bistable level.
• To set a latch to ‘1’, an input current, Iin, must be supplied to the data node during the restoration of
the bias voltage to the bistable level; otherwise: ‘0’ the latch will be reset to the low-voltage state.
• When the total drive current is less than the drive-RTD conduction current, the capacitive current is
negative and the voltage is driven lower.
• Likewise, when the total drive current is above the drive RTD conduction current, the voltage is driven
higher.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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RTD logic gates
delay
OR
XOR (NOT: one input kept 1)
AND
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Monostable BIstable Logic Element
(MOBILE)
• To establish a new state in a latch, it must first be brought to a monostable bias and returned quickly to
the bistable level.
• To set a latch to ‘1’, the HFET is OFF: if Al>Ad, a net current charge the RTD driver capacitance,
resulting in a switch toward the high voltage
• otherwise: the HFET is ON the net current in the DATA NODE is such that the capacitive current is
negative and the voltage is driven lower.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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MOBILE Flip-Flop Circuit
Operating at up to 35 Gb/s
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Multivalued Logic
• Operating Principle of Ternary Quantizer
Ip(A)> Ip(B)> Ip(X)> Ip(Y)
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Multivalued Logic
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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RTD-CMOS
• Substantial improvement in speed, power dissipation,
and circuit complexity over CMOS only circuits.
• A hybrid integration process for RTD to be
transferred and bonded to CMOS
J. I. Bergman, et al., IEEE EDL, Vol. 20, no. 3, March 1999
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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RTD-CMOS
A 1-bit conventional CMOS
comparator: 18 devices
A 1-bit RTD/CMOS comparator:
6 devices
J. I. Bergman, et al., EDL, 1999
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Memory cell
VRTD
Write
Select
IRTD
Read
Select
RTD1
RTD2
RTD1
Read
Data
Write
Data
Storage
Node
RTD2
IRTD
VLO
VHI VRTD
Storage Node
• Concept: A static memory cell with a low
device count and low static power dissipation
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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T-SRAM
TSRAM cell test circuit.
Vref is 1.0 V and RTD bias Vref+ is
0.45 V (2-state) or 1.0 V (3-state). The
source follower at the storage node,
SN, provides the read output Vout.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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T-SRAM
Fabricated 4x4 1T-cell TSRAM
array.
Write–read cycles for high and low
inputs for the 4x4-bit TSRAM chip.
Horizontal grid scale is 50 ns/div,
vertical grid scale is 100 mV/div. The
letters “W,” “S,” and “R” stand for
write, store, and read, respectively.
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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Promising Future
A. Cidronali, Dept. Electronics and Telecommunications, University of Florence – Italy
6/29/2005
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