IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.9 SEPTEMBER 2004
2241
PAPER
Special Section on Nonlinear Theory and its Applications
Novel Design Procedure for MOSFET Class E Oscillator
Hiroyuki HASE†a) , Nonmember, Hiroo SEKIYA† , Jianming LU† , and Takashi YAHAGI† , Members
SUMMARY
This paper presents a novel design procedure for class E
oscillator. It is the characteristic of the proposed design procedure that a
free-running oscillator is considered as a forced oscillator and the feedback
waveform is tuned to the timing of the switching. By using the proposed
design procedure, it is possible to design class E oscillator that cannot be
designed by the conventional one. By carrying out two circuit experiments,
we find that the experimental results agree with the calculated ones quantitatively, and show the validity of the proposed design procedure. One
experimental measured power conversion efficiency is 90.7% under 6.8 W
output power at an operating frequency 2.02 MHz, the other is 89.7% under
2.8 W output power at an operating frequency 1.97 MHz.
key words: class E oscillator, design procedure, free-running oscillator,
numerical calculation, class E switching conditions
1.
Introduction
Class E [1]–[12] is a class of operation of the MOSFET
tuned power amplifiers. The nominal waveforms can minimize the switching power losses because of class E switching conditions and yield the high power conversion efficiency under high frequency (MHz order) operation. That is
because class E switching minimizes the power dissipated
during the MOSFET off-to-on transition, even if the switching time is an appreciable fraction of the signal period.
Class E oscillator [1], [2] is one of class E family and is
driven by the feedback voltage transformed from the output
voltage. Class E oscillator is especially applicable at high
frequency and may be as high-efficiency, high stability FM
oscillator. However, class E switching need to satisfy two
conditions, that is, zero voltage and zero slope of voltage
switching. Therefore, it is quite difficult to determine the
values of circuit elements.
The conventional design procedure for class E oscillator in [1] and [2] can be divided into two parts. One is the
design of class E amplifier [3]–[10] and the other is that of
the feedback network [11], [13]. High output Q, infinite dcfeed inductance and zero switch on resistance are assumed
in the design of [1] and [2]. In the design of the feedback
network, the design values are determined by AC analysis.
Therefore, the output voltage of the amplifier, namely the
input voltage of the feedback network, is assumed as a sinusoidal waveform. As a result, output Q must be high in the
design of [1] and [2]. However, low Q is required for high
Manuscript received December 19, 2003.
Manuscript revised March 29, 2004.
Final manuscript received May 14, 2004.
†
The authors are with the Graduate School of Science and
Technology, Chiba University, Chiba-shi, 263-8522 Japan.
a) E-mail: hase@graduate.chiba-u.jp
power output since the voltage across the resonant circuit
becomes high. Moreover, finite dc-feed inductance is effective to minimize the circuit scale. Furthermore, the power
losses at switch on resistance affect the power conversion
efficiency. So it is worth considering switch on resistance
in the design. Therefore, it is required to establish the design procedure with any conditions, i.e., any output Q, finite
dc-feed inductance and switch on resistance.
This paper presents a novel design procedure for class
E oscillator. And we clarify the design curves of class E
oscillator for any conditions. It is the characteristic of the
proposed design procedure that a free-running oscillator is
considered as a forced oscillator and the feedback waveform
is tuned to the timing of the switching. In the proposed design procedure, we consider class E oscillator as one circuit
though it is divided into class E amplifier and the feedback
network for the conventional design. The proposed design
procedure requires only circuit equations and design specifications. The other processes for computations of the design
values are carried out with aid of computer. Therefore, class
E oscillator with any conditions can be designed by the proposed design procedure. As a result, we can design class E
oscillator that cannot be designed by the conventional design
procedure. By carrying out the circuit experiment, we find
that the experimental results agree with the calculated ones
quantitatively, and show the validity of the proposed design
procedure. The proposed design procedure can be applicable to the design for many kinds of free-running oscillators
[13].
2.
Circuit Description
Figure 1(a) shows the circuit topology of class E oscillator.
Class E oscillator consists of an input direct voltage source
VD , a dc-feed inductor LC , a MOSFET as a switching device S , a capacitor CS shunting the switch, a series resonant
circuit L0 − C0 − R, two capacitors C1 and C2 , and a feedback inductor L f . Rd1 and Rd2 are resistors for supplying
the bias voltage to the MOSFET and they are large enough
to neglect the current through them [2]. Figure 1(b) shows
the equivalent circuit in this paper. In this figure, Cg and
rg are equivalent series capacitance and resistance between
gate and source of the MOSFET. rS is switch on resistance.
Moreover, rC , r0 and r f are parasitic resistance of LC , L0 and
L f , respectively. The nominal waveforms of class E oscillator are shown in Fig. 2. The switching losses are reduced
to zero by the operating requirements of zero and zero slope
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[1] and [2] can be divided into two parts. One is the design of class E amplifier [3]–[10] and the other is that of the
feedback network [11], [13]. High output Q, infinite dc-feed
inductance and zero switch on resistance are assumed in the
design of [1] and [2]. In the feedback network, the design
values are determined by using the relation of phase-shift
between input and output of the feedback network which
is given by AC analysis. Therefore, the output voltage of
the amplifier, namely the input voltage of the feedback network, is assumed as a sinusoidal waveform. As a result,
output Q must be high in the design of [1] and [2], and it is
impossible to design class E oscillator for low Q. However,
low Q is required for high power output since the voltage
across the resonant circuit becomes high. Moreover, finite
dc-feed inductance is effective to minimize the circuit scale.
The power losses at switch on resistance affect the power
conversion efficiency. So it is worth considering switch on
resistance in the design. Moreover, we think that finite dcfeed inductance and switch on resistance of amplifier affect
the phase-shift of the feedback network. Therefore, it is important to establish the design procedure of class E oscillator
with any conditions, i.e., any output Q, finite dc-feed inductance and switch on resistance.
Fig. 1
(a) Circuit topology of class E oscillator. (b) Equivalent circuit.
4.
The Proposed Design Procedure for Class E Oscillator
In this section, we present the design procedure for class E
oscillator. This design procedure is based on the design procedure for class E amplifier without using waveform equations [5], [12]. The circuit of [5] and [12] is a forced oscillation system. This paper applies the design procedure of [5]
and [12] to that of a free-running oscillator.
4.1 Assumptions and Parameters
Fig. 2
Nominal waveforms of class E oscillator.
of switch voltage (vS = 0 and dvS /dt = 0) at the turn on
transition, called class E switching conditions [1]–[12]. The
output voltage vo of the oscillator is given as vo = v1 + v2 .
The feedback voltage v f is the driving signal for the MOSFET. When the driving signal is larger than the threshold
voltage Vth of the MOSFET, the MOSFET is in on state. On
the other hand, in case of v f < Vth , the MOSFET is in off
state.
3.
The Conventional Design Procedure for Class E Oscillator
The conventional design procedure for class E oscillator in
At first, the following parameters of the circuit are defined.
√
1. ω0 = 2π f0 = 1/ L0C0 : The resonant angular frequency inthe amplifier.
2. ω f = 1/ L f Cg : The resonant angular frequency in
the feedback network.
3. A = (ω0 /ω)2 = ( f0 / f )2 : A square value of the ratio of
the resonant frequency in the amplifier to the operating
(switching) frequency.
4. B = C0 /CS : The ratio of the capacitance of a resonant
circuit capacitor to a capacitor shunting the switch S .
5. H = L0 /LC : The ratio of the inductance of a resonant
circuit inductor to a dc-feed inductor.
6. J = C0 /C1 : The ratio of the capacitance of a resonant
circuit capacitor to a feedback network capacitor.
7. K = C1 /C2 : The ratio of the capacitance between two
capacitors in the feedback network.
8. M = (ω f /ω)2 = ( f f / f )2 : A square value of the ratio of
the resonant frequency in the feedback network to the
operating (switching) frequency.
9. Q = ωL0 /R : The loaded quality factor of the resonant
circuit L0 − C0 − R.
HASE et al.: NOVEL DESIGN PROCEDURE FOR MOSFET CLASS E OSCILLATOR
2243
Table 1
An example model of IRF530 MOSFET.
threshold voltage Vth
switch on resistance rS
gate-source capacitance Cg
gate-source resistance rg
3.0 V
0.16 Ω
1.72 nF
2.18 Ω
10. Q f = ωL f /rg = 1/ωMCg rg : The loaded quality factor
of the resonant circuit L f − Cg − rg .
Next, the design given below is based on the following
assumptions.
1. The switching device S has zero switching times, infinite off resistance and on resistance rS . In this paper,
we use IRF530 MOSFET as a switching device. Table 1 shows an example model of IRF530 MOSFET. In
this table, Vth and rS are used from the FET manual. rg
and Cg are measured values by HP 16047 A.
2. The inductors have equivalent series resistance(ESR’s).
3. All passive elements including switch on resistance and
ESR’s operate as linear elements.
4. The shunt capacitance CS includes switch device capacitance.
5. The operating frequency f is assumed as f < 8.5 MHz.
From Cg and rg in Table 1, we can assume high Q f
(Q f > 5) if f < 8.5 MHz is satisfied. High Q f means
that the feedback waveform v f is sinusoidal. Hence,
the switch on duty ratio of the oscillator is thought as
0.5 under this assumption.
4.2 Circuit Equation
We consider the circuit operation in the interval 0 ≤ θ ≤
2π, where θ = ωt represents angular time. And the circuit
equations are expressed as follows:
 di
H
C



=
(VD − vS − rC iC )



dθ
QR




dvS
vS



= ABQR(iC −
− i)



dθ
R

S




dv



= AQRi



dθ




di
1



=
(vS − v − v1 − v2 − r0 i)



dθ
QR





v1 + v2
 dv1
= AJQR(i −
)
(1)



dθ
R




dv2
v1 + v2



= AJKQR(i −
− if )



dθ
R





di f
dvg



= ωMCg (v2 − vg − ωrgCg
− rf if )



dθ
dθ





VD − v f
vf
dvg
1



=
(i f +
−
)



dθ
ωCg
Rd1
Rd2





dv


 v f = vg + ωrgCg g .
dθ
In (1), RS means the resistance of the switch S . When
we define that the switch S turns on at θ = 0, RS is expressed
as
RS =
rS (0 ≤ θ ≤ π)
∞ (π ≤ θ ≤ 2π).
(2)
In the proposed design procedure, we assume a forced
oscillation like (2) by using assumption 5. And the design
values are determined by tuning the phase of the feedback
voltage v f to the timing of the switching.
When we define x(θ) = [x1 , x2 ,..., x8 ] T = [iC , vS , v, i,
v1 , v2 , i f , vg ] T ∈ R8 , (1) can be written as
dx
= f (θ, x, λ)
dθ
(3)
where λ = [A, B, H, Q, J, K, M, Cg , ω, VD , rS , rg , rC , r0 , r f ,
R, Rd1 , Rd2 ] T ∈ R18 .
4.3 Conditions for the Design
We assume that (1) has a solution x(θ) = ϕ(θ, x0 , λ) = [ϕ1 ,
ϕ2 ,..., ϕ8 ]T defined on −∞ < θ < ∞ with every initial condition x0 and every λ : x(0) = ϕ(0, x0 , λ). If the oscillator is
in the steady state, the equation:
ϕ(θ + 2π, x0 , λ) = ϕ(θ, x0 , λ)
∀θ
(4)
is given. Therefore,
ϕ(2π, x0 , λ) − ϕ(0, x0 , λ) = 0
∈ R8
(5)
is given as the boundary conditions between θ = 0 and θ =
2π.
In order to design class E oscillator, we have to consider the conditions for class E switching and the phase
matching of driving signal of the MOSFET. The class E
switching conditions mean that both the voltage and the
slope of the voltage of the switch are zero when switch S
turns on. Therefore, the equations
ϕ2 (2π, x0 , λ) = 0
dϕ2 (θ, x0 , λ) dθ
θ=2π
(6)
= ABQR(ϕ1 (2π, x0 , λ) − ϕ4 (2π, x0 , λ)) = 0
(7)
are given. The phase matching of driving signal of the MOSFET means that the feedback voltage v f is equal to Vth when
switch S turns on. Therefore, the equation
ϕ8 (0, x0 , λ) + ωrgCg
ϕ8 (0, x0 , λ)
= Vth
dθ
(8)
is given.
From above considerations, we recognize that the design of class E oscillator boils down to the derivation of the
solution of the algebraic Eqs. (5)–(8). In these equations,
we have 11 algebraic equations and 8 unknown initial values, namely x0 ∈ R8 . Therefore, 3 parameters can be set as
the design parameters from λ ∈ R18 . In this paper, we set
A, B, and M as unknown parameters. And the other parameters are given as the design specifications. As a result, we
can get the algebraic equations in shape as follows:
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







ϕ(2π, x0 , A, B, M) − ϕ(0, x0 , A, B, M)


ϕ2 (2π, x0 , A, B, M)


ϕ1 (2π, x0 , A, B, M) − ϕ4 (2π, x0 , A, B, M)

ϕ8 (0, x0 , A, B, M)

ϕ8 (0, x0 , A, B, M) + ωrgCg
− Vth 
dθ
= 0.
(9)
Applying Runge-Kutta method and Newton’s method
to (9), the unknown parameters can be found, and the design
values, that is, A, B and M are determined. The procedure
for calculations of Newton’s method is the same as in [5]
and [12].
5.
The Benefits of the Proposed Design Procedure
It seems to be natural to use a circuit simulator, e.g., SPICE
for the design of class E oscillator. In order to design class
E oscillator, we have to consider three conditions, namely,
class E switching conditions and the condition of phase
matching of driving signal of the MOSFET. However, three
parameters, that is, A, B and M cannot be determined independently since all of three parameters affect all of three
conditions. Therefore, it takes a long time to tune the parameters experientially based on the results of using SPICE
since many trial and error efforts are needed, and it is difficult to derive the accurate solutions. Moreover, it is necessary to derive the solutions in steady state when designers
check the validity of tuned parameters. Therefore, many
calculations are needed since the designers tune parameters
many times.
Because of above reason, the design values of class E
oscillator are derived from waveform equations in the conventional design procedure [1], [2]. However, these design
procedures allow only a condition under high output Q, infinite dc-feed inductance and zero switch on resistance. If
designers require other design specifications, they need to
derive waveform equations according to the required conditions. It is very difficult to express the solutions in steady
state explicitly. Therefore, it also takes a long time to derive
waveform equations.
In the proposed design procedure, the solutions in
steady state and nominal parameters are derived simultaneously by using Newton’s method. As shown in [5], the
variational equations must be needed for the calculation of
Jacobean matrix in Newton’s method. The circuit Eq. (1) are
required in order to derive the variational equations. These
are also reasons why SPICE simulator cannot be used in
the proposed design procedure. However, if only the circuit equations are formulated, the accurate design values of
class E oscillator can be derived with few efforts under any
conditions. This is because the all procedures except the
derivation of the circuit equations can be carried out with
aid of computer. They are benefits of the proposed design
procedure compared with the other design procedure.
6.
Disscussion of the Results
In this section, we show the design curves of class E oscil-
lator. At first, the design specifications are given as follows:
f = 2.0 MHz, VD = 12 V, R = 10 Ω, J = 1.0, K = 0.1, Rd1
= 750 kΩ, Rd2 = 250 kΩ and rC = r0 = r f = 0 Ω. Moreover,
rS , Cg and rg are the same as in Table 1.
Figure 3 shows the design curves of A, B, M and the
power conversion efficiency η of class E oscillator as a function of Q. In this figure, the power conversion efficiency η
is given by
η=
Vo2 /R
.
VD IC
(10)
Here, Vo is the root mean square output voltage vo that is
given by
2π
1
Vo =
{vo (θ)}2 dθ,
(11)
2π 0
and IC is the root mean square input current iC that is given
by
2π
1
IC =
iC (θ)dθ.
(12)
2π 0
For the calculations of the integrations of v2o and iC in (11)
and (12), we apply trapezoidal method in this paper. The design curves of A and B vary rapidly at about Q = 7.5. That
is because Q = 7.5 is the boundary between under-damped
case and over-damped case. For Q > 7.5, the waveforms for
this region are almost same since the current i through the
resonant circuit is sinusoidal regardless of Q. Therefore, the
variations of the design parameters are small for Q > 7.5.
On the other hand, for Q < 7.5, the variations of the design
Fig. 3 The design parameters as a function of Q for H = 0.001, J = 1.0
and K = 0.1. (a) The design curve of A. (b) The design curve of B. (c) The
design curve of M. (d) The power conversion efficiency η.
HASE et al.: NOVEL DESIGN PROCEDURE FOR MOSFET CLASS E OSCILLATOR
2245
parameters are large since the current i through the resonant
circuit is nonsinusoidal. From Fig. 3(c), we can find that
the variation of M is small. This is because the phase-shift
between input and output of the feedback network has a little change even if the current i through the resonant circuit
is nonsinusoidal. From Fig. 3(d), the power conversion efficiency η of the oscillator keeps over than 90% for Q > 2. On
the other hand, the characteristic curve of η varies rapidly
for Q < 2. Therefore, we think that Q = 2 is the lower
limit of Q for these specifications. From this figure, we can
find that the design parameters are greatly influenced by the
waveforms of the current i through the resonant circuit.
Figure 4 shows the design curves of A, B, M and the
power conversion efficiency η of the oscillator as a function
of H for Q = 3, 5, and 10. When H is small, LC works as
RF choke and the input current iC is direct. Therefore, the
design parameters are almost constant for small H. However, in the range of large H, the design parameters are varied since LC works as finite dc-feed inductance and iC is not
direct. From Fig. 4(c), it is confirmed that M varies as H
varies. This result shows that the parameter of the amplifier
affects the design of the feedback network and denotes the
importance of our opinion that class E oscillator should be
considered as one circuit at the design. From Figs. 4(a)–(c),
there are limitations of H for these specifications. The maximum values of H are 3.4, 3.2 and 4.3 for H = 3, 5 and 10,
respectively in Fig. 4. Moreover, from Fig. 4(d), the power
conversion efficiency η increases as H increases. Therefore,
finite dc-feed inductance achieves not only the miniaturization of circuit scale but also high efficiency operation.
From Fig. 3 and Fig. 4, it is confirmed that we can de-
Fig. 4 The design parameters as a function of H for J = 1.0 and K = 0.1.
(a) The design curve of A. (b) The design curve of B. (c) The design curve
of M. (d) The power conversion efficiency η.
rive the design values of class E oscillator with any output
Q, finite dc-feed inductance and switch on resistance. When
we notice the power conversion efficiency η, class E oscillator should be designed for high Q and high H. When we
notice the miniaturization of circuit scale, class E oscillator
should be designed for low Q and high H.
7.
Experimental Results
We carry out two circuit experiments. At the first experiment, class E oscillator with high Q and low H is designed.
The design specifications are the operating frequency f =
2.0 MHz, the input voltage VD = 12 V, R = 10 Ω, H =
0.003, Q = 10, J = 1.0 and K = 0.1. From the above
specifications, LC and L0 are determined as LC = 2.65 mH
and L0 = 7.95 µH. Therefore, we can make inductors LC and
L0 before the calculations for the design. From these inductors, ESR’s of LC and L0 can be measured as rC = 0.04 Ω
and r0 = 0.20 Ω. The resonant frequency in the feedback
network is nearly equal to the operating frequency. Therefore, we assume r f = 0.09 Ω from the relation of L0 and
r0 . We use these values of ESR’s for the calculations of
the design. In this experiment, we use IRF530 MOSFET
whose characteristics are measured as shown in Table 1.
From VD =12 V and Vth =3 V, we give Rd1 = 750 kΩ and
Rd2 = 250 kΩ. By using above specifications and the proposed design procedure, we derive the design parameters
as A = 0.863, B = 0.599 and M = 0.808. From these
parameters, the element values of class E oscillator are derived as shown in Table 2. Figure 5 depicts the experimental
waveforms and the calculated ones for the conditions in Table 2. From this figure, the input current iC is direct and the
output voltage vo is sinusoidal because of low H and high
Q. The experimental waveforms are satisfied with class E
switching conditions. In this circuit experiment, class E oscillator achieves 90.7% power conversion efficiency under
6.8 W, 2.02 MHz output operation.
At the second experiment, class E oscillator with low Q
and high H is designed. In these specifications, it is impossible to design class E oscillator by the conventional design
procedure. The design specifications are the operating fre-
Fig. 5 Experimental results for f = 2.0 MHz, VD = 12 V, R = 10 Ω,
H = 0.003, Q = 10, J = 1.0 and K = 0.1. (a) Experimental waveforms.
Vertical: iC : 1 A/div, vS , vo and v f : 20 V/div. Horizontal: 200 ns/div (b)
Calculated waveforms.
IEICE TRANS. FUNDAMENTALS, VOL.E87–A, NO.9 SEPTEMBER 2004
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Table 2
Design values of class E oscillator for Q = 10 and H = 0.003.
LC
L0
Lf
CS
C0
C1
C2
R
Rd1
Rd2
rC
r0
rf
f
VD
Vo
IC
η
Table 3
Calculated
2.65 mH
7.95 µH
4.55 µH
1.54 nF
922pF
922pF
9.22 nF
10.0 Ω
250 kΩ
750 kΩ
0.04 Ω
0.20 Ω
0.09 Ω
2.00 MHz
12.0 V
8.30 V
0.640 A
89.6%
Measured
2.50 mH
7.81 µH
4.61 µH
1.59 nF
909pF
914pF
9.08 nF
9.95 Ω
240 kΩ
750 kΩ
0.04 Ω
0.20 Ω
0.11 Ω
2.02 MHz
12.0 V
8.24 V
0.627 A
90.7%
Table 4
Difference
−5.7%
−1.8%
1.3%
3.2%
−1.4%
−0.9%
−1.5%
−0.5%
−4.0%
0.0%
0.0%
0.0%
22.2%
1.0%
0.0%
−0.7%
−2.0%
1.1%
Design values of class E oscillator for Q = 3 and H = 1.
LC
L0
Lf
CS
C0
C1
C2
R
Rd1
Rd2
rC
r0
rf
f
VD
Vo
IC
η
Calculated
2.39 µH
2.39 µH
4.14 µH
3.51 nF
4.25 nF
4.25 nF
42.5 nF
10.0 Ω
750 kΩ
750 kΩ
0.09 Ω
0.09 Ω
0.14 Ω
2.00 MHz
6.0 V
5.45 V
0.549A
90.2%
Measured
2.39 µH
2.42 µH
4.27 µH
3.46 nF
4.26 nF
4.26pF
42.6 nF
9.92 Ω
750 kΩ
750 kΩ
0.09 Ω
0.09 Ω
0.12 Ω
1.97 MHz
6.0 V
5.27 V
0.520A
89.7%
Difference
0.0 %
1.3 %
3.1 %
−1.4 %
0.2 %
0.2 %
0.2 %
−0.8 %
0.0 %
0.0 %
0.0 %
0.0 %
−14.3 %
−1.5 %
0.0 %
−3.3 %
−5.3 %
−0.5 %
The model of IRF530 MOSFET used in the second experiment.
threshold voltage Vth
switch on resistance rS
gate-source capacitance Cg
gate-source resistance rg
3.0 V
0.16 Ω
1.66 nf
2.36 Ω
quency f = 2.0 MHz, the input voltage VD = 6 V, R = 10 Ω,
H = 1, Q = 3, J = 1.0 and K = 0.1. From the above specifications, LC and L0 are determined as LC = L0 = 2.39 µH.
From these inductors, ESR’s of LC and L0 can be measured
as rC = 0.09 Ω and r0 = 0.09 Ω. We assume r f = 0.14 Ω.
We use these values of ESR’s for the calculations of the design. In this experiment, we use IRF530 MOSFET whose
characteristics are measured as shown in Table 3. From
VD =6 V and Vth =3 V, we give Rd1 = Rd2 = 750 kΩ. By
using our design procedure, we derive the design parameters as A = 0.624, B = 1.211 and M = 0.920. From these
parameters, the element values of class E oscillator are derived as shown in Table 4. Figure 6 depicts the experimental
waveforms and the calculated ones. From this figure, the input current iC is not direct and the output voltage vo is nonsinusoidal because of high H and low Q. The experimenal
waveforms are satisfied with class E switching conditions.
Therefore, we can confirm that the design values which are
satisfied with the desired conditions can be determined in
spite of low Q and high H by using proposed design procedure. In this circuit experiment, class E oscillator achieves
89.7% power conversion efficiency under 2.8 W, 1.97 MHz
output operation.
In Figs. 5(a) and 6(a), the experimental waveforms of
v f are afffected by switching characteristics of the MOSFET.
Therefore, the waveforms of v f lose their shapes a little.
From Figs. 5 and 6, and Tables 2 and 4, we find that the
experimental results agree with the calculated ones quantitatively and we show the validity of the proposed design
procedure.
Fig. 6 Experimental results for f = 2.0 MHz, VD = 6 V, R = 10 Ω,
H = 1, Q = 3, J = 1.0 and K = 0.1. (a) Experimental waveforms. Vertical:
iC : 1 A/div, vS , vo and v f : 10 V/div. Horizontal: 200 ns/div (b) Calculated
waveforms.
8.
Conclusion
This paper has presented a novel design procedure for class
E oscillator. And the design curves of class E oscillator for
any conditions have been clarified. It is the characteristic of
the proposed design procedure that a free-running oscillator
is considered as a forced oscillator and the feedback waveform is tuned to the timing of the switching. Moreover, in
the proposed design procedure, we consider class E oscillator as one circuit though it is divided into class E amplifier
and the feedback network for the conventional design. By
carrying out two circuit experiments, we find that the experimental results agree with the calculated ones quantitatively,
and show the validity of the proposed design procedure.
One experimental measured power conversion efficiency is
90.7% under 6.8 W output power at an operating frequency
2.02 MHz for high Q and low H. The other is 89.7% under 2.8 W output power at an operating frequency 1.97 MHz
for low Q and high H. The proposed design procedure is
applicable to the design for many kinds of oscillators.
HASE et al.: NOVEL DESIGN PROCEDURE FOR MOSFET CLASS E OSCILLATOR
2247
Acknowledgments
This work was partially supported by Support Center
for Advanced Telecommunications Technology Research
(SCAT), The Telecommunications Advancement Foundation (TAF), and The Yazaki Memorial Foundation for science and Technology.
Hiroyuki Hase
was born in Tokyo, Japan,
on September 21, 1980. He received the B.E.
degree from Chiba University, Japan, in 2004.
He is a M.E. candidate in Graduate School of
Science and Technology, Chiba University. His
research interests include high-frequency highefficiency oscillator, resonant dc/dc power converter and dc/ac inverter.
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Hiroo Sekiya
was born in Tokyo, Japan,
on July 5, 1973. He received the B.E., M.E.,
and Ph.D. degrees in electrical engineering from
Keio University, Yokohama, Japan, in 1996,
1998, and 2001 respectively. Since April 2001,
He has been with Graduate School of Science
and Technology, Chiba University, Chiba, Japan
where he is a Research Associate. His research
interests include high-frequency high-efficiency
tuned power amplifiers, frequency multipliers,
resonant dc/dc power converter, dc/ac inverters,
bifurcation and chaotic phenomena in nonlinear electrical circuits, and digital signal processing for speech, image and communication. Dr. Sekiya
is a member of IEEE and Research Institute of Signal Processing (RISP),
Japan.
Jianming Lu
received the M.S., and Ph.D.
degrees from Chiba University, Japan, in 1990
and 1993, respectively. In 1993, he joined Chiba
University, Chiba, Japan, as an Associate in the
Department of Information and Computer Sciences. Since 1994 he has been with the Graduate School of Science and Technology, Chiba
University, and in 1998 he was promoted to Associate Professor in the Graduate School of Science and Technology, Chiba University. His current research interests are in the theory and applications of digital signal processing and control theory. Dr. Lu is a member of IEEE (USA), SICE (Japan), IEEJ (Japan) and JSME (Japan).
Takashi Yahagi
received the B.S., M.S.,
and Ph.D. degrees all in electronics engineering
from the Tokyo Institute of Technology, Tokyo,
Japan, in 1966, 1968 and 1971, respectively. In
1971, he joined Chiba University, Chiba, Japan,
as a Lecturer in the Department of Electronics
Engineering. From 1974 to 1984 he was an Associate Professor, and in 1984 he was promoted
to Professor in the Department of Electrical Engineering. From 1989 to 1998, he was with the
Department of Information and Computer Sciences. Since 1998 he has been with the Graduate School of Science and
Technology, Chiba University. His current research interests are in the theory and applications of digital signal processing and other related areas.
He is the editor of the “Library of Digital Signal Processing” (Corona Pub.
Co., Ltd., Tokyo, Japan). Since 1999 he has been Chairman of the IEEE
Japan Chapter of Signal Processing Society. Dr. Yahagi is a member of
IEEE (USA), The New York Academy of Sciences (USA), ISCIE (Japan).