Vol. 37, No. 2
Journal of Semiconductors
February 2016
A transient-enhanced NMOS low dropout voltage regulator with parallel feedback
compensation
Wang Han(王菡)Ž and Tan Lin(谭林)
Analog IC Design Department, 24th Research Institute of China Electronics Technology Group Corporation,
Chongqing 400060, China
Abstract: This paper presents a transient-enhanced NMOS low-dropout regulator (LDO) for portable applications
with parallel feedback compensation. The parallel feedback structure adds a dynamic zero to get an adequate phase
margin with a load current variation from 0 to 1 A. A class-AB error amplifier and a fast charging/discharging unit
are adopted to enhance the transient performance. The proposed LDO has been implemented in a 0.35 m BCD
process. From experimental results, the regulator can operate with a minimum dropout voltage of 150 mV at a
maximum 1 A load and IQ of 165 A. Under the full range load current step, the voltage undershoot and overshoot
of the proposed LDO are reduced to 38 mV and 27 mV respectively.
Key words: parallel feedback compensation; class-AB amplifier; fast charging/discharging unit; transient response; low-dropout regulator (LDO)
DOI: 10.1088/1674-4926/37/2/025005
PACS: 85.40.-e; 84.30.Le
EEACC: 1205
1. Introduction
Low dropout linear regulators (LDOs) are widely used in
portable battery-powered electronic devices due to their low
noise and fast response characteristics. In CMOS technology,
depending on whether the power transistor is an N- or Ptype low dropout linear regulators have two general categories.
PMOS LDOs offer high voltage headroom and good power efficiency, however, with respect to the use of the NMOS counterpart, it has a slower response time, degraded load regulation, lower maximum output current (for the same area) and
requires complex frequency compensation schemesŒ1 . Thus,
NMOS LDOs are increasingly popular in the industry. Recently, several NMOS LDOs with the low dropout characteristic have been presentedŒ2 5 .
In NMOS LDO architecture, the power transistor operates
as a source follower and the output pole is located at high frequency making it an on-dominant pole. These circuits may be
compensated internally and consequently the need for an external capacitor is eliminated. However, during load transients,
the output capacitor acts as a charge buffer to absorb (provide)
the current difference between the load and the power transistor. Elimination of the output filtering capacitor will lead to severe output voltage changes during fast load transients, which
the power-line-sensitive devices supplied by the LDO cannot
tolerate. Thus, NMOS LDOs generally do not need a load capacitor for stability; load capacitors are nevertheless used in
most applications to help improve transient performance.
If an output capacitor is presented, due to the finite
transconductance of the power transistor, the load capacitance
causes a second pole at the output node of LDO. Moreover, the
output pole movement is wide when the load current varies,
which adds complexity for compensation. To deal with this
wide movement of the output pole, roughly speaking, two
methods might be effective. (1) Make the output pole always
out of the expected bandwidth. (2) Accommodate the output
pole movement by adding a dynamic zero.
Method 1 can be realized by increasing the standby load
current (e.g. in mA range) to move the output pole to a higher
frequency, but this is unacceptable in low quiescent current applications. It can also be realized by some pole-splitting methodsŒ6 10 , which push the output pole out of the bandwidth.
However, there are two reasons that make this solution not
suitable. One is the gain of the NMOS power transistor in the
source follower configuration that is near unity which makes
pole spitting very difficult. The other is that the large load capacitor makes the output pole be at a relatively low frequency.
To push this pole to the higher frequency may require a very
large spitting capacitor and high current consumption. Method
2 can be realized by some dynamic zero compensation techniquesŒ11 13 . The traditional technique to generate a low frequency zero relies on passive components, which will bring an
associate pole with it.
In this paper, a low dropout regulator with parallel feedback compensation is proposed. It is composed of a global reference tracking loop for steady state accuracy and a secondary
parallel feedback loop, which adds a dynamic compensation
zero to the voltage transfer characteristic. In addition, a classAB operational amplifier is utilized to improve the slew rate at
the gate of the power transistor and a fast charging/discharging
unit serves as a plug-in module to enhance the recovery of the
parallel feedback loop from the transient condition. Thus, a fast
and current-efficient LDO can be achieved.
2. Parallel feedback compensation
Figure 1 shows the proposed structure. It is composed of a
global reference tracking loop for steady state accuracy and a
secondary parallel feedback loop, which adds a dynamic compensation zero to the voltage transfer characteristic. The ref-
† Corresponding author. Email: eehanwang@163.com
Received 2 June 2015, revised manuscript received 25 August 2015
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J. Semicond. 2016, 37(2)
Wang Han et al.
at higher frequencies. The output capacitor CL introduces the
second dominant pole, the movement of which is wide as the
load current varies.
The loop gain of the parallel feedback loop is the product
of dc gains of the subsidiary amplifier and the high pass filter:
sCf Rf
gm2 rO
;
1 C sro .C1 C CP / 1 C sCf Rf
(6)
where gm2 is the transconductance of the subsidiary amplifier.
The loop gain of the parallel feedback loop can be divided into
three different regions. At low frequency, the loop gain is indicated by the expression:
T .s/ D Asub .s/ AHP .s/ T .s/ gm2 rO sCf Rf :
Once the impedance of capacitor C1 and CP decreases below the rO , the loop gain flattens and levels to
Figure 1. Block diagram of the proposed regulator.
erence tracking loop includes an error amplifier, an NMOS
power transistor, a high resistance feedback network and an
output capacitor. The parallel feedback loop includes a unity
gain voltage buffer, a high pass filter and a subsidiary amplifier. The added zero tracks the pole at the output node of the
LDO to make the compensation effective for a wide range of
load current and output capacitor values CL .
Figure 2 shows the small-signal model of the regulator,
where CL and RL model the load capacitor and load impedance.
In order to investigate the stability of the circuit with dual feedback loops, the reference tracking loop and the parallel feedback loop are analyzed separately. The loop gain of the reference tracking loop is represented by
ARTLopen .s/ D ARTL
;
s
s
1C
1C
!p1
!p2
(1)
where ARTL is the DC open-loop gain, and it is the product of
DC gains of the error amplifier and resistance feedback network as follows:
ARTL D gm1 rO ˇ;
(2)
where gm1 is the transconductance of the error amplifier and
rO models the output impedance. ˇ is the voltage ratio of the
output feedback network. !p1 and !p2 are given by
!p1 D 1=rO .C1 C CP /;
(3)
!p2 D 1=.RO ==RL /CL gmn =CL ;
(4)
gm1 ˇ
;
(5)
C1 C CP
where gmn is the transconductance and CP is total gate capacitance of the power device. RO denotes the output impedance
of the power stage which is 1/gmn in the source follower structure and is much smaller than RL . The dominant pole !p1 is
located at the output node of the error amplifier. The second
dominant pole !p2 is derived from the transconductance of the
power device and load capacitor.
Figure 3 depicts the frequency response of the proposed
regulator. The frequency response of the reference tracking
loop is shown as the solid line. The dominant !p1 causes the
reference tracking loop gain to roll off at –20 dB per decade
GBW D
(7)
T .s/j1=rO .C1 CCp /<!<1=Rf Cf gm2 Cf Rf =.Cl C CP /:
(8)
At high frequency, the high-pass filter capacitor Cf acts as
a short, and the loop gain falls again at 20 dB per decade,
which equates to
T .s/j!>1=Rf Cf gm2 =s.Cl CP /:
(9)
The frequency response of the parallel feedback loop is
depicted by the dashed line curve in the bode plot of Figure 3.
Without the foregoing parallel feedback path, the overall
loop response follows the reference tracking loop characteristics. At a frequency higher than gmn =CL , the loop response
rolls off at –40 dB per decade, passing the 0 dB line and continuing along the thin dashed line as shown in the bode plot of
Figure 3, resulting in a low phase margin. With the foregoing
parallel feedback path, the roll-off signal of the reference tracking loop encounters and combines with the signal through the
parallel feedback loop, and ceases being dominant. The overall loop response no longer rolls off along the thin dashed line,
and instead makes a turn at the frequency
!z D
gm1 gmn
:
gm2 CL
(10)
In other words, a zero at the frequency !z changes the overall gain roll-off back to –20 dB per decade. It can be seen from
Equation (10) and Figure 3 that the location of the !z tracks
the location of the second dominant pole irrespective of how
the load and output capacitor change. It should be noticed that
trade-offs need to be made in choosing the product gm1 =gm2 .
Specifically, if the error amplifier and the subsidiary amplifier
were to have equal transconductance, the phase margin would
be 90ı and a complete pole-zero cancellation is realized. However, the signal from the parallel feedback loop becomes so
strong that it significantly undermines the feedback loop controlling the main signal path leading to large transient undershoot and overshoot in Vout . On the other hand, if gm1 =gm2
is chosen to be too large, the loop may not be compensated
enough. In this design, the value of gm1 =gm2 D 10 may be used.
3. Circuit implementation
Figure 4 shows the schematic of the proposed transientenhanced parallel feedback LDO. The control circuit and
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Wang Han et al.
Figure 2. Equivalent small-signal model of the proposed regulator.
lowers and M1/M2/M5/M8 carry equal bias current set by M6
and M9. In the transient state, when Iload suddenly increases,
VOUT drops rapidly. The gate–source voltage of M5 and M8
are kept approximately constant by flipped voltage followers,
which makes the gate–source voltage of M1 increase while the
gate–source voltage of M2 decreases by the same amount. The
difference between the gate–source voltage of M1 and M2 generates current variations with the square law. Therefore, the
current through M1 increases drastically, and M14 pulls the
gate voltage of MN up quickly. Similarly, when the Iload suddenly decreases, the current through M2 increases drastically,
and M16 pulls the gate voltage of MN down quickly. Hence,
the slew rate improves and the settling time of LDO is greatly
reduced.
Figure 3. Frequency response of the proposed regulator.
power transistor in Figure 4 are powered by different supply
rails (VDD and VIN) in order to reduce the dropout voltage.
Input pairs M1/M2 and M3/M4 implement gm1 and gm2
in Figure 2, and M11–M16 combine their respective ac output
currents into VP . The prototyped LDO senses the gate signal
VP with parallel signal path transistor M17, which is designed
to have a very small ratio to the power transistor MN. The signal is then converted into the second feedback voltage VFB2 via
the high pass filter and couples to the input of the subsidiary
amplifier. An important difference in the structure of Figure 4
from that of Figure 1 is that the dc voltage at the input of the
subsidiary amplifier is set to VREF instead of GND. The reason
is that the drain voltage of input pair M3/M4 is the gate–source
voltage of M11/M15. Setting the DC voltage at the input of the
subsidiary amplifier to GND will push M3/M4 into the linear
region. Thus, a unity gain voltage buffer LVR is inserted to provide a low impedance VREF voltage reference for the feedback
signal of the subsidiary amplifier. The impedance at node VA
is determined by the transconductance of input pair M18/M19.
To improve the slew rate at the gate of the power transistor, the class-AB structureŒ14; 15 is introduced in the error amplifier. In the steady state, the gate–source voltage of
M1/M2/M5/M8 are forced to be equal by flipped voltage fol-
R1 limits C1 ’s shunt current to introduce a zero at
1/2R1 C1 , whose objective is to cancel the effects of the parasitic pole at high frequency. Similarly, CFF feeds forward inphase signals from VOUT to VFB1 to generate a zero that offsets
high frequency poles and improve the transient response.
Figure 5 indicates the simulated loop-gain transfer function of the regulator with parallel feedback compensation. The
load current was changed from 0 to 1 A. From the results, the
proposed LDO is absolutely stable under any operational condition with an off-chip capacitor with the worst case phase margin of 60ı .
The high pass filter components Rf and Cf should be large
to make the compensation effective. However, a large Rf and
Cf would significantly reduce the transient response of LDO.
To understand the phenomenon, we can consider the case when
a transient load increase occurs and the output voltage drops.
The error amplifier would respond by increasing the voltage at
the gate of the power transistor. The sudden voltage increase at
node VP would be sensed by parallel signal path transistor M17
and consequently VFB2 would experience a transient voltage increase as well as causing the subsidiary amplifier to counteract by reducing the voltage at the gate of the power transistor.
Due to the large value of Rf and Cf , the recovery of VFB2 to
a steady state is slow, which would significantly delay the recovery time of the reference tracking loop and deteriorate the
transient response of the LDO regulator. To solve the problem,
a fast charging/discharging unit is introduced.
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Wang Han et al.
Figure 4. Schematic of the transient-enhanced parallel feedback LDO.
Figure 5. Simulated frequency response of the regulator with parallel
feedback compensation.
gate terminals of M24/M25 are biased such that a current I2
flows on each path of M24/M25 when M24/M25 are in saturation with I2 being greater than I1 . In the steady state, since
the saturation currents of M24/M25 are greater than M22/M23,
M24/M25 operate in the linear region and M27–M30 are off. In
the transient state, when VFB2 falls below the desired value, the
current through M22 approaches I2 and the drain–source voltage of M24 increases. Current source M27 switches on and
supplies current to node VFB2 , thereby raising the voltage of
VFB2 momentarily. When VFB2 rises above the desired value, the
current through M23 approaches I2 and the drain–source voltage across M25 increases. M28 switches on thereby switching
on transistor M29. Since M29 and M30 are current mirror pairs,
current sink M30 is switched on, and sinks current from node
VFB2 , thereby lowing the voltage of VFB2 immediately. Thus, a
fast charging/discharging path of the capacitor Cf is provided
when a transient voltage disturbance of VFB2 occurs, which reduces the recovery time of the parallel feedback loop and improves the transient response of LDO.
Figure 7 shows the simulated load transient performance
of the regulator with and without the proposed F C/D unit. As
seen in Figure 7, the regulator with the proposed F C/D unit
settles 80% faster.
4. Experimental results
Figure 6. Fast charging/discharging unit in parallel feedback loop.
Figure 6 shows the schematic of the fast charging/discharging unit. The voltage at the gate of M26 is provided
that when VREF equals VFB2 , a current 2I1 flows on transistor
M26, and a current I1 flows on each path of M22/M23. The
The proposed LDO was implemented in 0.35 m BCD
technology. Figure 8 shows the die photograph. The system
was designed to source a nominal output current of 1 A with
a 10 F load capacitor. The regulator consumes 165 A quiescent current and the minimum dropout voltage is approximately 150 mV. Figure 9 shows the measured load transient
response when the loading current switches between 0 and 1 A.
When the load is switched on there is an internal voltage undershoot of 38 mV and switching the load off results in a voltage
overshoot of 27 mV. The measured VIN and VDD line transient response of the proposed LDO are shown in Figures 10
and 11. When the change in the VIN and VDD of the LDO is
1 V, the output voltage changes by less than 43 and 75 mV re-
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Wang Han et al.
Figure 10. Measured output wave form of line transient response with
VIN switch between 1.5 and 2.5 V.
Figure 7. Simulation result of load transient response for the LDO with
and without the F C/D unit with a 1 A load current change.
Figure 11. Measured output wave form of line transient response with
VDD switch between 3 and 4 V.
5. Conclusion
An LDO regulator with parallel feedback compensation
and fast transient response is presented in this paper. The design details, including circuit implementation, small-signal response and transient performance, have been presented. Both
simulation and experimental results have proven the stable operation in all load conditions and the improvement of the transient response. Meanwhile, the quiescent current and dropout
voltage are maintained at low levels to achieve a high power
efficiency.
Figure 8. Chip photograph of the proposed LDO.
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Figure 9. Measured output wave form of load transient response with
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spectively at Iload D 10 mA. A positive input voltage transient
produces larger spike durations since the output capacitance is
easier to charge than discharge due to the quadratic current–
voltage (I –V ) characteristics of the pass transistor.
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