Project 4: Layout design of CMOS circuits
Yuan-Ze University
Department of Computer Science and Engineering
© Copyright by Rung-Bin Lin, 1999
All rights reserved
Out: 4/28/2003 Due: 5/13/2003
Purpose:
This project is to make students becoming familiar with the commercial CAD tools
employed to perform fully customized CMOS circuit layout.
Introduction:
Transistors are created by superimposing various layers of transistor-forming
materials. The sizes of geometric objects and interrelationship among the objects on
these layers (may be on the same layer) must satisfy some particular constraints such
that the fabricated transistors can functionally and electrically correct. The constraints
are usually collectively formulated as a set of layout design rules. The purpose of
layout (also called physical layout or physical design) is to arrange the
transistor-forming geometric objects under the constraints of layout design rules such
that the fabricated transistors can perform their specified function. Layout design rules
vary from one process technology to another, thus when the same circuit design is
realized by two different processes, their layouts must be different.
In this project one is supposed to employ a fully customized layout design flow based
on Cadence tool set to perform physical layout of some basic circuits. (Cadence is a
CAD tool vendor that sells various kinds of IC design CAD tools such as tools for
logic simulation and synthesis, layout design and verification, placement and routing,
etc. ) The fully customized design flow is shown in Figure 4.1. The layout design
process starts from the target specifications. At this moment we have to set a target or
constraint respectively on area, timing and power. For example, when a 4-input AND
gate is designed, a target or constraint can be specified as follows:
(1). area is less than 80um2,
(2). power is less than 2 pico-Watt, and
(3). rise and fall propagation delays are approximately 1.2 ns and output rise and fall
times are approximately 0.6ns when input transition time is 0.5ns and output load
is 0.3pF.
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Some other constraints about geometric shapes of a layout may be specified. Once
this step is done, it then follows transistor circuit schematic design, carried out by
Cadence Composer. The transistor sizes of p- and n-transistors must be specified such
that the desired timing/power target can be reached. Timing and power measurements
can be performed by Hspice circuit simulation. If timing and power do not meet the
specifications, transistor sizes is tuned or circuit schematic is redesigned until the
specifications are satisfied. Note that circuit simulation is also employed to check the
correctness of functionality of a circuit.
Target
speccifications
Circuit schematic
design
Composer
Schematic Editor
NO
Circuit simulation
(timing/power meets
specification?)
Hspice
YES
Layout design
Virtuoso Layout
Editor & Tech.
file
Layout verification
and circuit extraction
Dracula Command
files...............LVS
, LPE, DRC, ERC
NO
NO
YES
Post layout circuit simulation
(timing/power meets
specifications)
Hspice
YES
Done
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Figure 4.1. The fully customized layout design flow
Layout design commences once a circuit design is completed. It is carried out by
Cadence Layout Virtuoso Editor. At this moment, transistor-forming geometric
objects are sketched under the constraints of layout design rules. The transistors are
drawn according to the specified transistor sizes. After layout is completed, layout
verification and circuit extraction are performed by Dracula tool set. Dracula includes
tools for layout design rule check (DRC), layout parasitic capacitance extraction
(LPE), layout parasitic resistance extraction (PRE), and layout versus schematic (LVS)
comparison, etc. DRC, LPE, and PRE are intuitively understandable. Note that LPE
also carries out circuit extraction. LVS is performed to ensure that the design
represented by circuit schematic is functionally equivalent to the one represented by
physical layout. This step is very important since an error during LVS usually
indicates that there exists an error in schematics or/and layout of a circuit.
The most creative task in the design flow shown in Figure 4.1 is the layout task. Some
decisions about the width and locations of power/ground bus, the placement and
orientation of transistors, the width of wires and their routing, etc. have to be made.
Figure 4.2 shows a layout of a circuit. The circle on the layout is not a geometric
object for the circuit and should be ignored.
Figure 4.2. A layout
Problem descriptions:
1. Design an inverter with a fixed-size pMOS (W=2um, L=1um, a=W, b=2um) and
nMOS (W=1um, L=1um, a=W, b=2um) transistors. One has to follow the design
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flow shown in Figure 1. Perform Hspice simulation prior to layout (i.e., simply
use the circuit design from the schematic) and after layout (ie., use the circuit
extracted from layout) under a fixed output load (CL=0.1pF) and an input waveform
with a fixed slope (rise-time=fall-time=0.5ns).
(a). Compare the source, drain and gate capacitance extracted by LPE to those
calculated in the problem (1) of the project 2.
(b). Compare the rise/fall time (Tr and Tf) and propagation delay (Tdr and Tdf) for
the circuit prior to layout to those for the circuit extracted from the layout.
2. Minimize the area of the layout for the circuit designed in (1) as much as possible
by reducing the area of source/drain of the transistors or re-arranging the transistors.
(a). Compare the area prior to and after layout.
(b). Compare the post layout rise/fall time (Tr and Tf) and propagation delay (Tdr
and Tdf) of this circuit to those of the circuit extracted in (1).
3. Cascade two inverter circuits designed in (2) to make a non-inverting buffer.
Measure the rise/fall time (Tr and Tf) and propagation delay (Tdr and Tdf) of the
buffer under the same input conditions and output load.
4. Design a 3-input NAND gate such that its rise/fall time (Tr and Tf) and propagation
delay (Tdr and Tdf) are respectively about 0.5ns, 0.5ns, 1.5ns and 1.5ns and its area
is minimized (with a fixed output load CL=0.4pF and input rise/fall times 0.5ns).
Notes:
♥ All layouts designs must pass LVS and LPE. The final timing data should be
generated using the netlist generated by LPE.
♥ A tutorial on the design flow shown in Figure 1 can be found on the web.
References:
[1]. HSPICE User’s Manual, Meta-Software, 1990.
[2]. “Composer Tutorial,” Cadence.
[3]. “Virtuoso Layout Editor Help,” Cadence.
[4]. “Diva Interactive Verification Reference,” Cadence.
[5]. “Dracula User Guide,” Cadence.
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