Principles of VLSI Design
Circuit Characterization and Performance Estimation
CMPE 413
Delay Definitions
 tpdr: rising propagation delay
From input to rising output crossing VDD/2
 tpdf: falling propagation delay
From input to falling output crossing VDD/2
 tpd: average propagation delay
tpd = (tpdr + tpdf)/2
 tr: rise time
From output crossing 20% to 80% VDD
 tf: fall time
From output crossing 80% to 20% VDD
 tcd: average contamination delay
tcd = (tcdr + tcdf)/2
„ tcdr: rising contamination delay: Min from input to rising output crossing VDD/2
„ tcdf: falling contamination delay: Min from input to falling output crossing VDD/2
1
Principles of VLSI Design
Circuit Characterization and Performance Estimation
CMPE 413
Delay Estimation
Solving differential equations by hand is hard.
SPICE like simulators used for accurate analysis. But simulations are expensive.
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
We need to be able to estimate delay although not as accurately as simulator.
Use RC delay models to estimate delay
„ C = total capacitance on the output node
„ Use Effective resistance R
„ Therefore tpd = RC
Transistors are characterized by finding their effective R.
2
Circuit Characterization and Performance Estimation
Principles of VLSI Design
CMPE 413
RC Delay Models
Equivalent circuits used for MOS transistors
„ Ideal switch + capacitance and ON resistance
„ Unit NMOS has resistance R, capacitance C
„ Unit PMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance is inversely proportional to width
d
g
d
k
s
s
kC
R/k
kC
2R/k
g
g
kC
kC
s
d
k
s
kC
g
kC
d
3
Principles of VLSI Design
Circuit Characterization and Performance Estimation
CMPE 413
RC Delay Models
A 3-input NAND gate with transistor widths chosen to achieve effective rise and fall resistance equal to that of a unit inverter (R)
2
2
2
3
3
3
3 NMOS in series = 3R, therefore each has to be three times the minimum width.
3 PMOS(2R) in parallel, worst case one ON, therefore each has to be twice minimum width
4
Circuit Characterization and Performance Estimation
Principles of VLSI Design
CMPE 413
RC Delay Models
3-input NAND gate with it's gate and diffusion capacitances (assuming all nodes are contacted). Estimated at the schematic level, values will be different if you look at layouts.
Capacitance can be lower if you look at the layout
2C
2
2C
2C
2C
2
2C
2C
2
2C
3C
3C
3C
2C
2
2
2
2C
3
3
3
3C
3C
3C
3
5C
5C
5C
3
3
9C
3C
3C
3C
Conservative estimate would assume that this two
diffusions are uncontacted and therefore have lower capacitance
(the difference is usually ignored for hand calculations)
5
Principles of VLSI Design
Circuit Characterization and Performance Estimation
CMPE 413
RC Delay Models: Layouts
Good layout minimizes diffusion area.
NAND3 gate shown below, shares one diffusion contact, thus lowering the output
capacitance by 2C. Contacted diffusions are assumed.
2C
Shared
Contacted
Diffusion
2C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
2
2
3
3
3C 3C 3C
3
7C
3C
3C
6
Principles of VLSI Design
Circuit Characterization and Performance Estimation
CMPE 413
RC Delay Models: Layout Comparison
Which layout is better?
VDD
A
VDD
B
Y
GND
A
B
Y
GND
7
Circuit Characterization and Performance Estimation
Principles of VLSI Design
CMPE 413
Elmore Delay
ON transistors are considered as resistors.
Pull-up or pull-down networks are considered as RC ladders.
Elmore Delay of a RC ladder:
t pd =
∑
R
nodes i
C
n−i i
= R 1 C 1 + ( R 1 + R 2 )C 2 + … + ( R 1 + R 2 + … + R N )C N
R1
R2
R3
C1
C2
RN
C3
CN
8
Circuit Characterization and Performance Estimation
Principles of VLSI Design
CMPE 413
Elmore Delay
Rising propagation delay of a 2-input NAND gate driving h identical NAND gates
2
2
A
2
B
2x
6C
Y
4hC
2C
R
Y
(6+4h)C
h copies
t pdr = ( 6 + 4h )RC
9
Circuit Characterization and Performance Estimation
Principles of VLSI Design
CMPE 413
Elmore Delay
Falling propagation delay of a 2-input NAND gate driving h identical NAND gates
2
2
A
2
B
2x
x
R/2
R/2
2C
6C
Y
4hC
2C
Y
(6+4h)C
h copies
R
R R
t pdf = ( 2C ) ⎛ ----⎞ + [ ( 6 + 4h )C ] ⎛ ---- + ----⎞
⎝ 2 2⎠
⎝ 2⎠
= ( 7 + 4h )RC
10
Circuit Characterization and Performance Estimation
Principles of VLSI Design
CMPE 413
Delay Components and Contamination Delay
Total delay is composed of two parts:
„ Parasitic delay: 6 or 7 RC in previous example, independent of load
„ Effort delay: 4h RC in previous example proportional to load capacitance.
Contamination Delay (best case delay): can be substantially less than propagation delay.
Example: Both inputs fall simultaneously in 2-input NAND gate.
2
2
A
2
B
2x
6C
Y
4hC
2C
R R
Y
(6+4h)C
t cdr = ( 3 + 2h )RC
11