Generics--Motivation
System Design w/ VHDL
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Oftentimes we want to be able to
specify a property separately for each
instance of a component
• Delay
• Bit width
Generics and
Configurations
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VHDL allows models to be
parameterized with generics
pp. 104-107, 153-156, 261-264,
292-307,
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Allows one to make general models
instead of making specific models
for many different configurations of
inputs, outputs, and timing
information.
entity NAND_GATE is
generic (N: Natural := 2;
D: Time := 10 ns);
port (A: in Bit_Vector (1 to N);
Z: out Bit);
end NAND_GATE;
Information passed into a design
description from its environment.
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Algorithmic architecture
for generic NAND gate
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Specification of Generic
Values (1/3)
architecture NAND_N_D of NAND_GATE is begin
NAND_CAL: process (A)
variable RESULT: Bit;
begin
RESULT := '1';
for K in 1 to N loop
RESULT := RESULT and A(K);
exit when RESULT = '0';
end loop;
Z <= not RESULT after D;
end process;
end NAND_N_D;
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A Generic NAND Gate
Generics--Motivation
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entity TESTBENCH is
end TESTBENCH;
architecture NAND_N_D of TESTBENCH is
signal A, B, C, D, E, T1, T2, Z_OUT: Bit;
component MY_NAND_GATE
generic (N: Natural := 2;
D: Time := 10 ns);
port (A: in Bit_Vector (1 to N);
Z: out Bit);
end component;
for all: MY_NAND_GATE use entity
work.NAND_GATE(NAND_N_D);
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Specification of Generic
Values (2/3)
Specification of Generic
Values (3/3)
component MY_NAND_GATE
generic (N: Natural := 2; D: Time := 10 ns);
port (A: in Bit_Vector (1 to N); Z: out Bit);
end component;
G1: MY_NAND_GATE
port map (A(1) => A, A(2) => B, Z => T1);
Note the lack of a ";"
G2: MY_NAND_GATE
after the generic map!
generic map (3, 15 ns)
port map (A(1) => C, A(2) => D, A(3) => E, Z => T2);
G3: MY_NAND_GATE
generic map (D => 20 ns, N => 2)
port map (A(1) => T1, A(2) => T2, Z => Z_OUT);
Architecture NAND_N_D …
-- architecture declarations
begin
A <= '0', '1' after 50 ns, '0' after 100 ns;
B <= '0', '1' after 50 ns;
C <= '0', '1' after 100 ns, '0' after 150 ns;
D <= '0', '1' after 100 ns;
E <= '0', '1' after 100 ns;
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Notes on generic
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Generic information is static--it can't be
changed during the simulation
Generic value is instance-specific
• Different instances of the same component
can have different values.
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z An
AND gate with parameterized
rise/fall times:
ENTITY and2 IS
GENERIC(rise, fall : TIME; load : INTEGER);
PORT( a, b : IN BIT;
c : OUT BIT);
END AND2;
ARCHITECTURE load_dependent OF and2 IS
SIGNAL internal : BIT;
BEGIN
internal <= a AND b;
c <= internal AFTER (rise + (load * 2 ns)) WHEN internal = '1'
ELSE internal AFTER (fall + (load * 3 ns));
END load_dependent;
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the parameterized AND gate:
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LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY test IS
GENERIC(rise, fall : TIME;
load : INTEGER);
PORT ( ina, inb, inc, ind : IN std_logic;
out1, out2 : OUT std_logic);
END test;
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Keeping track of generic values and which
architectures to use for specific instances can
be difficult, especially for large projects.
• Don't want to be required to edit each architecture
file whenever a different component or value is
desired.
ARCHITECTURE test_arch OF test IS
COMPONENT and2
GENERIC(rise, fall : TIME := 10 NS;
load : INTEGER := 0);
PORT ( a, b : IN std_logic;
c : OUT std_logic);
END COMPONENT;
BEGIN
U1: and2 GENERIC MAP(10 ns, 12 ns, 3) PORT MAP (ina, inb, out1);
U2: and2 PORT MAP (inc, ind, out2 );
END test_arch;
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Specifying all these
generics…
More generic examples
z Using
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More generic examples
• I.e. You can't have the simulation calculate
the value that is going to be passed to the
generic…
• Specified at compile time.
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z
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VHDL provides a method to declare
configurations that specify generics and
component architectures for each instance.
User can then tell the simulator which
configuration to simulate…without having to
edit the architecture or create a new one…
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2
Analogy
Analogy (cont'd)
Printed Circuit Board
Printed Circuit Board
CONFIGURATION
QUAD
NAND
GATE
74HC00
74LS00
BOX OF CHIPS
BOX OF CHIPS
74AS00
54AS00
( unpopulated with chips )
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( unpopulated with chips )
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Configurations
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VHDL Binding
Configurations
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• specify which architectures to use
for a particular component
• specify which parameter values to
use for a particular component
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74HCT00
Definition:
• Associating an architectural
description with a component in a
structural model.
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Two basic forms
Configurations bind all
component declarations
• configuration specifications
• configuration declarations
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Entity
DA
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Arch
DA_2
Arch
DA_3
Entity
DB
Arch
DB_1
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Configure the system
so that ENTITY DA
uses ARCHITECTURE
DA_2,
which instantiates
component DB, which
is bound to
ARCHITECTURE
DB_1
Arch
DB_2
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Configuration
Specification
Choosing a System
Arch
DA_1
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A VHDL construct which helps
associate a particular architecture
with an instantiated component
Simple configuration:
component MYCOMP
port ( ….);
end component;
Library
Architecture
Entity
for U1 : MYCOMP use entity work.MYCOMP(BEHAV);
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3
More Configuration
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Default Mapping Rules
Generic maps and port maps may be
included in the configuration:
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for H1 : HALF_ADDER use entity work.HA(BEHAV);
for H2 : HALF_ADDER use entity
EDSLIB.HALFADD(STRUCT)
generic map (GATEDELAY => 5 ns)
port map (I1=>A, I2=>B, S1=>SUM, C=>CARRY);
A
HA
B
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SUM
I1
CARRY
I2
z
S1
halfadd
z
C
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If the entity name is the same as the
component name, then this entity is
bound to the component
If there are multiple architectures
for the same entity (for example,
DA_1, DA_2,...) the last compiled
architecture for the entity is chosen
Very dangerous to use defaults
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"Boiler Plate"
Configuration
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Example 1/3
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Suppose you have a large system
model, and you want to experiment
with the configuration of a few subcomponents
Procedure:
•
•
•
•
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architecture RISC of CPU is
component ALU
port (....port declaration.... );
end component;
begin
U1: ALU port map ( ....port declaration.... );
end RISC;
Develop system model
Create library for model
Do not bind sub-components in model
Use separate Configuration Declaration
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NOTE:
Component
remains to be
bound.
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for RISC
for U1 : ALU
Perhaps several
architectural
descriptions of
the same entity.
use entity work.ALU(FAST);
end for;
end for;
end MYCONFIG;
architecture FAST of ALU is
begin
......insert body here....
end FAST;
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ALU
configuration MYCONFIG of CPU is
entity ALU is
port ( ....port declaration.... );
end ALU;
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CPU
Example Configuration
Declaration
More of the example:
architecture SMALL of ALU is
begin
......insert body here....
end SMALL;
Example CPU:
entity CPU is
port ( ....port declaration.... );
end CPU;
Example 2/3
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4
Configuration
Declaration Syntax
My test configuration name
configuration MYCONFIG of CPU is
for RISC
Common Errors
Top-level entity which is
being configured
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Name of architecture
being configured
for U1 : ALU
use entity work.ALU(FAST);
Note syntax
end for;
Modifying the model of a
component and forgetting to
reanalyze the component prior
to reuse
Configuration statement
end for;
end MYCONFIG;
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Common Errors
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Generics can have their values defined
in multiple places:
Changing the value in one place may
not have the intended effect due to
precedence
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When using default bindings of
components, the name, type
and mode of each signal in the
component declaration must
exactly match that of the entity
This is dangerous.
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Common Errors
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Common Errors
• within a model
• in a component instantiation (generic map)
• within an architecture in a component
declaration
• within a configuration declaration
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Summary
Inheriting a generic value by way of
default initializations in the
component declaration may lead to
unexpected values.
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Generics
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Configurations
• Parameterize a model
• Specify architectures and
parameters
This is dangerous.
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Next time: Start synthesis
• Reading: pp. 381-392, 439-452.
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