Dynamic Combinational
Circuits
• Dynamic circuits
– Charge sharing, charge redistribution
• Domino logic
• np-CMOS (zipper CMOS)
James Morizio
1
Dynamic Logic
• Dynamic gates use a clocked pMOS pullup
• Two modes: precharge and evaluate
A
2
1
2/3
Y
A
Static
4/3
Y
Pseudo-nMOS
φ
Precharge
φ
1
A
1
Y
Dynamic
Evaluate
Precharge
Y
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2
The Foot
• What if pulldown network is ON during
precharge?
• Use series evaluation transistor to prevent fight.
φ
A
precharge transistor
Y
φ
inputs
Y
f
φ
inputs
Y
f
foot
footed
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unfooted
3
Dynamic Logic
VDD
Φ
Mp
VDD
Φ
Out
CL
In1
In2
In3
PDN
Φ
In1
In2
In3
Me
Φn network
2 phase operation:
Me
PUN
Out
Φ
• Precharge
Mp
CL
Φp network
• Evaluation
James Morizio
4
Logical Effort
Inverter
unfooted
footed
φ
1
A
1
φ
1
A
2
2
NAND2
Y
gd
pd
= 1/3
= 2/3
Y
gd
pd
= 2/3
= 3/3
φ
1
A
2
B
2
φ
1
A
3
B
3
3
NOR2
Y
gd
pd
= 2/3
= 3/3
A
Y
φ
1
1
B
φ
gd
pd
James Morizio
= 3/3
= 4/3
A
1
1
2
B
2
2
Y
gd
pd
= 1/3
= 3/3
Y
gd
pd
= 2/3
= 5/3
5
Dynamic Logic
• N+2 transistors for N-input function
– Better than 2N transistors for complementary static CMOS
– Comparable to N+1 for ratio-ed logic
• No static power dissipation
– Better than ratio-ed logic
• Careful design, clock signal Φ needed
James Morizio
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Dynamic Logic: Principles
VDD
Φ
Mp
• Precharge
Out
CL
In1
In2
In3
PDN
Φ
Me
Φ = 0, Out is precharged to VDD by Mp.
Me is turned off, no dc current flows
(regardless of input values)
• Evaluation
Φ = 1, Me is turned on, Mp is turned off.
Output is pulled down to zero depending
on the values on the inputs. If not,
precharged value remains on CL.
Important: Once Out is discharged, it cannot be charged again!
Gate input can make only one transition during evaluation
• Minimum clock frequency must be maintained
• Can Me be eliminated?
James Morizio
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Example
VDD
Mp
Φ
Out
• Ratio le s s
• No Static Po we r Cons umptio n
A
C
B
Φ
• Nois e Marg ins s mall (NML)
• Requires Cloc k
Me
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Dynamic 4 Input NAND Gate
φ
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Cascading Dynamic Gates
VDD
Mp
Φ
VDD
Φ
Mp
Out2
Out1
V
Φ
In
Out1
In
VTn
Out2
Φ
Me
Φ
Me
t
Internal nodes can only make 0-1 transitions during evaluation period
James Morizio
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Monotonicity
• Dynamic gates require monotonically rising inputs
during evaluation
φ
–
–
–
–
0 -> 0
0 -> 1
1 -> 1
But not 1 -> 0
A
violates monotonicity
during evaluation
A
φ
Precharge
Evaluate
Precharge
Y
Output should rise but does not
James Morizio
11
Monotonicity Woes
• But dynamic gates produce monotonically falling
outputs during evaluation
• Illegal for one dynamic gate to drive another!
A=1
φ
A
X
Y
φ
Precharge
Evaluate
Precharge
X
X monotonically falls during evaluation
Y
Y should rise but cannot
James Morizio
12
Reliability Problems — Charge Leakage
VDD
Φ
Φ
Mp
Out
(1)
A
CL
t
Vout
(2)
precharge
evaluate
A=0
Φ
Me
(a) Leakage sources
(b) Effect on waveforms
t
(1) Leakage through reverse-biased diode of the diffusion area
(2) Subthreshold current from drain to source
Minimum Clock Frequenc y: > 1 MHz
James Morizio
13
Leakage
• Dynamic node floats high during evaluation
– Transistors are leaky (IOFF ≠ 0)
– Dynamic value will leak away over time
– Formerly miliseconds, now nanoseconds!
• Use keeper to hold dynamic node
– Must be weak enough not to fight evaluation
weak keeper
φ
A
1 k
2
X
H
Y
2
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Charge Sharing (redistribution)
VDD
• Assume: during precharge, A and B are 0, Ca is discharged
• During evaluation, B remains 0 and A rises to 1
• Charge stored on CL is now redistributed over CL and Ca
Mp
Out
A
CL
Ma
X
B=0
Mb
Me
Ca
Cb
CLVDD = CL Vout(t) + CaVX
VX = VDD - Vt, therefore
δVout(t) = Vout(t) - VDD =
Ca
(VDD-Vt)
CL
Desirable to keep the voltage drop below threshold
of pMOS transistor (why?) Ca/CL < 0.2
James Morizio
15
Charge Sharing
• Dynamic gates suffer from charge sharing
φ
φ
A
B=0
Y
CY
x
Cx
A
Y
Charge sharing noise
x
CY
Vx = VY =
VDD
C x + CY
James Morizio
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Charge Redistribution - Solutions
VDD
VDD
Mp
Φ
Mbl
Mp
Φ
Φ
Out
Out
A
Ma
A
Ma
B
Mb
B
Mb
Φ
Me
(a) Static bleeder
Mbl
Φ
Me
(b) Precharge of internal nodes
James Morizio
17
Secondary Precharge
• Solution: add secondary precharge transistors
– Typically need to precharge every other node
• Big load capacitance CY helps as well
φ
Y
A
x
secondary
precharge
transistor
B
James Morizio
18
Domino Logic
VDD
Φ
Mp
VDD
Φ
Out1
Mp
VDD
Mr
Out2
In1
In2
In3
PDN
Φ
Me
PDN
In4
Φ
Static Inverter
with Level Restorer
Me
Static inverters
between dynamic stages
James Morizio
19
Domino Gates
• Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs
φ
domino AND
W
Precharge
Evaluate
Precharge
W
X
Y
Z
X
A
B
C
φ
Y
Z
dynamic static
NAND inverter
φ
A
B
φ
φ
W
H
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X
C
Y
H
Z
=
A
B
φ
X
Z
C
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Domino Logic - Characteristics
• Only non-inverting logic
• Very fast - Only 1->0 transitions at input of inverter
• Precharging makes pull-up very fast
• Adding level restorer reduces leakage and
charge redistribution problems
• Optimize inverter for fan-out
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Domino Optimizations
• Each domino gate triggers next one, like a string of
dominos toppling over
• Gates evaluate sequentially but precharge in parallel
• Thus evaluation is more critical than precharge
• HI-skewed static stages can perform logic
φ
S0
S1
S2
S3
D0
D1
D2
D3
H
Y
φ
S4
S5
S6
S7
D4
D5
D6
D7
James Morizio
22
Dual-Rail Domino
• Domino only performs noninverting functions:
– AND, OR but not NAND, NOR, or XOR
• Dual-rail domino solves this problem
– Takes true and complementary inputs
– Produces true and complementary outputs
sig_h
sig_l
Meaning
0
0
Precharged
0
1
‘0’
1
0
‘1’
1
1
invalid
Y_l
Y_h
φ
inputs
f
f
φ
James Morizio
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Example: AND/NAND
• Given A_h, A_l, B_h, B_l
• Compute Y_h = A * B, Y_l = ~(A * B)
• Pulldown networks are conduction complements
Y_l
φ
= A*B
A_l
B_l
A_h
Y_h
= A*B
B_h
φ
James Morizio
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Example: XOR/XNOR
• Sometimes possible to share transistors
Y_l
= A xnor B
A_h
φ
A_l
B_l
Y_h
A_l
A_h
= A xor B
B_h
φ
James Morizio
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Domino Summary
• Domino logic is attractive for high-speed circuits
– 1.5 – 2x faster than static CMOS
– But many challenges:
• Monotonicity
• Leakage
• Charge sharing
• Noise
• Widely used in high-performance microprocessors
James Morizio
26
np-CMOS (Zipper CMOS)
VDD
Mp
Φ
In1
In2
In3
PDN
VDD
Φ
Out1
Me
PUN
In4
Out2
Φ
Me
Φ
Mp
• Only 1-0 transitions allowed at inputs of PUN
• Used a lot in the Alpha design
James Morizio
27
np CMOS Adder
VDD
φ
A1
VD D
VDD
φ
φ
B1
B1
A1
A1
φ
φ
B1
A0
B0
B0
Ci1
A0
B0
φ
Ci0
A1
B1
φ
φ
φ
φ
Ci1
VDD
φ
S1
Ci1
VDD
A0
φ
φ
Ci2
VD D
Ci0
VDD
φ
B0
A0
Ci0
S0
Carry Path
James Morizio
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CMOS Circuit Styles - Summary
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