COMP 103
Lecture 07
Pass Transistor Logic
[All lecture notes are adapted from Mary Jane Irwin, Penn State, which were adapted from Rabaey’s Digital Integrated
Circuits, ©2002, J. Rabaey et al.]
Comp103-L7.1
Review: Static Complementary CMOS
‰
High noise margins
z
VDD
…
In1
In2
Low output impedance, high
input impedance
‰
No static power consumption
F(In1,In2,…InN)
…
In1
In2
InN
‰
PUN
InN
PDN
PUN and PDN are dual logic networks
Comp103-L7.2
VOH and VOL are at VDD and
GND, respectively
z
Never a direct path between
VDD and GND in steady state
Delay a function of load
capacitance and transistor on
resistance
‰ Comparable rise and fall
times (under the appropriate
relative transistor sizing
conditions)
‰
NMOS Transistors in Series/Parallel
‰
Primary inputs drive both gate and source/drain
terminals
‰
NMOS switch closes when the gate input is high
A
B
X
Y
X = Y if A and B
A
‰
X = Y if A or B
B
X
Y
Remember - NMOS transistors pass a strong 0 but a
weak 1
Comp103-L7.3
PMOS Transistors in Series/Parallel
‰
Primary inputs drive both gate and source/drain
terminals
‰
PMOS switch closes when the gate input is low
A
B
X
Y
X = Y if A and B = A + B
A
X
‰
B
X = Y if A or B = A • B
Y
Remember - PMOS transistors pass a strong 1 but a
weak 0
Comp103-L7.4
Pass Transistor (PT) Logic
B
A
B
F=
0
Gate is static – a low-impedance path exists to both
supply rails under all circumstances
‰ N transistors instead of 2N
‰ No static power consumption
‰ Ratioless
‰ Bidirectional (versus undirectional)
‰
Comp103-L7.5
VTC of PT AND Gate
B
1.5/0.25
Vout, V
2
0.5/0.25
A
B=VDD, A=0→VDD
1
0.5/0.25
B
0
0.5/0.25
z
Comp103-L7.6
A=VDD, B=0→VDD
A=B=0→VDD
F= A•B
0
0
1
Vin, V
2
Pure PT logic is not regenerative - the signal
gradually degrades after passing through a number
of PTs (can fix with static CMOS inverter insertion)
Differential PT Logic (CPL)
B
A
A
B
B
PT Network
A
A
B
B
Inverse PT
Network
B
B
F
F=AB
B
B
F=AB
B
AND/NAND
B
A
F=A+B
B
A
F=A⊕B
A
A
A
F
B
A
A
F
F
F=A+B
B
F=A⊕B
A
OR/NOR
XOR/XNOR
Comp103-L7.7
CPL Properties
‰
Differential so complementary data inputs and outputs
are always available (so don’t need extra inverters)
‰
Still static, since the output defining nodes are always
tied to VDD or GND through a low resistance path
‰
Design is modular; all gates use the same topology, only
the inputs are permuted.
‰
Simple XOR makes it attractive for structures like adders
‰
Fast (assuming number of transistors in series is small)
‰
Additional routing overhead for complementary signals
‰
Still have static power dissipation problems
Comp103-L7.8
CPL Full Adder
B
Cin
B
Cin
A
!Sum
A
Sum
B
B
Cin
Cin
A
!Cout
B
Cin
A
Cout
B
Cin
Comp103-L7.9
NMOS Only PT Driving an Inverter
In = VDD
A = VDD
VGS
D
Vx =
VDD-VTn
M2
S
B
M1
‰
Vx does not pull up to VDD, but VDD – VTn
‰
Threshold voltage drop causes static power
consumption (M2 may be weakly conducting forming a
path from VDD to GND)
‰
Notice VTn increases of pass transistor due to body
effect (VSB)
Comp103-L7.10
Voltage Swing of PT Driving an Inverter
3
In
In = 0 → VDD
1.5/0.25
2
Out
0.5/0.25
0.5/0.25
B
Voltage, V
S
D
VDD
x
x = 1.8V
1
Out
0
0
0.5
1
1.5
2
Time, ns
‰
Body effect – large VSB at x - when pulling high (B is
tied to GND and S charged up close to VDD)
‰
So the voltage drop is even worse
Vx = VDD - (VTn0 + γ(√(|2φf| + Vx) - √|2φf|))
Comp103-L7.11
Cascaded NMOS Only PTs
B = VDD
B = VDD C = VDD
G
M1
A = VDD
S
C = VDD
x = VDD - VTn1
z
M1
x
M2
y
Out
G
y
M2
Out
S
Swing on y = VDD - VTn1 - VTn2
z
A = VDD
Swing on y = VDD - VTn1
Pass transistor gates should never be cascaded as on
the left
Logic on the right suffers from static power dissipation
and reduced noise margins
Comp103-L7.12
Solution 1: Level Restorer
Level Restorer
on
Mr
off
B
A=1
A=0
Mn
M2
x= 0
1
Out=0
Out =1
M1
‰
Full swing on x (due to Level Restorer) so no static
power consumption by inverter
‰
No static backward current path through Level Restorer
and PT since Restorer is only active when A is high
‰
For correct operation Mr must be sized correctly (ratioed)
Comp103-L7.13
Transient Level Restorer Circuit Response
3
W/L2=1.50/0.25
W/Ln=0.50/0.25
W/L1=0.50/0.25
Voltage, V
2
W/Lr=1.75/0.25
node x never goes below VM
of inverter so output never
switches
W/Lr=1.50/0.25
1
W/Lr=1.25/0.25
W/Lr=1.0/0.25
0
0
‰
100
200
Time, ps
300
400
500
Restorer has speed and power impacts: increases the
capacitance at x, slowing down the gate; increases tr (but
decreases tf)
Comp103-L7.14
Solution 2: Multiple VT Transistors
‰
Technology solution: Use (near) zero VT devices for the
NMOS PTs to eliminate most of the threshold drop (body
effect still in force preventing full swing to VDD)
low VT transistors
In2 = 0V
A = 2.5V
on
Out
off but
leaking
B = 0V
In1 = 2.5V
sneak path
‰
Impacts static power consumption due to subthreshold
currents flowing through the PTs (even if VGS is below VT)
Comp103-L7.15
Solution 3: Transmission Gates (TGs)
‰
Most widely used
solution
C
C
A
A
B
B
C
C
C = GND
A = VDD
B
C = VDD
‰
C = GND
A = GND
B
C = VDD
Full swing bidirectional switch controlled by the gate
signal C, A = B if C = 1
Comp103-L7.16
Resistance of TG
W/Lp=0.50/0.25
30
0V
25
Rn
Rp
Resistance, kΩ
20
2.5V
Vout
Rp
Rn
15
2.5V
10
Req
W/Ln=0.50/0.25
5
0
0
1
2
Vout, V
Comp103-L7.17
TG Multiplexer
S
S
S
S
F
S
VDD
In2
S
F
In1
S
F = !(In1 • S + In2 • S)
GND
In1
Comp103-L7.18
In2
Transmission Gate XOR
A
A⊕B
B
Comp103-L7.19
TG Full Adder
Cin
B
A
Sum
Cout
Comp103-L7.20
Differential TG Logic (DPL)
B
A
B
B
A
B
A
A
A
F=AB
GND
B
F=A⊕B
A
B
B
GND
A
VDD
A
F=AB
B
F=A⊕B
A
VDD
B
B
AND/NAND
Comp103-L7.21
A
XOR/XNOR