Combinatorial and Sequential Logic
ROCHESTER INSTITUTE OF TECHNOLOGY
MICROELECTRONIC ENGINEERING
Combinatorial and Sequential CMOS
Circuits
Dr. Lynn Fuller
Webpage: http://people.rit.edu/lffeee
Microelectronic Engineering
Rochester Institute of Technology
82 Lomb Memorial Drive
Rochester, NY 14623-5604
Tel (585) 475-2035
Email: Lynn.Fuller@rit.edu
Department webpage: http://www.microe.rit.edu
Rochester Institute of Technology
Microelectronic Engineering
10-30-2015 Combinational_Sequential_Circuits.ppt
© October 30, 2015
Dr. Lynn Fuller
Page 1
Combinatorial and Sequential Logic
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Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
OUTLINE
Inntroduction
VTC of NAND and NOR
CMOS AND-OR-INVERT Gate
XOR and XNOR
Encoder, Decoder, Multiplexer, Demultiplexer
Set-Reset Latch
Flip-Flop
Power Dissipation
Energy and Delay
References
Homework
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 3
Combinatorial and Sequential Logic
INTRODUCTION
In this module we want to look at combining transistors to make
CMOS logic gates. In general we want the logic gate to function
correctly for static operation, we want the noise margin to be similar
to that of the CMOS inverter and the speed at which the gate
operates to be similar to that of the CMOS inverter.
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
CMOS INVERTER DESIGN
The design guideline is that the inverter should have the same current
drive when Vout is switching low to high as high to low. Because the
mobility of electrons is ~1.5 times higher than mobility for holes we
make the PMOS 1.5 times wider. Typically L’s are the same.
(W/L)pullup = ~ 1.5 (W/L)pulldown based on mobility only
Vin
Vout
Pull up
1.5µW/L
ID = µW Cox’ (Vg-Vt)2
2L
+V
I low to high
Vout
Vin
C Load
Pull down
µW/L
Rochester Institute of Technology
Microelectronic Engineering
CMOS
© October 30, 2015
Dr. Lynn Fuller
Page 5
Combinatorial and Sequential Logic
CMOS NOR AND NAND
The design guideline for other logic gates is to provide the same current drive as the inverter.
For the NOR gate we can go from high to low by starting with both inputs at zero and then
making either input high or both high. The worst case condition is making only one input
high. For that condition we want the same current drive as the inverter. Thus the width of the
NMOS should be W. If both the inputs were switching high at the same time the current
would be twice as much (that’s okay) For a low to high transition the current goes through
two PMOS in series. The equivalent L for the series combination is 2L. If the width for each
transistor was 3W the combined value is 3W/2L which is 1.5W/L as desired for equal drive
current as the inverter.
VA VB NOR NAND
VA
VB
Vout +V
3W
0
0
1
1
0
1
0
1
1
0
0
0
1
1
1
0
VA
VB
+V
1.5W
1.5W
3W
NOR
VA
WRochester Institute of W
Technology
VB
VAMicroelectronic Engineering
© October 30, 2015
2W
VB
2W
Dr. Lynn Fuller
NAND
Page 6
Vout
Combinatorial and Sequential Logic
VTC FOR CMOS NOR AND NAND
Vout1
Vout2
Vout3
Vout4
NMOS
L=2u
W=2u
Vout1 PMOS L=2u, W=3u, VA Sweep 0 to 5, VB=zero
Vout2 PMOS L=2u, W=3u, VA Sweep 0 to 5, VB=VA
Rochester Institute of Technology
Vout3
PMOS
L=2u, W=2u, VA Sweep 0 to 5, VB=zero
Microelectronic
Engineering
Vout4 PMOS L=2u, W=2u, VA Sweep 0 to 5, VB=VA
© October 30, 2015
Dr. Lynn Fuller
Page 7
Combinatorial and Sequential Logic
VTC FOR 3-INPUT NAND
The three NMOS transistors each have different source to substrate
voltages which will change the threshold voltage of those transistors
and as a result will change the VTC depending on which transistors
are switching. This causes a horizontal shift in the VTC.
VA
VB
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
+V
VC NAND
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
0
VA
VB
VOUT
NAND
VOUT
VA
M1
VB
M2
VC
M3
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
SIZING AND TIMING FOR THREE-INPUT NAND
To achieve equal rise time and fall time (and make these times
approximately equal to the simple inverter rise time and fall time).
The transistors length and width can be calculated. In the simple
inverter the nmos W/L is the smallest values for that technology.
The pmos is 1.5 times wider to give equal drive current. For a more
complex gate there will be transistors in series and parallel and those
combinations need to be considered when trying to achieve rise and
fall times equivalent to the simple inverter. For example:
+V
M1, M2 and M3 have a combined length of 3L
So the combined width should be 3W to give 1.5W/L
drive current equivalent to the nmos in the
simple inverter. M1,M2,M3 nmos = 3W/L
The worst case condition for low to high
transition is only one input going low. So the
width of the PMOS should be 1.5W. (when
two or moreRochester
inputs
are
going low at the same
Institute
of Technology
Microelectronic Engineering
time there will be more current (that is okay)
© October 30, 2015
Dr. Lynn Fuller
VA
1.5W/L
1.5W/L
VOUT
M1 3W/L
VB
M2
3W/L
VC
M3
3W/L
Page 9
Combinatorial and Sequential Logic
3-INPUT NAND
Vout2
Vout1
+V
VA
VOUT
M1
VB
M2
M3
VC
Vout1 has M2 and M3 NMOS on and M1 NMOS switching
Rochesterand
InstituteM2
of Technology
Vout2 has M1
NMOS on and M3 NMOS switching
Microelectronic Engineering
Other combinations are also possible.
© October 30, 2015
Dr. Lynn Fuller
Page 10
Combinatorial and Sequential Logic
FAN IN AND FAN OUT CONSIDERATIONS
Fan in refers to the number of inputs to a gate. It is common to have
up to 8 inputs. In CMOS this implies that there are 8 transistors in
parallel and 8 transistors in series. The 8 in parallel is not necessarily
a problem but the 8 in series is because of the body effect on the
threshold voltage of some of the transistors if they are all in the same
well (at Vss or Vdd for p-well or n-well respectively)
Fan-In = 6
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
FAN OUT CONSIDERATIONS
Fan out refers to the number of gates connected to the output of a
gate. Each gate adds more capacitance to be charged or discharged
during switching which has implications on rise time, fall time and
gate delay. The size (W and L) of the MOSFETS can be made to keep
the gate delay small.
Fan-Out = 6
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
PSEUDO – CMOS
There are situations where we want a large number of inputs. Rather
than have CMOS where there will be many transistors in series
(which will not work) we can use a single PMOS/NMOS transistor
that is always on.
+V
+V
Idd
Idd
VIN
CMOS
VA
Pseudo CMOS
Inverter
VB
VC
Pseudo CMOS
4 Input NOR
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Idd
VO
VO
VO
VIN
+V
Dr. Lynn Fuller
Page 13
VD
Combinatorial and Sequential Logic
OTHER BASIC LOGIC GATES
AND
VA
VB
3 INPUT AND
OR
VOUT
VA
VOUT
VA
VB
VC
VOUT
3 INPUT OR
VA
VB
VC
VOUT
VB
VA VB VOUT VA VB VOUT VA VB VC VOUT VA VB VC VOUT
0 0 0
0
0
0
0
0
0
0
0 0 0
0
0 0 1
0
0
1
0
0
1
1
0 0 1
1
0 1 0
0
1
0
0
1
0
1
0 1 0
1
0 1 1
0
1
1
1
1
1
1
0 1 1
1
1 0 0
0
1 0 0
1
1 0 1
0
1 0 1
1
1 1 0
0
1 1 0
1
1 1 1
1
1 1 1
1
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
OTHER BASIC LOGIC GATE REALIZATIONS
Enhancement Load
V++ Gate Enhancement Load
Depletion Load
Pseudo CMOS NAND, NOR
CMOS AND-OR-INVERT Gate
Generalized Complex CMOS Gate
More Complex Gates, XOR, MUX,
Encoder, Decoder, etc.
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
CMOS AND-OR-INVERT GATE
+V
VOUT = (VA VB)+VC
VA
VC
VB
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
GENERALIZED COMPLEX GATE
+V
A
B
C
.
.
F = (VA+VB) VC
A
B
C
.
.
Design a gate that
provides this output
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
EXCLUSIVE OR (XOR) DESIGN EXAMPLE
Functional Description – This digital logic circuit returns a true
(high) value when one of two inputs is high and returns a false
(zero) otherwise.
Exclusive OR VA VB VOUT
Truth Table
XOR
0
0
0
0
1
1
1
0
1
1
1
0
Gate Level Design
COUT
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Microelectronic Engineering
A
© October 30, 2015
B
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
GATE LEVEL SIMULATION OF XOR – AND/OR
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
NOR CIRCUIT REALIZATION FOR XOR
Exclusive OR VA VB VOUT
XOR
0
0
0
OUT
0
1
1
A B
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 20
1
0
1
1
1
0
Combinatorial and Sequential Logic
GATE LEVEL SIMULATION OF XOR – ALL/NOR
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 21
Combinatorial and Sequential Logic
TRANSISTOR LEVEL SIMULATION OF XOR – ALL/NOR
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
BASIC CELL XOR
Input A
Port in
A’
A’B
XOR
B
Port out
Input B
Port in
XOR = A’B+AB’
A
AB’
B’
XOR
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
LAYOUT FOR XOR
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
BASIC DIGITAL CELLS WITH PADS
Decoder
Multiplexer
XOR
Full Adder
Encoder
Decoder
JK FF
Edge Triggered D FF
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Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 25
Demux
Combinatorial and Sequential Logic
4 TO 1 MULTIPLEXER
I0
A
I1
Q
I2
B
I3
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
4 TO 1 MUX - GATE LEVEL SIMULATION
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
ADDITION IN BINARY
IN BASE 10
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
7
+2
___
9
IN BINARY
11
0111
0010
___
1001
CARRY
SUM
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
TRUTH TABLE
FOR ADDITION
RULES
A
B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
CIN SUM COUT
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
AND-OR CIRCUIT REALIZATION OF SUM
TRUTH TABLE
FOR ADDITION
RULES
A
SUM
A
B
B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
CIN SUM COUT
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
Cin
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
CIRCUIT REALIZATION OF CARRY OUT (COUT)
TRUTH TABLE
FOR ADDITION
RULES
A
COUT
A
B
B
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
CIN SUM COUT
0
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
1
Cin
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
FULL ADDER
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 31
Combinatorial and Sequential Logic
1 TO 4 DEMULTIPLEXER
Q0
A
I
Q1
Q2
B
Q3
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
DECODER
A
Q0
Q1
B
Q2
Q3
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 33
Combinatorial and Sequential Logic
ENCODER
Q0
Q1
Q2
ABCD
1 0 0 0
0 1 0 0
0 0 1 0
0 0 0 1
Coded
Output
Lines
Qn
Digital Encoder
512 inputs can be coded into 9 lines
which is a more dramatic benefit
A
B
C
D
Q1
Q2
No Connection
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 34
Q0 Q1
0 0
0 1
1 0
1 1
Combinatorial and Sequential Logic
FILP-FLOPS
R
Q
S
QBAR
R
0
0
1
1
RS FLIP FLOP
S
0
1
0
1
Q
Qn-1
1
0
INDETERMINATE
D FLIP FLOP
Q
DATA
CLOCK
QBAR
Q=DATA IF CLOCK IS HIGH
IF CLOCK IS LOW Q=PREVIOUS DATA VALUE
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
MASTER-SLAVE D FLIP FLOP
Q
DATA
CLOCK
QBAR
NEGATED INPUT NOR IS EQUAL TO AND
A
OUT
A
A
=
B
B
B
A B OUT OUT
A
B
1
0
0
0
1 1
1
0
0
1
1 0
1
0
1
0
0 1
0
1
1
1
0 0
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
ALL NOR MASTER SLAVE D FLIP FLOP
Q
DATA
CLOCK
DATA
Q
CLOCK
Rochester Institute of Technology
Microelectronic Engineering
ALL NOR NMOS REALIZATION
ALLOWS FOR LOWER SUPPLY VOLTAGE
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
CMOS CLOCKED DATA LATCH USING AND-OR-INV
D
_
Q
CLK
Q
VDD
Q
CLK
CLK
_
D
_
Q
D
VDD
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
EDGE TRIGGERED D TYPE FLIP FLOP
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 39
Combinatorial and Sequential Logic
JK FLIP FLOP
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 40
Combinatorial and Sequential Logic
T-TYPE FILP-FLOP
TOGGEL FLIP FLOP
Q
T
QBAR
Q: Toggles High and Low with Each Input
T
Qn-1
Q
0
0
1
1
0
1
0
1
0
1
1
0
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
BINARY COUNTER USING T TYPE FLIP FLOPS
State Table for Binary Counter
A
Present
State
TA
A
A
0
0
0
0
1
1
1
1
B
TB
B
C
Input
Pulses
Tc
C
B C
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Next
State
A
B
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
A
Qn-1
Q
0
0
0
0
1
1
1
0
1
1
1
0
TOGGEL FLIP FLOP
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
C
1
0
1
0
1
0
1
0
0
0
0
1
0
0
0
1
0
1
0
1
0
1
0
1
A
A
0
1
0
00 1
1
01 1
1
01 1
1
1
11 1
1
11 1
1
0
10 0
0
10 1
1
1
00 0
0
00 0
01 0
0
11 1
10 0
BC
TA
Dr. Lynn Fuller
1
1
1
1
1
1
1
1
0
BC
T
F-F
Inputs
TA TB TC
Page 42
0
1 BC
TB
TC
Combinatorial and Sequential Logic
3-BIT BINARY COUNTER WITH D FLIP FLOPS
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 43
Combinatorial and Sequential Logic
INVERTER WITH HYSTERESIS
1
R=100K
3
+
-
Vout
M2
Inverter with Hysteresis
M3
V1
5V
7
2
V2=0-5
Or 5-0
Vout
+
-
M1
Vin
The voltage on node 7 is different depending on if Vout is high or low.
Rochester Institute of Technology
Changing
the Voltage
Microelectronic
Engineering from source to substrate which changes the
threshold voltage of M2
© October 30, 2015
Dr. Lynn Fuller
Page 44
Combinatorial and Sequential Logic
INVERTER WITH HYSTERESIS
SPICE shows inverter has hysteresis
Rochester Institute of Technology
Microelectronic Engineering
(Flip Blue output about the y-axis and superimpose on Red-Green Plot)
© October 30, 2015
Dr. Lynn Fuller
Page 45
Combinatorial and Sequential Logic
RC OSCILLATOR USING INVERTER WITH HYSTERESIS
R
Vout
C
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
RC Oscillator
Dr. Lynn Fuller
Page 46
Combinatorial and Sequential Logic
BUFFERS
R
Vout
Vout’
C
RC Oscillator
Buffers
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 47
Combinatorial and Sequential Logic
CMOS INVERTER WITH HYSTERESIS
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
SPICE show this inverter
has hysteresis
Dr. Lynn Fuller
Page 48
Combinatorial and Sequential Logic
OSCILLATOR CMOS INVERTER WITH HYSTERESIS
R
Vout
Rochester Institute of Technology
Microelectronic Engineering
C
RC Oscillator
© October 30, 2015
Dr. Lynn Fuller
Page 49
Combinatorial and Sequential Logic
REFERNCES
1. Hodges Jackson and Saleh, Analysis and Design of Digital
Integrated Circuits, Chapter 4.
2. Sedra and Smith, Microelectronic Circuits, Sixth Edition,
Chapter 13.
3. Dr. Fuller’s Lecture Notes, http://people.rit.edu/lffeee
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 50
Combinatorial and Sequential Logic
HOMEWORK – LOGIC
1. Design a pseudo CMOS NAND gate. Use 1um technology.
Show it will work using SPICE.
2. Look up the data sheet for the MM74C14 CMOS inverter with
hystersis. Design a 10 Khz oscillator.
3. Use SPICE (transistor level) to simulate the 1 to 4
Demultiplexer.
4. Use SPICE (transistor level) to simulate the positive edge
triggered D-type Flip-Flop.
5. Use SPICE to simulate a CMOS RC Oscillator with Buffers.
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
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Combinatorial and Sequential Logic
SPICE MODELS FOR CD4007 MOSFETS
*SPICE MODELS FOR RIT DEVICES - DR. LYNN FULLER 8-7-2015
*LOCATION DR.FULLER'S WEBPAGE - http://people.rit.edu/lffeee/CMOS.htm
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.1 NRS=0.1
.MODEL RIT4007N7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8
+VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*Used in Electronics II for CD4007 inverter chip
*Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.54 NRD=0.54
.MODEL RIT4007P7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8
+VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94
Rochester
Institute of Technology
+CJSW=1.19E-10
MJSW=0.5
PBSW=0.94 pCLM=5
Microelectronic Engineering
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
© October 30, 2015
Dr. Lynn Fuller
Page 52
Combinatorial and Sequential Logic
SPICE MODELS FOR MOSFETS
* From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology
.MODEL RITSUBN7 NMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=1.84E-7 NCH=1.45E17 NSUB=5.33E16 XT=8.66E-8
+VTH0=1.0 U0= 600 WINT=2.0E-7 LINT=1E-7
+NGATE=5E20 RSH=1082 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*From Sub-Micron CMOS Manufacturing Classes in MicroE ~ 1um Technology
.MODEL RITSUBP7 PMOS (LEVEL=7
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=1.5E-8 XJ=2.26E-7 NCH=7.12E16 NSUB=3.16E16 XT=8.66E-8
+VTH0=-1.0 U0= 376.72 WINT=2.0E-7 LINT=2.26E-7
+NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 53
Combinatorial and Sequential Logic
SPICE MODELS FOR MOSFETS
*4-4-2013 LTSPICE uses Level=8
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSN NMOS (LEVEL=8
+VERSION=3.1 CAPMOD=2 MOBMOD=1
+TOX=5E-9 XJ=1.84E-7 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=0.4 U0= 200 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-4 MJ=0.5 PB=0.95
+CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5
+CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10)
*
*4-4-2013 LTSPICE uses Level=8
* From Electronics II EEEE482 FOR ~100nm Technology
.model EECMOSP PMOS (LEVEL=8
+TOX=5E-9 XJ=0.05E-6 NCH=1E17 NSUB=5E16 XT=5E-8
+VTH0=-0.4 U0= 100 WINT=1E-8 LINT=1E-8
+NGATE=5E20 RSH=1000 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-4 MJ=0.5 PB=0.94
+CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5
+CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10)
*
Rochester Institute of Technology
Microelectronic Engineering
© October 30, 2015
Dr. Lynn Fuller
Page 54