Spring 2004
CSE45401 VLSI Design Lab
Lab #4 – Design of CMOS XOR/XNOR Gates
(One lab session)
Introduction
Exclusive-OR (XOR) and Exclusive-NOR (XNOR) gates find wide applications in
arithmetic circuits and error correcting codes. They have been found to have compact
representations compared to AND/OR or NAND/NOR based circuits.
In this laboratory you will first design an XOR/XNOR gate using pass logic design
approaches, and then design the layout for the cell in standard cell format using the
Tanner Research Standard Cell Library. Then a timing analysis of the gate is to be done
using Spice simulation. Finally, the new cell that you designed has to be added to the
standard cell library that you created in Lab #3.
Procedure
You will be designing only one of the cells – XOR or XNOR. The cell assigned to
you is listed against your name at the end of this handout.
There are three parts to your design.
1. XOR/XNOR gate transistor schematics
This starts with a k-map. The gate has two inputs A and B and one output Z. Use pass
logic design approaches and design your gate so that the gate produces good 0’s and 1’s
at the output. If you need complementary variables they need to be generated using
inverters inside your cell. Take special attention to minimize the number of transistors in
your design. The articles listed at the end of this handout are good references for this
topic.
The transistor schematics for your cell must be completed before you start your lab
session and must be recorded in your lab notebook. Please get the lab instructor’s
approval before you start your L-edit layout.
2. Stick layout
A good starting point before you start any layout design is to draw a stick diagram for the
cell. A stick diagram will help you to optimize your design in terms of layout area. It is a
fast way to identify wire crossings in your layout and to come up with a good
transistor/interconnect strategy for your layout. Perfecting a stick diagram is an iterative
process, each time modifying your stick diagram to reduce the number of
crossings/layout area. Contacts normally occupy more area and hence you must try to
minimize them as much as possible at this stage.
SUNY at New Paltz
Spring 2004
3. Layout design
A first step in this procedure is to make a complete layout in a graph paper. The perfected
stick diagram can be used as a design guide at this stage. The manual layout need not be
drawn to exact dimensions, but must try to follow all design rules. By preparing a good
manual layout before your lab session, you will be able to utilize your lab time in a more
productive manner.
Hints: Assume that the cell inputs and the output are routed vertically in Metal2. In your
design, use pMOS transistors equal to twice the size of your nMOS transistors. This will
help you with your later lab sessions, where you will be using the XOR/XNOR gates
designed in this lab to build more complex cells (adder cells).
Once you have your manual layout ready, draw it using L-edit. Follow the procedure laid
out in Lab # 2 to complete your layout. Use the cell name “ABCXOR” or “ABCXNOR”,
where ABC may be replaced with your initials. Check the design rules frequently during
the layout, and also save your design.
Once you have a completed XOR/XNOR cell with all design rules satisfied, the next step
is to verify its functionality using Spice simulation. To do this you need to do a circuit
extraction and then insert additional statements for voltage sources and transistor models.
Use a load capacitance of around 200fF. From now on, while doing simulation, all
input waveforms must be fed through inverters (use your standard cell inverter).
This is a good practice followed in industry since the inputs to a cell seldom come from a
waveform generator. The input waveforms have to be carefully defined to verify the
functionality of the circuit. Always try to avoid simultaneous switching of the inputs, and
also space the input edges far apart so that you don’t get into high frequency switching of
the cell. During your Spice simulation, measure the propagation delay (tPHL and tPLH) and
the rise and fall times of the output waveform and record all your readings for later use.
Also, measure the power dissipation of the cell. The majority of power dissipation is due
to the charging and discharging of the capacitances (dynamic power) at different nodes in
2
the circuit. The dynamic power dissipation is given by the formula: P = ∑ CiVDD
fi , where
i
Ci is the node capacitance and fi is the switching frequency at the node. You may
compare the calculated value of power with the simulation results.
Your lab notebook must contain all details (XOR/XNOR gate design, transistor
schematics, stick diagram, manual layout etc). In addition to the above, you should have
the following documents:
1.
2.
3.
4.
5.
A printout of the L-edit layout for your cell
.SPC files extracted from L-edit
.CIR files used for Pspice simulation
Properly labeled Spice output waveforms illustrating the functionality of the gate
Pspice waveforms showing the supply current, rise time, fall time, and
propagation delay.
At the completion of the lab get the signature of the lab instructor.
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Spring 2004
4. References
[1] Low voltage CMOS full adder cells
[2] A Structured Approach for Designing Low Power Adders
[3] A Novel Efficient Design of XOR/XNOR function for Adder Applications
[4] New 4-Transistor XOR and XNOR Designs
Cell Assignments
No
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Student Name
Cell Assigned
Asad Ahmed
Davis Jesse Emerson
Gilani Asif Badruddin
Gonzalez Jose Manuel
Green Phillip Sylvestor
Grisanti Rick Scott
Lee Hung
McQuilkin Scott Patrick
Schaller Stephen K
Shi Hunter Feng
Stapleton Lauren Margare
Tam Manhin
Tang Khang Phoung
White Adam Weldon
Williams Chicho Stefan
XOR
XNOR
XOR
XNOR
XOR
XNOR
XOR
XNOR
XOR
XNOR
XOR
XNOR
XOR
XNOR
XOR
3