Data Sheet No. PD-6.043C
IR2101
HIGH AND LOW SIDE DRIVER
Features
Product Summary
n Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
n Gate drive supply range from 10 to 20V
n Undervoltage lockout
n 5V Schmitt-triggered input logic
n Matched propagation delay for both channels
n Outputs in phase with inputs
Description
VOFFSET
600V max.
IO+/-
100 mA / 210 mA
VOUT
10 - 20V
ton/off (typ.)
130 & 90 ns
Delay Matching
30 ns
Packages
The IR2101 is a high voltage, high speed power
MOSFET and IGBT driver with independent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is compatible with standard CMOS or LSTTL outputs. The
output drivers feature a high pulse current buffer stage
designed for minimum driver cross-conduction. The
floating channel can be used to drive an N-channel
power MOSFET or IGBT in the high side configuration which operates up to 600 volts.
Typical Connection
up to 600V
VCC
VCC
VB
HIN
HIN
HO
LIN
LIN
VS
COM
LO
TO
LOAD
C ONTROL I NTEGRATED C IRCUIT D ESIGNERS’ M ANUAL
B-1
IR2101
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions.
Symbol
Parameter
Definition
Value
Min.
Max.
VB
High Side Floating Supply Voltage
-0.3
625
VS
High Side Floating Supply Offset Voltage
VB - 25
VB + 0.3
VHO
High Side Floating Output Voltage
VS - 0.3
VB + 0.3
VCC
Low Side and Logic Fixed Supply Voltage
-0.3
25
VLO
Low Side Output Voltage
-0.3
VCC + 0.3
VIN
Logic Input Voltage (HIN & LIN)
-0.3
VCC + 0.3
dVs/dt
Allowable Offset Supply Voltage Transient
PD
Package Power Dissipation @ TA ≤ +25°C
RθJA
—
50
(8 Lead DIP)
—
1.0
(8 Lead SOIC)
—
0.625
(8 Lead DIP)
—
125
(8 Lead SOIC)
—
200
Thermal Resistance, Junction to Ambient
TJ
Junction Temperature
—
150
TS
Storage Temperature
-55
150
TL
Lead Temperature (Soldering, 10 seconds)
—
300
Units
V
V/ns
W
°C/W
°C
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. The VS offset rating is tested with all supplies biased at 15V differential.
Symbol
Parameter
Definition
Value
Min.
Max.
VB
High Side Floating Supply Absolute Voltage
VS + 10
VS + 20
VS
High Side Floating Supply Offset Voltage
Note 1
600
VHO
High Side Floating Output Voltage
VS
VB
VCC
Low Side and Logic Fixed Supply Voltage
10
20
VLO
Low Side Output Voltage
0
VCC
VIN
Logic Input Voltage (HIN & LIN)
0
VCC
TA
Ambient Temperature
-40
125
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS.
B-2
CONTROL INTEGRATED CIRCUIT DESIGNERS’ MANUAL
Units
V
°C
IR2101
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 15V, CL = 1000 pF and TA = 25°C unless otherwise specified.
Symbol
Parameter
Definition
Min.
Value
Typ. Max. Units Test Conditions
ton
Turn-On Propagation Delay
—
130
200
VS = 0V
toff
Turn-Off Propagation Delay
—
90
200
VS = 600V
tr
Turn-On Rise Time
—
80
120
tf
Turn-Off Fall Time
—
40
70
Delay Matching, HS & LS Turn-On/Off
—
30
—
MT
ns
Static Electrical Characteristics
VBIAS (VCC, VBS) = 15V and TA = 25°C unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM.
The VO and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO.
Symbol
Parameter
Definition
VIH
Logic “1” Input Voltage
VIL
Min.
2.7
Value
Typ. Max. Units Test Conditions
—
—
V
VCC = 10V to 20V
Logic “0” Input Voltage
—
—
0.8
VOH
High Level Output Voltage, VBIAS - VO
—
—
100
VOL
Low Level OutputVoltage, VO
—
—
100
IO = 0A
I LK
Offset Supply Leakage Current
—
—
50
VB = VS = 600V
I QBS
Quiescent VBS Supply Current
—
20
50
VIN = 0V or 5V
IQCC
QuiescentVCC Supply Current
—
140
240
IIN+
Logic “1” Input Bias Current
—
20
40
VIN = 5V
IIN-
Logic “0” Input Bias Current
—
—
1.0
VIN = 0V
VCCUV+
VCC Supply Undervoltage Positive Going
Threshold
8.8
9.3
9.8
VCCUV-
VCC Supply Undervoltage Negative Going
Threshold
7.5
8.2
8.6
I O+
Output High Short Circuit Pulsed Current
100
125
—
I O-
Output Low Short Circuit Pulsed Current
210
250
—
mV
µA
VCC = 10V to 20V
IO = 0A
VIN = 0V or 5V
V
mA
VO = 0V,VIN = 5V
PW ≤ 10 µs
VO = 15V, VIN = 0V
PW ≤ 10 µs
CONTROL INTEGRATED C IRCUIT DESIGNERS’ MANUAL B-3
IR2101
Functional Block Diagram
VB
Q
HV
LEVEL
SHIFT
HIN
PULSE
FILTER
R
HO
S
PULSE
GEN
VS
UV
DETECT
VCC
LIN
LO
COM
Lead Definitions
Lead
Symbol Description
HIN
Logic input for high side gate driver output (HO), in phase
LIN
Logic input for low side gate driver output (LO), in phase
VB
High side floating supply
HO
High side gate drive output
VS
High side floating supply return
VCC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
B-4
8 Lead DIP
SO-8
IR2101
IR2101S
CONTROL INTEGRATED CIRCUIT DESIGNERS’ MANUAL
IR2101
Device Information
Process & Design Rule
Transistor Count
Die Size
Die Outline
Thickness of Gate Oxide
Connections
First
Layer
Second
Layer
Contact Hole Dimension
Insulation Layer
Passivation
Method of Saw
Method of Die Bond
Wire Bond
Leadframe
Package
HVDCMOS 4.0 µm
168
67 X 91 X 26 (mil)
Material
Width
Spacing
Thickness
Material
Width
Spacing
Thickness
Material
Thickness
Material
Thickness
Method
Material
Material
Die Area
Lead Plating
Types
Materials
800Å
Poly Silicon
4 µm
6 µm
5000Å
Al - Si (Si: 1.0% ±0.1%)
6 µm
9 µm
20,000Å
5 µm X 5 µm
PSG (SiO2)
1.5 µm
PSG (SiO2)
1.5 µm
Full Cut
Ablebond 84 - 1
Thermo Sonic
Au (1.0 mil / 1.3 mil)
Cu
Ag
Pb : Sn (37 : 63)
8 Lead PDIP / SO-8
EME6300 / MP150 / MP190
Remarks:
CONTROL INTEGRATED C IRCUIT DESIGNERS’ MANUAL B-5
IR2101
50%
50%
HIN
LIN
HIN
LIN
ton
t off
tr
90%
HO
LO
HO
LO
Figure 1. Input/Output Timing Diagram
HIN
LIN
10%
90%
10%
Figure 2. Switching Time Waveform Definitions
50%
50%
LO
HO
10%
MT
MT
90%
LO
HO
Figure 3. Delay Matching Waveform Definitions
B-6
tf
CONTROL INTEGRATED CIRCUIT DESIGNERS’ MANUAL