KLM Electronics
CDR Review
CDR Review
16‐MAR‐2012
16
MAR 2012
Gary Varner
University of Hawai’i
Outline
•
•
•
•
•
•
System requirements
Performance requirements (DAQ & trigger)
Performance requirements (DAQ & trigger)
Technical implementation (readout)
Technical implementation (trigger)
Development status
Development status
Summary and Schedule
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System Requirements
y
q
((1))
• Operate within Belle‐II Trigger/DAQ environment
• >= 30kHz L1
>= 30kHz L1
• Gbps fiber Tx/Rx
• COPPER backend
• Muon trigger
• Super‐KEKB clock/timing
SuperKEKB RF clock
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System Requirements (2)
y
q
• Belle2link for KLM
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System Requirements (3)
y
q
• Belle‐like timing primitives for GDL (trigger)
New KLM New
KLM
trigger elements
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Performance R
Requirements (daq)
i
t (d )
h
Al
Depletion
Region
2 m
2 m
R 50
Substrate
Ubias
•
a/k/a “Si‐PMs”, MPPCs, SPADs
Relatively inexpensive (standard silicon processing)
•
Insensitive to magnetic fields
Insensitive to magnetic fields
•
Noise is 500kHz − 2MHz not a problem: •
5 p.e. threshold reduces rate to < 1kHz 5
p e threshold reduces rate to < 1kHz
while maintaining ~ 99% MIP efficiency
Results with
Results with prototype ASIC
(TARGET)
Resolve individual p.e.
σ ~ 38.4ps
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Performance Requirements (daq)
q
( q)
• Waveform sampling to tune gain and MPPC response p g
g
p
after neutron damage (eKLM 14‐40Gy/10 yrs)
MPPC+preAmp+TARGET readout
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Performance Requirements (daq)
q
( q)
• High efficiency triggering, ns‐level timing
Setting threshold at 7.5 pixels: SiPM
noise  neutron bg rate even after 10
years of SiPM irradiation
A small degradation of the MIP detection
efficiency (99%  97% at 10 Belle
Belle-II
II years) is
due to smearing of the threshold by noise coadditon. Can be recovered by fitting the signal
p to waveform data in SRM FPGA.
shape
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Performance Requirements (trigger)
• Merge streams to reduce # of links
• Implement algorithms in a common trigger Implement algorithms in a common trigger
module (UT3)
• Trigger algorithm finds 2D track(s) in each l
h f d
k( )
h
projection
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Design Constraints
• Pre‐amps inside module
4x iterations of
Carrier Card design
Temp sensor for
each 15 ch.
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Technical Status: architecture
112+32 DAQ fiber transceivers
36 FINESSE
9 COPPER
20k channels
20k
h
l
1.25k 16‐channel
Waveform sampling
(TARGET) ASICs
112+32 SRM
FTSW for programming/ i i / i
timing/trigger
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Gary Varner, CDR Review – Scint. KLM Electronics
Trigger is common with RPC/barrel :
Use a common merge board
11
Technical Status: Pre‐amplifiers
 will be installed inside the detector
 were tested for radiation hardness at
ITEP proton (200 MeV) beam.
Photo-electron peaks
obtained with
irradiated amplifier
Amplifiers
A
lifi gain
i andd noise
i measuredd
before (blue) and after (red) irradiation
No effect was observed with radiation doses 5
times higher than expected at Belle II.
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Technical Status: ASIC (1)
Initial TARGET design  BLAB architecture
Die Overview
Pre‐production TARGET specifications
p
p
• 16 channels
• 1‐2 GSa/s (cosmic, beam ~2.5GSa/s)
• 12‐bit digitization
12 bit di iti ti
• Samples stored, digitized in groups of 32
• 16k samples per channel (8us at 2GSa/s)
• Event sequencing/timing off‐chip [firmware] 3/16/2012
TSMC 0 25
CMOS
TSMC 0.25m CMOS process
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Technical Status: ASIC (2)
• Sampling: 128
(2x 64) separate
transfer lanes
Recording in one set 64, R
di i
t 64
Very similar to transferring other BLAB:
(“ping‐pong”)
• 2x more channels
• No precision timing requirement
• Storage: 64 x 512 (32k per ch.)
ch )
• Wilkinson ADC (64 at once)
6 conv/channel
/ h
l (512
(
iin parallel)
ll l)
• 64
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Technical Status: SRM (1)
Though looks very different, same framework
same framework as iTOP readout
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Technical Status: SRM (2)
• Readout module prototype
TARGET DC
((10x – to merge
g
DACmon & TARGET
DC)
DAC_MON
(10x)
SCROD
Re-package card as
9U form factor
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Technical Status: back‐end (1)
S ch em atic D raw in g of th e C O P P E R
Detecctor Signals
L ocal B u s
PCI Bus
M ezzan in e C ards
FFIN
INEESSSE
SE
FFIF
IFO
O
FFIN
INEESSSE
SE
FFIF
IFO
O
B
Brid
ridge
ge
B rid ge
P C I M ezzan in e C ard s
FFIN
INEESSSE
SE
FFIF
IFO
O
M
Mem
emory
ory
FFIN
INEESSSE
SE
FFIF
IFO
O
CCPPUU
C
Con
ontrol
trol
B
Brid
ridge
ge
mDvwwsDlvOqcC
mDvwwsDlvOCsDDcqC
Upgraded for
U
d df
Belle II
• COPPER (COmmon Pipelined Platform for Electronics Readout)
• Used in Belle, J-PARC experiments
•FINESSE
N SS ((Front-end
o t e d Instrumentation
st u e tat o Entity
t ty for
o Subdetecto
Subdetector Spec
Specificc Electronics)
ect o cs)
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Technical Status: back‐end (2)
Belle2link
18
Technical Status: Trigger
Trigger time‐stamping same as iTOP
Trigger 1-shot Width Adjust
T_1_TRG
Power (T_1_TRG)
Output Width [ns]
100
A wide variety of established FPGA‐based TDCs with few ns resolution
10
Need anyway for readout hit‐
matching
matching 1
0
20
40
60
80
Discharge Current [uA]
100
120
19
Development Status
p
• SRM firmware lagging (KEK/ITEP)
– Some experience
Some experience in Fermilab
in Fermilab test beam
test beam
– Operation of eKLM quadrant at KEK
• P
Pre‐amps, carrier cards ready for production i
d
d f
d i
(testing @ Virginia Tech)
• (pre‐)Production TARGET ASIC (Hawaii)
TARGET DAC daughtercard (Hawaii)
• TARGET_DAC daughtercard
• 9U VME version of SRM (Hawaii)
• Trigger/fiber merge board (Indiana)
/f b
b d( d
)
• Trigger firmware (Virginia Tech)
gg
( g
)
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Summary and Schedule
Summary and Schedule
• Same
Same basic infrastructure common to all basic infrastructure common to all
subdetector upgrades: common DAQ system
• Waveform sampling ASICs (“oscilloscope on a chip”)) to set/monitor efficiency
chip
to set/monitor efficiency
• Prototypes under test (pre‐amps critical path)
• Pre‐production prototypes end of 2012
• Production in 2013
Production in 2013‐2014
2014
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Back‐up
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Test assembly
Assembly and geometrical/
mechanical compatibility were tested in
J l 2011 with
July
ith the
th first
fi t full
f ll size
i module
d l
Assembly is really easy and fast:
even two professors can assemble one
module during ½ hour; cabling takes
another 30 minutes
3/16/2012
Gary Varner, CDR Review – Scint. KLM Electronics
Module-0 assembly
y
at KEK
23
EKLM electronics
 will be installed inside the detector
 were tested for radiation hardness at
ITEP proton (200 MeV) beam.
Preamplifiers
Photo-electron peaks
obtained with
irradiated amplifier
Amplifiers gain and noise measured
before (blue) and after (red) irradiation
No effect was observed with radiation doses 5
times higher than expected at Belle II.
DAQ motherboard
Multiple ASICs readout checked during beam tests in Fermilab.
Firmware development (to fit SiPM signals  time, amplitude) was started.
Trigger/Timing Distribution (FTSW)
gg
g
From Nakao‐san’s documentation:
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Trigger/Timing Distribution (FTSW)
gg
g
From Nakao‐san’s documentation:
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