A 125 MHz −86 dB IM3 Programmable-Gain Amplifier
Cheng-Chung Hsu and Jieh-Tsorng Wu
Department of Electronics Engineering
National Chiao-Tung University, Hsin-Chu 300, Taiwan
Abstract
A digitally programmable-gain amplifier (PGA) is realized
using a 0.35 µm CMOS technology. Constant bandwidth and
high linearity are achieved by using a current-mode amplifier
with resistor-network feedback. The PGA has a voltage gain
varying from 0 dB to 19 dB with a bandwidth of 125 MHz.
With 1 Vpp output, the third-order intermodulation (IM3) of
the PGA is −86 dB at 10 MHz and −59 dB at 80 MHz. The
distortion is also insensitive to the gain change. The circuit
dissipates 21 mW from a 3.3 V supply.
VG
R
R
V
f1
1
V o-
in+
A1
V
V o+
inR
CL
2
R
VG
R 1a
Ms
f2
Fig. 1. Programmable-gain amplifier (PGA) architecture.
Introduction
In a modern communication receiver, the received signal is
usually quantized by an analog-to-digital converter (ADC) and
then processed in the digital domain using digital circuitry. A
programmable-gain amplifier (PGA) is usually placed in front
of the ADC to adapt the loss variation of the transmission channel so as to ease the dynamic range requirement for the ADC.
It is critical for the PGA to maintain its linearity and low noise
over the entire signal bandwidth as well as gain range.
Shown in Fig. 1 is a fully differential PGA using linear resistors in the feedback network to achieve high linearity. The voltage gain can be adjusted by changing the ratios of R f1 /R1 and
Rf2 /R2 . In the conventional design, the A1 is a voltage-mode
operational amplifier [1]. Whenever the values of R f1 /R1 and
Rf2 /R2 change, the PGA’s frequency bandwidth and the total
harmonic distortion (THD) also change accordingly, due to the
variation of the feedback factor. When the circuit is designed
to cover the worst-case scenario over the entire gain range, its
power dissipation won’t be optimized.
The proposed PGA uses a current-mode operational amplifier for the A1 amplifier. A current-mode amplifier with fixed
feedback resistances of R f1 and Rf2 can maintain a constant
feedback factor, regardless of the input resistances of R 1 and
R2 . Thus, the amplifier can be optimized for minimal power
dissipation with a specific bandwidth. The PGA’s voltage gain
can be varied by changing the resistances of R 1 and R2 . When
the PGA is placed in the automatic gain control (AGC) loop,
the resistors R1 and R2 will be adjusted so that the average
current signals in the resistors remain constant, leading to little
change of linearity at the PGA’s outputs.
The voltage gain of the proposed PGA is controlled by digital signal, in order to facilitate advanced AGC such as decisionfeedback gain control. As shown in Fig. 1, the resistors R 1 and
R2 are realized using linear resistors in series with MOSFET
switches biased in the triode region [2]. The switched resistors are often used to implement low-distortion tunable analog
blocks [3]. The nonlinearity of a MOS transistor can introduce
0 This work was supported by the National Science Council under the contract NSC-91-2215-E-009-009.
0-7803-7310-3/02/$17.00 (C) 2002 IEEE
harmonic or intermodulation distortions, and degrade the linearity of the entire circuit. Accurate analysis of the nonlinear
effect is essential to the design of the PGA and other digitally
tunable circuits. In this paper, a closed-form formula of the
nonlinearity is developed to design the switched resistors R 1
and R2 .
Switched-Resistor Design Considerations
We can describe the drain current of the MOS transistor using Taylor series expansion at V DS = 0. Neglecting terms
whose order is higher than three, the drain current is given by
3
2
ID = gds VDS + α2 VDS
+ α3 VDS
(1)
where gds is the drain-source conductance, α 2 and α3 are
the second and third-order nonlinear coefficients, respectively.
Furthermore, body effect, mobility reduction, and velocity saturation must be considered in order to understand their influence in the deep-submicron technology. Calculated from the
simple level 2 model of the device, the drain current can be
expressed by [4]:
µeff Cox W VGS − VF B − φ0 − γ φ0 + VSB VDS
L
µeff Cox W
γ
2
VDS
1+ −
2L
2 φ0 + VSB
ID =
µeff Cox W
γ
3
+
VDS
3
24L
(φ0 + VSB ) 2
(2)
where µeff is the effective surface mobility, C ox is the gate
oxide capacitance per unit area, V F B is the flat-band voltage,
γ is the body-effect factor, and φ 0 is the surface potential.
Considering the short-channel effects, the mobility term in the
current-voltage characteristic shows a dependence on the voltage VDS or channel electric field [5]. Therefore, it causes the
2002 Symposium on VLSI Circuits Digest of Technical Papers
-20
VG
VG
C gd
C gs
-30
R 1a
Vi
Ii
R ds
R 1a
Vi
C sb
C db
Ii
Fig. 2. A simplified model of the switched resistor in “ON” mode.
Distortion (dB)
Ms
-40
-50
-60
L = 1.4 um HD2
L = 1.4 um HD3
L = 0.35 um HD2
L = 0.35 um HD3
-70
-80
Distortion (dB)
L = 0.35 um
L = 1.4 um
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
measured HD2
measured HD3
calculated HD2
calculated HD3
100
Fig. 4. Measured distortion versus time constant R1 Cs of the
MOSFET switches.
measured HD2
measured HD3
calculated HD2
calculated HD3
-70
-80
-80
100 200 300 400 500 100 200 300 400 500
MOS Resistance (ohm)
MOS Resistance (ohm)
Fig. 3. Measured and calculated HD2 and HD3 of the switched
resistors. R1a + Rds = 1K, Vov = 0.43 V, VSB = 1.83 V, and
1
γ = 0.52 V 2 .
distortion in the switched resistor. Neglecting terms whose order is higher than three, the mobility reduction caused by voltage VDS can be also expressed as
1
2
µeff = µv 1 −
(3)
V
2(LEc )2 DS
where µv is the surface mobility under the effect of vertical
electrical field, and Ec is the critical electric field and equal to
6.09 MV/m in a 0.35 µm process.
Fig. 2 shows the equivalent circuit model of the switched
resistor when the MOS transistor is in the “ON” mode. Input
voltage Vi is converted into nonlinear current I i flowing into
the current-mode amplifier of the PGA. In this weakly nonlinear network, expressions for harmonic distortions (HD 2 and
HD3 ) of the nonlinear current I i can be derived using Volterra
series:
2
−Vi α2 g1a
(4)
HD2 =
2(g1a + gds )2 gds
HD3 =
−Vi2 α3
4
4R13 gds
+
Vi2 α22
5
2R14 g1a gds
(5)
where Vi is the input’s peak amplitude, and R 1 is the total resistance equal to R1a + Rds . The accurate prediction of distortion
is highly dependent on the nonlinear coefficients of the drain
0-7803-7310-3/02/$17.00 (C) 2002 IEEE
1000
Time Constant (ps)
current. The HD2 term is proportional to second-order nonlinear coefficient α 2 . The HD3 term consists of two contributions.
One contribution comes from the third-order coefficient α 3 of
the drain current, and the other is due to the second-order coefficient α2 through the linear conductor g 1a . Using these expressions in (1) and (5), the harmonic distortion can be calculated
as
1
γ
Vi
(6)
+ HD2 =
2R12 β 2 Vov3 2 4 φ0 + VSB
Vi2
Vov
γ
HD3 =
−
3
4R13 β 3 Vov4 2(L · Ec )2 24(φ0 + VSB ) 2
(7)
2
Vi2 R1a
γ
1
+
+ 2R4 β 3 Vov5 2 4 φ0 + VSB
1
where β = µv Cox W /L is the device transconductance parameter, and Vov = gds /β is the gate overdrive voltage. The distortions decrease significantly as R 1 , β, and Vov increase. Increasing gate overdrive voltage is an effective method to lower
the distortions. In (7), the effect of the mobility reduction on
HD3 can be seen from the first term, but it has the opposite
effect against the body effect.
A setup based on Fig. 1 is used to measure the distortions of
the switched resistors [4]. The n-MOS transistors with different channel lengths and widths are fabricated on the test
chip in a 0.35 µm CMOS process. The loop gain of the external voltage-mode opamp is set to 94 dB, which is enough to
suppress the distortions caused by the opamp itself. The gate
overdrive is set to 0.43 V. The distortion figures are measured
at 1 kHz for an input amplitude of 0.5 V. The resistance of R 1a
is adjusted so that the equivalent total resistance R 1 is 1 kΩ.
Calculated and measured distortions are plotted versus MOS
resistance in Fig. 3. It shows that the proposed formulas are
in good agreement with the measured data, even for the short
channel L = 0.35 µm.
Under the condition of measurement setup, the distortions are almost identical with MOSFETs of different channel lengths, if the equivalent MOS resistances are identical.
2002 Symposium on VLSI Circuits Digest of Technical Papers
30
VDD
Mb7
M7
M6
M12
M8
Mb5
V i+
M14
Mb8
V bp
Mb6
M1 M9
Mb1
V i-
Mb2
M2
M10
C c2
C c1
V o-
M3
V bn
Mb3
Buffer
0
-10
R f1
R f2
M4 M13
M5
10
M11
V o+
R1
20
Gain (dB)
V bp
M15
VSS
Current Amplifier
R2
V bn
Mb4
-20
1
10
100
Frequency (MHz)
Buffer
Fig. 6. Measured frequency response of the PGA.
Fig. 5. PGA circuit schematic.
Therefore, it can be deduct that the mobility reduction contributes much less distortions than the second term of (7) in
the 0.35 µm technology. The MOS transistor with wider channel width obviously exhibits better linearity for a given channel
length and R1 . However, the associated larger gate capacitance
and parasitic capacitance can degrade the stability and settling
time of the PGA. In Fig. 2, C s = Cgs + Csb is proportional to
channel width and thus HD 2 has the relationship
HD2 ∝
1
R12 W 2
∝
1
R12 Cs2
(8)
Fig. 4 shows the distortions versus R 1 Cs of the switched resistors. There is a trade-off between the linearity and the bandwidth of the PGA, and the switches with shorter channel length
should be used since short channel effects on distortions are
still not evident. As a result, when the differential architecture
is used and the body effect is ignored, the transistor size can be
calculated from (7) approximately as
Vi2 R1a
1 W
3
≈
(9)
L
µv Cox 8HD3 R4 Vov5
1
PGA Circuit Design
Fig. 5 shows the circuit schematic of the PGA. It consists
of two voltage buffers and a fully differential current-mode
amplifier. For simplicity, the schematic is explained with the
half-circuit analysis. A super-source follower [6], Mb1-Mb7,
is placed before input switched resistor R 1 to provide high input impedance for the inputs. Mb5 and Mb7 form the current
driver to deliver constant output current to the current amplifier. At a constant output current, the nonlinearity of Mb5 is
suppressed by the loop gain T 1 [4], which can be expressed as:
gmb5 rob7 · gmb1 R1
T1 =
2 + gmb1 R1
(10)
where gmb5 and gmb1 are the transconductance of Mb5 and
Mb1, respectively, and r ob7 is the output resistance of Mb7.
0-7803-7310-3/02/$17.00 (C) 2002 IEEE
The maximum loop gain of the super-source buffer can be
achieved by increasing g mb5 and rob7 , and thus minimizes the
distortions contributed by the transistor Mb5. The variation of
the loop gain is small if g mb1 R1 is high enough, regardless of
the change of resistance R 1 . This makes the distortion insensitive to the gain change.
The current signal is received by the M2 common-gate
stage, followed by the M1 common-source amplifier. The
transconductance of M2 is boosted by the local feedback
loop consisting of the M3 and M7. The resulting low input
impedance is essential to obtain wide bandwidth and good linearity. The loop gain T 2 of the current amplifier can be expressed by
T2 =
gm1 ro6 (1 + sCc1 Rf1 )
(1 + sCp ro6 )[1 + s(Cc1 + CL )Rf1 ]
(11)
where gm1 is the transconductance of M1, r o6 is the output
resistance of M6, C c1 is the compensation capacitor, C L is
the output load, and C p is the parasitic capacitor at the drain
of M2. The frequency compensation capacitor C c1 , creates
no right half-plane feedforward zero usually associated with
the Miller compensation technique. At high frequency, the
compensation capacitors also boost the loop gain, thus improving the amplifier’s linearity. Simulation shows that, with
Cc1 = Cc2 = 0.3 pF and C L = 2 pF, the compensation capacitors can improve the linearity by 3 dB, comparing with
traditional Miller compensation.
To enable the common-mode rejection capability, the
M1-M9 source-coupled pair implements the second-stage
common-source amplifier. Not shown in the schematic
is a common-mode feedback circuitry, which monitors the
common-mode voltage at the gates of M1 and M9 and adjusts
the output currents of M6 and M12.
Experimental Results
The PGA was fabricated in a standard 0.35 µm CMOS technology. The resistors are the polysilicon resistors. The resistance of Rf1 is 5k while the maximum and minimum resistances of R1 are 0.42k and 4.2k, respectively. The switched
2002 Symposium on VLSI Circuits Digest of Technical Papers
-30
Output IM3 (dB)
-40
-50
-60
-70
2Vpp vout, gain=0dB
2Vpp vout, gain=19dB
1Vpp vout, gain=0dB
1Vpp vout, gain=19dB
-80
-90
0
20
40
60
80
100
Frequency (MHz)
Fig. 7. Measured PGA’s IM3 versus frequency.
Fig. 9. Chip micrograph of the PGA.
TABLE I
PGA specifications
Technology
Power Dissipation (3.3V supply)
Bandwidth
Gain Range
Gain Error at 14dB and 20dB Gain
Setting
Input Referred Noise (19 dB gain)
Input Referred Noise (0 dB gain)
IM3 (1 Vpp output, C L = 2pF, and
Fsignal ≤ 70 MHz )
Active Area
0.35 µm CMOS
21 mW
125MHz
0 dB–19 dB
0.35dB and 1dB
√
8.6 nV/ √Hz
28.8 nV/ Hz
≤ −60 dB
0.18 mm 2
Fig. 8. Measured IM3 of the PGA at 80 MHz with Vout = 1 Vpp.
resistors are weighted to obtain a dB-linear gain step with a
step size of 2 dB. As shown in Fig. 6, the PGA has a measured voltage gain varying from 0 dB to 19 dB while maintaining a constant bandwidth of 125 MHz with 2 pF capacitive loads. Power dissipation is 21 mW from a 3.3 V supply. Fig. 7 shows the IM3 is dependent on input frequency
and output amplitude. The magnitude of the IM3 changes less
than 5 dB with 1 Vpp output over the full gain range up to
80 MHz. The PGA has an IM3 ≤ −60 dB for 0–70 MHz with
1 Vpp differential output voltage; in addition, the IM3 is also
as low as −86 dB at 10 MHz for an output voltage of 1 Vpp.
Fig. 8 shows the measured
output spectrum. The input referred
√
noise is 8.63 nV/ Hz for 19-dB gain. The active area occupies 0.18 mm2 , and the PGA specifications are summarized in
Table I. A photograph of the experimental chip is shown in
Fig. 9.
Conclusions
A PGA using current-mode amplifier and resistor-network
feedback can achieve constant bandwidth, high linearity, and
optimal power dissipation. The voltage gain is digitally controlled through the switched-resistor network, and the distortion of the switched resistors can be predicted by a closed-form
0-7803-7310-3/02/$17.00 (C) 2002 IEEE
formula. The distortion is heavily dependent on the associated
linear resistor, gate overdrive voltage, and the size of the MOS
transistor.
Acknowledgment
The authors thank Chip Implementation Center of the National Science Council for chip fabrication and die bonding.
References
[1] John Guido, et al., “Analog front end IC for category I & II
ADSL,” in Symposium on VLSI Circuits Digest of Technical Papers, pp. 178–181, 2000.
[2] J. J. F. Rijns, “CMOS Low-Distortion High-Frequency VariableGain Amplifier,” IEEE Journal of Solid-State Circuits, vol. 31,
pp. 1029–1034, July 1996.
[3] U. K. Moon, and B. S. Song, “Design of a Low-Distortion 22-kHz
Fifth-Order Bessel Filter,” IEEE Journal of Solid-State Circuits,
vol. 28, pp. 1254–1264, December 1993.
[4] P. Wambacq, and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Norwell, MA: Kluwer, 1998.
[5] Yannis Tsividis, Operation and Modeling of the MOS Transistor.
New York: McGraw-Hill Book Company, 1999.
[6] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis
and Design of Analog Integrated Circuits. Forth Edition, Wiley,
New York, 2000.
2002 Symposium on VLSI Circuits Digest of Technical Papers