Design for Reliability

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Design for Reliability
© 2005
2004 - 2010
2007
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1
Reality of Design for Reliability (DfR)
„
Ensuring reliability of electronic
designs is becoming increasingly
difficult
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Increasing complexity of electronic
circuits
Increasing power requirements
Introduction of new component and
material technologies
Introduction of less robust
components
Results in multiple potential
drivers for failure
© 2005
2004 - 2010
2007
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2
Reality (cont.)
„
Predicting reliability is becoming problematic
‰
‰
© 2005
2004 - 2010
2007
Standard MTBF calculations can tend to be
inaccurate
A physics-of-failure (PoF)
approach can be timeintensive and not always
definitive (limited insight
into performance during
operating life)
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3
Why This DfR?
„
The process of Design for Reliability (DfR) is
achieving a high profile in the electronics
industry
‰
‰
„
DfR is even on Wikipedia!
Part of an overall Design for Excellence (DfX)
Numerous organizations
now offer DfR training
tools (courses, books, etc.)
‰
© 2005
2004 - 2010
2007
Response to market demand
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4
Why This DfR? (cont.)
„
However, many of these tools are
‰
‰
Too broad in focus (not electronics focused)
Too much emphasis on techniques (e.g., FMEA
and FTA) and not answers
„
‰
Incorporation of HALT and failure analysis (HALT
is test, not DfR; failure analysis is too late)
„
© 2005
2004 - 2010
2007
FMEA/FTA rarely identify DfR issues because of limited
focus on the failure mechanism
Frustration with ‘test-in reliability’, even HALT, has been
part of the recent focus on DfR
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5
DfR Outline
„
What this section will not be about
‰
‰
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Not supplier issues
Not production issues
Not testing issues
Not MTBF / MTTF
Strictly design and material selection
© 2005
2004 - 2010
2007
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6
DfR Outline
„
DfR at Concept / Block-Diagram Stage
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„
Part selection
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Specifications
Derating and uprating
Wearout mechanisms and physics of failure
‰
© 2005
2004 - 2010
2007
Predicting degradation in today’s electronics
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7
Design for Reliability
At Concept: Specifications
© 2005
2004 - 2010
2007
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8
Concept / Block Diagram
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Can DfR mistakes occur at this stage?
‰
„
No………..and Yes
Failure to capture and understand product
specifications at this stage lays the
groundwork for mistakes at schematic and
layout
© 2005
2004 - 2010
2007
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9
Specifications
„
Important specifications to capture at concept
stage
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© 2005
2004 - 2010
2007
Reliability expectations
Use environment
Dimensional constraints
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10
Reliability Goals
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Reliability is the measure of a product’s ability to
‰
‰
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…perform the specified function
…at the customer (with their use environment)
…over the desired lifetime
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Typical reliability metrics: Desired Lifetime / Product Performance
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Desired lifetime
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Defined as when the customer will be satisfied
Should be actively used in development of part and product
qualification
Product performance
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‰
© 2005
2004 - 2010
2007
Returns during the warranty period
Survivability over lifetime at a set confidence level
Try to avoid MTBF or MTTF
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11
Failure Rate
Why is Desired Lifetime Important?
Electronics: Today and the Future
Electronics: 1960s, 1970s, 1980s
Wearout!
No wearout!
Time
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2004 - 2010
2007
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12
Desired Lifetime (IC Wearout)
Process Variability
confidence bounds
1000
100
Airplanes
Mean
Service 10
life, yrs.
Computers
laptop/palm
cell phones
1.0
0.1
Technology
0.5 µm
0.25 µm
1995
130 nm
65 nm
2005
Year produced
35 nm
2015
Known trends for TDDB, EM and HCI degradation
(ref: extrapolated from ITRS roadmap)
© 2005
2004 - 2010
2007
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13
Desired Lifetime (Capacitor Wearout)
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Ceramic chip capacitors with high capacitance / volume (C/V) ratios
‰
Can fail in less than one year when operated at rated voltage and temperature
© 2005
2004 - 2010
2007
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14
Solder Wearout (cont.)
„
„
Design change: More silicon, less plastic
Increases mismatch in coefficient of thermal
expansion (CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR QFN TYPE PACKAGES,
Ahmer Syed and WonJoon Kang, Amkor Technology.
© 2005
2004 - 2010
2007
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15
Examples: Desired Lifetime
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Low-End Consumer Products (Toys, etc.)
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Do they ever work?
Cell Phones:
Laptop Computers:
Desktop Computers:
Medical (External):
Medical (Internal):
High-End Servers:
Industrial Controls:
Appliances:
Automotive:
Avionics (Civil):
Avionics (Military):
Telecommunications:
© 2005
2004 - 2010
2007
18 to 36 months
24 to 36 months
24 to 60 months
5 to 10 years
7 years
7 to 10 years
7 to 15 years
7 to 15 years
10 to 15 years (warranty)
10 to 20 years
10 to 30 years
10 to 30 years
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16
Product Performance: Warranty Returns
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Consumer Electronics
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„
Low Volume, Non Hi-Rel
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1 to 2%
Industrial Controls
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Table on right
(1st
500 to 2000 ppm
Year)
Depends on complexity,
production volumes, and risk
sensitivity
Automotive
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1 to 5% (Electrical,
Year)
Can also be reported as
problems per 100 vehicles
Percent of revenue (1.2 to 4.5)
© 2005
2004 - 2010
2007
1st
Repair rate (%)
[First 3 Yrs]
Product
Desktop PC
37
Laptop PC
33
Refrigerator: side-by-side (with icemaker and dispenser)
28
Washing machine
22
Refrigerator: top- and bottom-freezer (with icemaker)
17
Projection TV
16
Vacuum cleaner (excluding belt replacement)
13
Dishwasher
13
Clothes dryer
13
Microwave oven (over-the-range)
12
Electric range
11
Camcorder
8
Digital camera
8
Refrigerator: top- and bottom-freezer (without icemaker)
8
TV: 30- to 36-inch
7
TV: 25- to 27-inch
5
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Consumer Reports 2006
17
Product Performance: Survivability
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Some companies set reliability goals based on
survivability
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Advantages
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Often bounded by confidence levels
Example: 95% reliability with 90% confidence over 15
years
Helps set bounds on test time and sample size
Does not assume a failure rate behavior (decreasing,
increasing, steady-state)
Disadvantages
‰
© 2005
2004 - 2010
2007
Can be re-interpreted through mean time to failure (MTTF)
or mean time between failures (MTBF)
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18
Limitations of MTTF/MTBF
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MTBF/MTTF calculations tend to assume that
failures are random in nature
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Easy to manipulate numbers
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Tweaks are made to reach desired MTBF
E.g., quality factors for each component are modified
Often misinterpreted
‰
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Provides no motivation for failure avoidance
50K hour MTBF does not mean no failures in 50K hours
Better fit towards logistics and procurement, not
failure avoidance
© 2005
2004 - 2010
2007
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19
Identify Field Environment
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„
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Approach 1: Use of industry/military
specifications
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MIL-STD-810,
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MIL-HDBK-310,
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SAE J1211,
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IPC-SM-785,
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Telcordia GR3108,
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IEC 60721-3, etc.
Advantages
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No additional cost!
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Sometimes very comprehensive
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Agreement throughout the industry
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Missing information? Consider standards
from other industries
Disadvantages
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Most more than 20 years old
‰
Always less or greater than actual (by how
much, unknown)
MIL HDBK310
IPC SM785
© 2005
2004 - 2010
2007
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20
Field Environment (cont.)
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Approach 2: Based on actual measurements
of similar products in similar environments
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Determine average and realistic worst-case
Identify all failure-inducing loads
Include all environments
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„
© 2005
2004 - 2010
2007
Manufacturing
Transportation
Storage
Field
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21
Failure Inducing Loads
• Temperature Cycling
– Tmax, Tmin, dwell, ramp times
• Sustained Temperature
– T and exposure time
• Humidity
– Controlled, condensation
• Corrosion
– Salt, corrosive gases (Cl2, etc.)
• Power cycling
– Duty cycles, power dissipation
• Electrical Loads
– Voltage, current, current density
– Static and transient
• Electrical Noise
• Mechanical Bending (Static and Cyclic)
– Board-level strain
• Random Vibration
– PSD, exposure time, kurtosis
• Harmonic Vibration
– G and frequency
• Mechanical shock
– G, wave form, # of events
© 2005
2004 - 2010
2007
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22
Field Environment (Best Practice)
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Use standards when…
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Measure when…
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Certain aspects of your environment are common
No access to use environment
Certain aspects of your environment are unique
Strong relationship with customer
Do not mistake test specifications for the
actual use environment
‰
© 2005
2004 - 2010
2007
Common mistake with vibration loads
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23
Electrical Environments
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„
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Often very well defined in developed
countries
Introduction into developing countries can
sometimes cause surprises
Rules of thumb
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‰
© 2005
2004 - 2010
2007
China: Can have issues with grounding
(connected to rebar?)
India: Numerous brownouts (several a day)
Mexico: Voltage surges
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24
Temperature: Worst-Case (Ambient)
Temperature
Avg. U.S.
Avg. U.S.
Weighted by Registration
CLIM Data
(Source: Confidential)
Phoenix
(hrs/yr)
U.S.
Worst Case
(hrs/yr)
95F (35C)
0.375%
0.650%
11% (948)
13% (1,140)
105F (40.46C)
0.087%
0.050%
2.3% (198)
3.8% (331)
115F (46.11C)
0.008%
0.001%
0.02% (1.4)
0.1% (9)
© 2005
2004 - 2010
2007
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25
Temperature: Closed Containers
Container and Ambient Temperature
75.0
Temp.
Variation
65.0
55.0
Temperature (°C)
Trucking
Container
Container Temp (°C)
Outdoor Temp (°C)
45.0
35.0
25.0
15.0
0
50
100
150
200
250
300
350
400
450
Hours
© 2005
2004 - 2010
2007
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26
Temperature: Long-Term Exposure
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For electronics used outside with minimal power dissipation, the
diurnal (daily) temperature cycle provides the primary
degradation-inducing load
Phoenix, AZ
Month
Cycles/Year
Ramp
Dwell
Max. Temp (oC)
Min. Temp. (oC)
Jan.+Feb.+Dec.
March+November
April+October
90
60
60
6 hrs
6 hrs
6 hrs
6 hrs
6 hrs
6 hrs
20
25
30
5
10
15
May+September
June+July+August
60
90
6 hrs
6 hrs
6 hrs
6 hrs
35
40
20
25
© 2005
2004 - 2010
2007
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27
Humidity / Moisture (Rules of Thumb)
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Non-condensing
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Condensing
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Standard during operation, even in outdoor applications
Due to power dissipation
Can occur in sleep mode or non-powered
Driven by mounting configuration (attached to something at
lower temperature?)
Driven by rapid change in environment
Can lead to standing water if condensation on housing
Standing water
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‰
© 2005
2004 - 2010
2007
Indirect spray, dripping water, submersion, etc.
Often driven by packaging
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28
Dimensions
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Keep dimensions loose at this stage
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Case study: Use of 0201 chip components
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Large number of hardware mistakes driven by arbitrary size
constraints
Examples include poor interconnect strategies and poor
choices in component selection
Tight dimensional requirements push designer towards
wholesale placement of 0201 components
0201 is not yet an appropriate technology for systems
requiring reliability
Result: Major issues at customers
Use the Toyota approach
‰
© 2005
2004 - 2010
2007
Except with sudden acceleration
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29
Toyota Approach
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Toyota's development engineers are
4X as productive as U.S. counterparts.
Why?
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Focus on learning as much as possible
Use of that knowledge to develop a stream of excellent products
Western engineers
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© 2005
2004 - 2010
2007
Define several product concepts
Select the one that has the most
promise
Draw up specifications and
divide them into subsystems;
Subsystems are designed, built
and rolled up for system testing.
Failures? Rework the specs and
the designs accordingly (nonoptimized and confusing
endeavor)
„
Toyota engineers
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‰
Efforts concentrated at lowest
possible design level
Thorough understanding of the
technology of a subsystem so it
can be used appropriately in
future designs
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30
Toyota Example: Radiators
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Traditional approach: Design radiator for a specific vehicle
based on mechanical specifications written for that vehicle
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Toyota considers a range of radiator solutions based on cooling
capacities and the cooling demands of various engines that
might be used.
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How the radiator actually fits into a vehicle would be kept loose so
that Toyota's knowledge of radiator technology could be used to
create the optimum design
Toyota's system is "test & design" rather than the traditional
"design & test."
‰
© 2005
2004 - 2010
2007
Toyota engineers test at the fundamental knowledge level so they
don't have to test at the later, more expensive stages of design and
prototyping
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31
Design for Reliability
Part Selection
© 2005
2004 - 2010
2007
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32
Part Selection
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The process of creating the bill of materials
(BOM) during the ‘virtual’ design process
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Before physical layout
For some companies, this is during the
creation of the approved vendor list (AVL)
‰
© 2005
2004 - 2010
2007
Design-independent
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33
Part Selection (cont.)
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KIS: Keep it Simple
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New component technology can be very attractive
Not always appropriate for high reliability embedded
systems
Be conservative
Reality: Marketing hype FAR exceeds actual
implementation
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© 2005
2004 - 2010
2007
Component manufacturers typically use portable sales to
boost numbers
Claim: We have built 100’s of millions of these components
without a single return!
Actuality: All sales were to two cell phone customers with
lifetimes of 18 months
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34
Part Selection (cont.)
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Even when used by hi-rel companies, some
modifications may have been made
‰
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Example: State-of-the-art crystal oscillator required
specialized assembly to avoid failures one to three years
later in the field
Prior examples of where care should have been
taken
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‰
© 2005
2004 - 2010
2007
New technologies: X5R dielectric, SiC diodes, etc.
New packaging: Quad flat pack no lead (QFN), 0201, etc.
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35
Part Selection (cont.)
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As technology progresses, functional performance
has become a limited aspect of the part selection
process
Other concerns are increasingly taking center stage
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Moisture sensitivity level (MSL)
Temperature sensitivity level
Electrostatic discharge (ESD) classification
Manufacturability (Design for Assembly)
Plating material
Lifetime / Long-term reliability
„
© 2005
2004 - 2010
2007
Sometimes Physics of Failure is required
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36
Critical Components
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„
Most small to mid-size organizations do not have the resources to
perform a thorough part selection assessment on every part
‰ Does not excuse performing this activity
‰ Requires focusing on components critical to the design
Critical Components: A narrowed list of components of most
concern to the OEM
‰ Sensitivity of the circuit to component performance
‰ Number of components within the circuit
‰ Output from FMEA / FTA
‰ Past experiences
‰ Complexity of the component
‰ Industry-wide experiences
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2007
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37
Critical Components (Industry Experience)
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Optoelectronics
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Low volume or custom parts
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Non-volatile memory has limited data retention time and
write cycles
Parts with mechanical movements (switches, relays,
potentiostats, fans)
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Part is no longer a commodity item
Memory devices
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High volume controls not always in place
Wearout can initiate far before 20 years
Depending on environment, wear out can initiate far before 20
years
Surface mount ceramic capacitors
‰
© 2005
2004 - 2010
2007
Assembly issues
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Critical Components (cont.)
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New technologies or state-of-the-art
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‰
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Electronic modules
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Part is a miniature assembly (no longer a commodity item)
Power components
Fuses
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At the limit of the manufacturer’s capabilities
MEMS, 45-nm technology, green materials, etc.
Susceptible to quality issues
Electrolytic capacitors
‰
© 2005
2004 - 2010
2007
Depending on environment, wear out can initiate far before
20 years
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Part Selection
(ESD)
© 2005
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2007
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40
Part Selection for ESD
„
Industry movement to decreasing feature
sizes and high frequency technology
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‰
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90nm → 65nm → 45nm
GaAs / SiGe desirable at high GHz
Increasing ESD risks
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‰
© 2005
2004 - 2010
2007
More parts are ESD susceptible
ESD sensitivity is increasing (is Class 0 still
sufficient?)
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41
Parts Selection for ESD (cont.)
„
Know the ESD rating for each part and select
parts with the best ESD rating
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‰
„
Identify all ESD Sensitive Parts on drawings
Mark Locations of ESD Sensitive parts on the
Board with the ESD symbol
Be aware that the appropriate ESD rating is
driven by part location
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2004 - 2010
2007
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42
ESD Sensitivity and Location
„
Use ESD Protection on all susceptible parts
‰
Box or System I/O
„
‰
„
ESD Rating < Class 2 HBM IEC (4000V, 150pf, 330 Ohm) MANDATORY
Internal Components (not exposed to outside connectors)
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ESD Rating <= Class 1 ANSI (0-999V) MANDATORY
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ESD Rating < Class 2 ANSI (2000V) WHEREVER POSSIBLE
High Speed, RF and GaAs parts will be sensitive to ESD
[Class 0 (<250V) or Class 1A (<500V)]
‰
‰
‰
© 2005
2004 - 2010
2007
Place ESD sensitive components and traces to avoid locations where
the board may be handled
Avoid Coupled ESD events – Do not route traces to ESD sensitive parts
near lines connected to the outside world
Install protective devices before ESD sensitive parts (Class 1 or lower)
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43
Evaluate Potential ESD
„
If ESD sensitive parts are used in design, the circuitry
connected to device pins should be evaluated
‰
„
Insure that it provides “attenuation” to prevent voltage in excess
of the parts ESD rating from developing in case the pin or
connected traces are contacted during board handling or system
assembly.
Often the recommended circuit components for operation of
the part will provide adequate ESD protection.
‰
‰
This should be verified by analysis or simulation and extra
protection added as required to limit the voltage seen at the part.
Assumptions for analysis/simulation
„
„
© 2005
2004 - 2010
2007
2000V,1.5K, 100pf for Internal circuits
4000V, 330 Ohms, 150pf for I/Os
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Part Selection
(Plating Material)
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2007
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45
Tin Whiskers – Failure Modes
Courtesy of P. Bush, SUNY Buffalo
„
Direct Contact
‰
‰
„
Requires growth of sufficient length
and in the correct orientation
Electromagnetic (EM) Radiation
‰
‰
„
Causes an electrical short
Emits or receives EM signal and
noise at higher frequencies
Deterioration of signal for
frequencies above 6 GHz
independent of whisker length
DfR Solutions
Debris
‰
Whisker breaks off and shorts two
leads (primarily during handling)
© 2005
2004 - 2010
2007
Observation of tin whisker debris as
reported to NASA from Sanmina-SC
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46
Tin Whiskers – Root Cause
„
Whiskering behavior is speculated
to be driven by stress gradients
‰ Results in preferential diffusion
paths
„
Stresses can be extrinsic or
intrinsic
‰ Extrinsic: pressure, bending,
corrosion
‰ Intrinsic: plating, intermetallics
„
The grains that whisker are
supposedly based on orientation
and oxide morphology
© 2005
2004 - 2010
2007
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47
What Do We Know about Tin Whiskers?
„
It can take days to years before tin whiskers start to grow
„
Growth rates can vary by orders of magnitude
‰
„
Maximum lengths can vary by orders of magnitude
‰
‰
„
Usually 1 to 5 µm
Current carrying capability
‰
‰
„
Highly dependent upon plating type and substrate material
Bright (?) tin on steel - 25 mm; Matte tin on copper - 0.5 mm
Diameters of 6 nm to 7 µm recorded
‰
„
0.1 to 200 microns per day
Typically 10 - 35 mA, up to 75 mA observed
Plasma arcing, up to 200 A possible
Plating type plays a very important role
Source GEB-0002
© 2005
2004 - 2010
2007
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48
Bright vs. Matte: Plating Differences
„
Bright tin can be “bad” plating and matte tin can be “better” plating, not
necessarily “good” plating
Problem: quantitative definitions of bright tin and matte tin can vary
‰
„
What are the differences?
Appearance
Sulfate, stannate, methane sulfonate (MSA) or fluoro-borate baths
Carbon content in plating (organic brighteners and other agents)
Grain size and grain orientation (lattice structure)
‰
‰
‰
‰
Grain Size
Carbon Content
© 2005
2004 - 2010
2007
Bright Tin
Matte Tin
Tyco
< 1 µm
~ 3 µm
iNEMI
0.5 – 0.8 µm
1 – 5 µm
Tyco
< 0.3%
< 0.05%
iNEMI
0.2 – 1.0%
0.005 – 0.05%
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Current
terminology
considered
ineffective in
capturing whisker
risks
49
What Else Do We Know?
„
Temperature cycling primarily accelerates whiskering when there
is a large mismatch in thermal expansion
‰ Example: Tin-plated Alloy 42 (Ni-Fe alloy)
‰ Tends to be less effective for tin-plated copper
„
Temperature/Humidity
‰ Tends to be more effective for tin-plated copper
‰ ‘Corrosion’ sites, areas of condensation, tend to accelerate
whisker growth
„
Electric Field
‰ No effect
„
Vibration / Mechanical Shock
‰ Whiskers do not break
© 2005
2004 - 2010
2007
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50
Tin Whiskering and Alloy 42
„
Industry seems to be unable to prevent whiskering
of tin plating over discrete (‘loose’) Alloy 42
components
‰
„
Standard mitigation techniques are not available
(NiPdAu) or have limited influence (nickel
underplate, anneal)
‰
„
Whisker lengths > 67 microns (Class 1 as per JESD201)
when exposed to JESD 22A121 temperature cycle
Exposure to Pb-free reflow (peak temp > 232C) may
provide mitigation (Micron)
Maximum whisker lengths may saturate at values
lower than tin over copper
© 2005
2004 - 2010
2007
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51
What Don’t We Know?
„
Tin whiskering is a complex problem
„
Drivers are a combination of Materials and Environment
‰
Materials: metals, intermetallics, organic inclusions, affect grain
size, grain structure, grain boundary behavior
„
‰
„
Depends on: substrate materials, substrate thickness, substrate geometry,
plating bath composition, plating thickness, plating material composition,
plating microstructure
Environment: temperature, humidity, corrosion, stress gradients
Compressive stress gradients (global vs. local) play a
very important role
‰
© 2005
2004 - 2010
2007
Intermetallic formation, residual stresses in tin plating, external
stress, mechanical loading, coefficient of thermal expansion
(CTE) mismatches, corrosion or oxidation, damage to surface
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52
Don’t Know (cont.)
„
No organization has identified a technique to
predict maximum whisker length for a
particular component
„
No organization has identified a plating
parameter or additive (other than Pb) that will
consistently (under all conditions) prevent
plated tin from whiskering
„
What’s left?
‰
© 2005
2004 - 2010
2007
Mitigation
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53
Tin Whiskering
(Mitigation)
© 2005
2004 - 2010
2007
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54
How to Mitigate Tin Whiskers?
„
„
The first step is to focus mitigation on critical
components
Critical components are based upon three
pieces of knowledge
‰
‰
‰
© 2005
2004 - 2010
2007
The overwhelming majority of tin plated electronic
parts are matte tin over copper
Matte tin over copper produces whiskers of a finite
length
Whiskers tend to only break off during handling
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55
Maximum lengths – Matte Sn over Cu
Reference
Environment
Time Period
Maximum Length
JEITA[10]
25C/50%RH
4000 hours
150 microns
Peng (Freescale)[1]
60C/93%RH
3000 hours
70 microns
Hashemzadeh (Linköping)[2]
-60C/60C
500 cycles
130 microns
Okada (Murata)[3]
-40C/85C
2200 cycles
85 microns
Gedney (iNEMI)[4]
60C/95%RH
3000 hours
60 microns
-55C/85C
3000 cycles
35 microns
iNEMI – DOE3)[5]
60C/93%RH
8000 hours
270 microns
Brusse (NASA)[6]
-40C/90C
500 cycles
250 microns
60C/93%RH
5000 hours
450 microns
Room Conditions
8500 hours
100 microns
-55/85C
3000 cycles
40 microns
Romm (TI)[8]
51C/85%RH
3634 hours
34 microns
Dittes (E4)[9]
30C/60%RH
450 days
275 microns
-55C/85C
3000 cycles
35 microns
Hilty (Tyco)[7]
[1]
Peng Su, Min Ding, and Sheila Chopin, "Effects of Reflow on the Microstructure and Whisker Growth Propensity of Sn Finish", Proceedings of the 55th ECTC
Study of Tin Whisker Growth and their Mechanical and Electrical Properties, Moheb Nayeri Hashemzadeh, Undergraduate Thesis, Linköping University, 2005
[3] S. Okada, et al, "Field Reliability Estimation of Tin Whiskers Generated by Thermal Cycling Stress", Capacitor and Resistor Technology Symposium (CARTS) Europe, October 2003
[4] R. Gedney, J. Smetana, N. Vo, G. Galyon, "NEMI Tin Whisker Projects", Second International Conference on Lead Free Electronics, June 21-23, 2004 (Amsterdam)
[5] “Tin Whisker Test Committee Results (Phase 3)", Presentation at ECTC NEMI workshop, June 1, 2005
[6] J. Brusse, "Tin Whisker Observations on Pure Tin-Plated Ceramic Chip Capacitors", Proceedings of the American Electroplaters and Surface Finishers (AESF) SUR/FIN Conference, June 24-28, 2002, pp. 45-61
[7] Tin Whiskers in Electronic Components, Bob Hilty, www.tycoelectronics.com/environment/ leadfree
[8] D. Romm, D. Abbott, S. Grenney, M. Khan, "Whisker Evaluation of Tin-Plated Logic Component Leads", Texas Instruments Application Report SZZA037A, February 2003
[9] Standard for Whisker Acceptance Level in Pb-free Lead Finish. A Step towards Green Packaging for Consumer Products to Drive Future European Strength, Final Report. Contract No: IST-2001-37826.
01.06.2002 - 30.11.2004, Marc Dittes, Infineon Technologies
[10] Tin Whisker Workshop, ECTC2005, Tin Whisker Test Committee Results (Phase 3)
[2]
© 2005
2004 - 2010
2007
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56
When Do Really Long Whiskers Occur?
„
Usually bright tin and/or tin plating over a substrate
material other than copper (brass, bronze, steel, etc.)
NASA (Leidecker): 25 mm over +10 years
Bright tin over BeCu(?) or steel(?)
© 2005
2004 - 2010
2007
DfR (Fischer): +2 mm over 6 months
Tin (matte?) over brass
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Tin Whiskers: Effect of Substrates
Sakuyama (FUJITSU Sci. Tech. J., 2005)
Sn over Phosphor-Bronze 10X
longer than Sn-Cu over Copper
© 2005
2004 - 2010
2007
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58
Tin Whiskers: Critical Components
JEDEC JESD201
„
Spacings of less than 500 microns
‰
‰
‰
„
Contact points (connector flex circuitry)
‰
„
Stress gradients could change maximum
length
Welds (electrolytic capacitors)
‰
„
Parts with 0.8 mm lead pitch or less
0201 chip components
Metal can housing
Stress gradients could change maximum
length
Note: some organizations specify the critical
spacing as 350 microns (e.g., EU)
‰
© 2005
2004 - 2010
2007
0.65 mm pitch or less
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59
How to Mitigate?
„
„
„
There are three basic approaches to mitigation
Data Gathering and Monitoring
Part Manufacturer Mitigation
‰
„
Steps offered by your suppliers
Equipment Manufacturer (OEM) Mitigation
‰
© 2005
2004 - 2010
2007
Steps you have to perform yourself
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60
Data Gathering and Monitoring
„
„
Driven by iNEMI and JEDEC
(JESD22A121.01, JESD201, JP002)
Industry recommended qualification
tests
‰
‰
‰
‰
„
Ambient (25ºC/50%RH, 4000 hrs)
Elevated (55ºC/85%RH, 4000 hrs)
Cyclic (-40 to 85ºC, 1500 cycles)
Shorter test times for consumer
products
Use manufacturer’s data, require thirdparty testing, or perform your own
‰
‰
© 2005
2004 - 2010
2007
Visual inspection should be performed
properly
http://nepp.nasa.gov/whisker/video/
inspection/index.html
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61
JESD201: Potential Issues
„
Document allows for test coupons versus actual
components (JESD 22A121-01, sec. 5.1)
„
Document does not specify if components are
discrete (‘loose’) or board-mounted
‰
‰
„
Temperature cycling and elevated humidity exposure of
non-preconditioned discrete parts may not be
representative of storage conditions
Board-mounted parts may not be representative of hand
assembly or repair conditions
Test times are not based on a failure model
‰
© 2005
2004 - 2010
2007
Unable to correlate to time in the field for various use
environments
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62
Part Manufacturer Mitigation
„
Nickel underplate between the tin plating and the copper
leadframe
‰
‰
Some question about effectiveness (IBM vs. TI)
Some question about minimum thickness
„
„
„
„
‰
‰
„
iNEMI article recommends minimum of 2 microns (Smetana,
Global SMT, 6/07)
ATIS requires minimum of 2 microns
PC manufacturer requires 1.2 microns
JP-002 requires 0.5 microns
What if the nickel underlayer cracks?
Might not help for ceramic substrate due to CTE mismatch
Anneal for 1 hour at 150ºC within 24 hours of plating
‰
This is the approach for Freescale
© 2005
2004 - 2010
2007
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63
Part Manufacturer Mitigation (cont.)
„
Fusing (melting of tin through dipping in a hot oil
bath)
‰
„
Excellent field history; must be performed soon
after plating
Minimum plating thickness
‰
© 2005
2004 - 2010
2007
Some question about minimum thickness
„
Telecom manufacturer requires 10 microns
„
JP-002 recommends 7 microns
„
ATIS requires 4 microns (with nickel underplate)
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64
Mitigation (Sn-Bi and Sn-Ag)
„
Some component suppliers
promoting bismuth and silver
additives (1 – 3 wt%)
‰
‰
„
Not as accepted as other mitigation
techniques
However, increasing acceptance by
some OEMs (e.g., Rockwell Collins)
Concerns
‰
‰
‰
Low melting point SnPbBi alloys
Some claim test results
demonstrating this behavior
Others state thermodynamically
impossible below 6 wt%
Gordon, Northrop Grumman
© 2005
2004 - 2010
2007
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65
Part Manufacturer Mitigation (cont.)
„
Some component manufacturers claiming
proprietary whisker-free plating formulation
‰
„
Be skeptical; require Statistical Process Control
Request palladium (Pd) plating – NiPdAu
‰
‰
© 2005
2004 - 2010
2007
Increasingly offered as an option, even to low
volume customers (medical, industrial controls,
etc.)
Most manufacturers have moved to Pd as a
standard plating for fine-pitch components
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66
Mitigation: Lead Frame Platings
Company
Amkor
Package
Plating
Intel
QFP / TSOP
Sn[1]
Samsung
QFP / TSOP
NiPdAu
Texas Instruments
QFP / TSOP
NiPdAu
TSOP (Discretes)
NiPdAu
TSOP (Memory)
SnAg or SnCu
TSOP (LSI)
NiPdAu or SnAg or SnBi
QFP / TSOP
NiPdAu
QFP
Sn or SnPb
TSOP
NiPdAu
QFP
Mostly Sn-Cu, Sn-Bi; some NiPdAu
TSOP
Mostly NiPdAu, with some Sn-Cu, Sn-Bi
QFP / TSOP
Pd or SnPb
QFP
Sn
TSOP
NiPdAu
Hynix
TSOP
SnBi
Freescale
QFP / TSOP
Sn
NEC
QFP / TSOP
Sn, SnBi, or NiPdAu
Micron
TSOP
Sn, SnPb
QFP
Pd
Toshiba
STMicroelectronics
Infineon
Renesas Technology
Sony
Philips/NXP
Palladium and SnBi are seeing an
increasing market share due to
concerns with tin whiskering
Matsushita/Panasonic
TSOP
SnBi
AMD
QFP
Sn, SnCu, or SnPb
IBM
QFP
N/A
Qualcomm
N/A
N/A
QFP
SnBi
TSOP
SnBi
QFP
SnBi, NiPdAu
TSOP
SnBi
Fujitsu
Sharp
© 2005
2004 - 2010
2007
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67
OEM Mitigation
„
Four Options
‰
„
Procurement / Design
‰
‰
‰
„
Procurement, Re-packaging, Post-plate or dip, Conformal coat
Select only components with SnPb or Pd plating
May require complete change in circuit design if alternative
component required
Rarely performed (functionality trumps reliability)
Subcontract packaging or Re-packaging
‰
‰
© 2005
2004 - 2010
2007
SnPb or Pd plated leadframes
Rarely performed (cost, risk of damage)
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68
OEM Mitigation: Post-Plate or Dip Options
„
Reflowing solder
‰
‰
„
Replating (passive components / AEM)
‰
‰
‰
„
Needs bake for enhancing interdiffusion
Hot-tin dipped coating
‰
„
Stripping and refinishing with whisker-free plating material
$0.10 - $0.40 per part (4000 part minimum)
Avnet considering stocking this option (Rollins / Minter)
Lead (Pb) overplating
‰
„
Application of solder over the entire exposed lead
Whiskers do not occur where solder is present
Found not be to effective (iNEMI)
Hot solder dip with SnPb
© 2005
2004 - 2010
2007
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69
OEM Mitigation: SnPb Solder Dipping
„
Initially relevant only to products not covered by RoHS
‰
„
GEIA-STD-0006 (Draft)
‰
„
‰
‰
Gap at component body could still
result in whiskers
Risk of solder bridging and popcorning
on fine pitch; thin components with
large die areas will be problematic
Some programs have erroneously
assumed ‘qualification by similarity’,
both process and part, and ended up
with damaged parts (Rollins / Minter)
Costing (Rollins / Minter)
‰
„
Requirements for Using Solder Dip to Replace the Finish on Electronic Components
Problems may outweigh solution
‰
„
Fine-pitch components now exempt from RoHS
$2.00-3.50 per part for 100,
plus $450-$900 set-up fee
Avnet considering stocking this option (Rollins / Minter)
© 2005
2004 - 2010
2007
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70
OEM Mitigation: Conformal Coating
„
Mitigation #1: Prevention or delay of
whiskering
‰
‰
„
Some indication of 2 - 6 year delay in whiskering
(Rollins / Minter)
NASA reported ~50um polyurethane coating
prevented whisker penetration after 9 years of
office storage
Short tin whiskers will eventually penetrate all
current conformal coatings
‰
© 2005
2004 - 2010
2007
No definitive trend in regards to coating properties
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Conformal Coating (cont.)
2nd International Symposium on Tin Whiskers
„
Mitigation #2: Buckling
‰ Based on calculations (Leidecker, NASA)
‰ Experimentally proven? (Brusse, NASA)
„
Limitations
‰ Insufficient coverage at leads (gravity)
‰ Problems with conformal coat may
outweigh possible risk avoidance
‰ Fine pitch components may have
no air gap!
„
Current status
‰ Development of whisker-resistant coating
„
‰
© 2005
2004 - 2010
2007
Patents filed
Assessment of single vs. double coating
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Leadframe
Conformal Coating
Tin Whisker
Conformal Coating
Leadframe
72
Conformal Coating (NEW)
Woodrow, 2008
© 2005
2004 - 2010
2007
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73
Conformal Coating (NEW)
„
„
„
„
Recent GEIA-Industry Survey (Touw, 2010)
Strong mitigators
‰ Parylene C
‰ Epoxy > 3 mil
Reasonable mitigators
‰ Uralane >1mil
‰ Urethane 1-2mil
‰ Epoxy 1-3mil
‰ Arcylic >2mil
‰ Silicone >3mil
‰ ALD
Weak mitigators
‰ Silicone 2-3mil
‰ Acrylic 1-2mil
© 2005
2004 - 2010
2007
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74
Strong Mitigators (>=4) (NEW)
„
„
„
„
Physical Barrier (1resp <=1)
Hard potting (2 resp <=1)
SnPb dip with Chemical dip (4 resp <=1)
Soldered with SnPb Solder with qualification /
verification of coverage (with or without sampling) (4
resp <=1)
„
Some Conformal Coats
‰
‰
„
Parylene C (1 resp <=1)
Epoxy >3mil (2 resp <=1)
Spacing >500mils (2 resp <=1)
© 2005
2004 - 2010
2007
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75
Reasonable Mitigators (>3) (NEW)
„
„
„
„
„
„
Many Conformal Coats
‰ Uralane >1mil (1 resp <=1)
‰ Urethane 1-2mil (4 resp <=1)
‰ Epoxy 1-3mil (4 resp <=1)
‰ Arcylic >2mil (5 resp <=1)
‰ Silicone >3mil (5 resp <=1)
‰ ALD (2 resp <=1, low response)
Soft potting or encapsulation (6 resp <=1)
Soldered with SnPb without verification on bottom termination or
small leadless chip parts (6 resp <=1)
Spacings 100-500mils (2 resp <=1)
SnPb with 1% to 3% Pb (errors in 3% process) (7 resp <=1)
Component Level Redundancy (2 resp <=1)
© 2005
2004 - 2010
2007
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76
Weak Mitigators (>2) (NEW)
„
„
„
„
„
„
„
„
„
„
„
Spacings 50-100mils (4 resp <=1)
Nickel Underplate (6 resp <=1)
SnPb dip with standoff (7 resp <=1)
Soldering with SnPb on large leadless chip and thru-hole (12 resp
<=1)
SAC finish or dip (with or without standoff) (13 resp<=1)
SnAg finish (11 resp <=1)
Heat treatment above fusing temperature (10 resp <=1)
Some Conformal Coats
‰ Silicone 2-3mil (7 resp <=1)
‰ Acrylic 1-2mil (8 resp <=1)
Styrofoam fillers (9 resp <=1; low response rate)
Avoiding compressive stress (8 resp <=1)
Medium Current (11 resp <=1)
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2007
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77
Very Weak or Non-Mitigators (<2) (NEW)
„
Soldering with SnPb without verification on surface-mount (4 resp
>=4)
„
„
„
„
„
„
„
„
„
Spacing <50 mils (10 resp >=4)
Hot dipped tin (7 resp >=4)
Silver Underplate (1 resp >=4)
SnBi finish (4 resp >=4)
Heat Treatment below fusing (1 resp >=4)
Large grain size or claimed matte tin (1 resp >=4)
Thick Tin (2 resp >=4)
Immersion Tin (1 resp >=4)
<1% Pb (1 resp >=4)
© 2005
2004 - 2010
2007
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78
Tin Whisker Field Failures (post RoHS)
„
Crystal Oscillator
‰
‰
‰
„
‰
Competitors used nickel instead
‰
‰
‰
‰
„
Tin over steel
Time to failure: N/A
Length: ~1.5 mm
Product: Industrial server
‰
‰
„
Bright tin over copper
Time to failure: N/A
Length: ~1.5 mm
Product: Electrical distribution
Connector contact crimped onto a flex circuit
‰
‰
‰
‰
Tin over nickel over copper
Time to failure: Less than 2 years
Length: N/A
Product: Medical
What can we learn from these failures?
‰
‰
„
Time to failure: ~6 months
Length: ~2-3 mm
Product: Appliance controls
D-style connector
‰
RJ45 Connector
Tin over brass (internal surface)
„
‰
„
Concept of critical components works!
All failures are wrong plating (bright), wrong substrate (steel, brass) or involve contact points
Keep a close eye on connectors
© 2005
2004 - 2010
2007
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79
FFC-Touch pad-Interposer board
Connector on Touch
pad
TP to interposer FFC
Interposer to MB FFC
FFC connector on
interposer (Elco)
© 2005
2004 - 2010
2007
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80
Sn Whiskers on SnCu plated Flex
(FPC)
Evidence shows this is where most of the risk lies.
„
Connector contact points
© 2005
2004 - 2010
2007
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81
Sn Whisker on Flex Cables
• JAE evaluated many Sn based finishes but all
showed unacceptable whisker growth.
• Whisker growth was acceptable only if Sn plating
thickness was reduced to below 0.5 microns but
then contact resistance degraded too much with
high temp aging.
• They concluded the following:
Recommendation for high value electronics is to only use gold plating on flex
cables and mated connectors.
Note: a tin plated connector to gold flex cable could result in fretting issues or galvanic corrosion.
© 2005
2004 - 2010
2007
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82
Part Selection
(Misc)
© 2005
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2007
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83
Ceramic Capacitors (Voltage Effect)
„
„
„
High C/V caps can display a significant voltage effect
‰ X5R/X7R (1 µF)
Operating at 80%
of rated voltage can
result in a 75% drop
in capacitance
0603 case size
‰ Similar performance
for 6.3, 10, and 16 VDC
‰ Same capacitor
© 2005
2004 - 2010
2007
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84
Ceramic Capacitors (Cyclic Voltage)
„
„
Reports of field failures of MLCC
in AC or pulsed DC voltage
Piezoelectric effect
‰
‰
„
„
Variant voltage will vary internal
stresses, potentially inducing
fatigue behavior
With high frequency ripple
current, capacitor can vibrate
(resonate).
Fatigued specimens can contain
scattered microcracks
‰
Decrease in capacitance;
increase in leakage current
Concern at hundreds of kHz
‰
‰
http://www.avxcorp.com/docs/techinfo/parasitc.pdf
Decreases with increasing
capacitance, X7R -> Y5V
Avoid or use AC-rated capacitors
Case Size
English
Metric
3025
7563
2220
5750
1812
4532
1210
3225
1206
3216
0805
2012
0603
1608
0402
1005
Resonance Frequency
250 - 750 kHz
300 - 900 kHz
400 - 1200 kHz
600 - 1200 kHz
600 - 1600 kHz
900 - 1800 kHz
N/A
N/A
Nippon Chemi-con, CAT.No.E1002l
© 2005
2004 - 2010
2007
5110 Roanoke Place, Suite 101, College
Park, Maryland 20740
Sang-Joo Kim and Qing Jiangy, Microcracking and electric fatigue of
ferroelectric ceramics, Smart Mater. Struct. 5 (1996)
Phone (301) 474-0607 polycrystalline
Fax (240) 757-0053
www.DfRSolutions.com
85
Resistors (High Resistance)
„
Board surfaces can be susceptible
to periodic SIR drops
‰
‰
‰
‰
„
Can interfere with high resistance
resistors
‰
‰
„
Especially with no-clean
Duration as short as 1 min
Down to 1 megaohm
Fine pitch, high voltage especially
susceptible
Especially chip resistors
Intermittent in nature
Avoid values > 500 kohms if used
for sensing or calibration
‰
‰
© 2005
2004 - 2010
2007
Consider lower values in series
Use guard banding or cutouts
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86
Sulfide Corrosion of Thick Film Resistors
„
Sulfur dioxide (SO2) and hydrogen sulfide (H2SO4)
in environment
‰
‰
‰
„
Sources: Black rubber, industrial pollution
Attacks silver material under passivation/ termination
Creates nonconductive silver sulfide
Drivers
‰
Cracking/separation of coating/termination
„
„
‰
Potting or conformal coating
„
„
„
„
Poor manufacturing
Thermal shock
Seems to act as a ‘sponge’
Holds SO2 molecules in place
Electrical opens within 1-4 years
Avoidance
‰
Orient parallel to solder wave
„
‰
‰
© 2005
2004 - 2010
2007
Entrance side can experience thermal
shock
Avoid hand soldering/rework
Sulfur-resistant PdAg material (KOA)
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87
Tantalum and Polymeric Capacitors
„
„
Tantalum capacitors are
selected for volumetric efficiency
Older technology can be
susceptible to ignition
‰
‰
„
Requires aggressive derating (50%
or greater)
Sensitive to higher temperatures
(>85C) and certain circuits
Newer, polymeric
capacitors are available
‰
‰
‰
© 2005
2004 - 2010
2007
Significant reduction in ESR
Less derating
No risk of ignition
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88
Electrolytic Capacitors
„
Voltage
‰
„
Maintain a minimum of 25-33% of rated
voltage (maintains the dielectric)
Temperature
‰
Maintain adequate distance from ‘hot’
components
„
„
‰
105C rated capacitors can be an issue at
lower temperatures (below -40C)
„
„
ESR increases 500X; capacitance decreases 80-90%
Ripple Current
‰
‰
‰
„
Power resistors, IGBTs, etc.
Seems to accelerate time to failure and can
induce explosive rupturing
Up to 100% or greater of rated ripple current
Need to calculate/measure case temperature rise
Equivalency on bill of materials is often not maintained
Equivalent Series Resistance (ESR)
‰
© 2005
2004 - 2010
2007
Often not specified on the component data sheet
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89
Separable Connectors
„
Separable Connectors
‰
‰
„
One of the most common failure sites
First thing maintenance checks (plug / unplug)
Hardware Design Rules
‰
‰
Blind insertion increases risk of damage or mismating
(consider flex or rigid-flex)
All connectors should be keyed
„
‰
‰
„
Prevents reversal of I/O pins
Use positively retained connectors
Avoid use of sockets
Specify material and thickness
© 2005
2004 - 2010
2007
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90
Separable Connectors [Gold (Au)]
„
Connections and environments
‰
‰
‰
‰
„
Hi-speed digital or critical connections
Low voltage (< 5V), low current (< 10mA)
Corrosive environment (gases such as H2S, SO2, Cl2)
Risk of micromotion (< 2.5 µm)
Material specifications
‰
‰
‰
‰
‰
‰
© 2005
2004 - 2010
2007
Be-Cu or P-bronze base pins
Nickel underplate (250 µin)
Soft gold (Au) plating
10 µin (single insertion); 30 µin
(50 insertions); 70 µin (hi-rel)
Porosity spec
No gold flash
„
Contact specifications
‰
‰
‰
‰
50-100 grams contact force
Minimum of 2 contacts; 4
preferred
Adequate contact wipe –
0.010” min.
No mating with tin plating
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91
Separable Connectors [Tin (Sn)]
„
Connections and environment
‰
‰
„
Power connections
Benign
Tin plating design specification
‰
© 2005
2004 - 2010
2007
100 grams-force, 100 microinches (Tin
Commandments)
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92
DfR (Misc.)
„
Components taller then 1 inch
‰
© 2005
2004 - 2010
2007
Use of staking compound to adhere to board
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93
Derating and Uprating
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2007
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94
Component Ratings
„
Definition
‰
„
A specification provided by
component manufacturers
that guides the user as to
the appropriate range of
stresses over which the
component is guaranteed to
function
Typical parameters
‰
‰
‰
‰
© 2005
2004 - 2010
2007
Voltage
Current
Power
Temperature
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95
Derating
„
Derating is the practice of limiting stress on electronic parts to levels
below the manufacturer’s specified ratings
‰ Guidelines can vary based upon environment
(“severe, protected, normal” or “space, aircraft, ground”)
‰ One of the most common design for reliability (DfR) methods
„
Goals of derating
‰ Maintain critical parameters during operation (i.e., functionality)
‰ Provide a margin of safety from deviant lots
‰ Achieve desired operating life (i.e., reliability)
„
Sources of derating guidelines
rd parties
‰ Governmental organizations and 3
‰ OEM’s
‰ Component manufacturers
„
Derating is assessed through component stress analysis
© 2005
2004 - 2010
2007
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96
Derating Guidelines
„
Government Agencies
Air Force AFSC Pamphlet 800-27 (1983)
‰
„
„
Component Manufacturers
Heavily legacy based
EEE / Mechanical Parts Management &
Implementation Plan for Space Station
NASA Goddard MSFC-3012 (1999)
‰
„
„
NASA Johnson Space Center SSP
30312 (1999)
‰
„
Parts Requirement and Application Guide
Heavily based on MIL standards
3rd Parties
RIAC (Quanterion)
Electronic Parts, Materials, and Processes
for Space and Launch Vehicles
NAVSEA SD-18 (2000)
‰
„
‰
Canceled in 1998; Replaced with NASA
Parts Selection List (NPSL)
MIL-HDBK-1547 (1997)
‰
„
„
MIL-STD-975 (1994)
‰
„
Acquisition Management Part Derating
Guidelines
„
OEMs
Boeing (MF0004-400)
Multiple other OEMs; especially telecom
EEE Parts Management and Control for
Space Flight Hardware
NASA Jet Propulsion Lab JPL-D-8545
(2003)
‰
© 2005
2004 - 2010
2007
Derating Guidelines
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97
Derating Guidelines (Examples)
© 2005
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2007
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98
Criticality of Component Stress Analysis
„
Failure to perform component stress analysis
can result in higher warranty costs, potential
recalls
‰
„
Eventual costs can be in the millions of dollars
Perspective from Chief Technologist at major
Original Design Manufacturer (ODM)
“…based on our experience, we believe a
significant number of field returns, and the
majority of no-trouble-founds (NTFs), are
related to overstressed components.”
© 2005
2004 - 2010
2007
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99
Derating Failures
„
Where are the derating mistakes?
„
Problem #1: Designers do not derate
‰
„
Failure to perform component stress analysis
Problem #2: Derating does not have a
practical or scientific foundation
‰
‰
© 2005
2004 - 2010
2007
Extraordinary measures are taken when
inappropriate
Derating is excessive: ‘The more, the better’ rule
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100
Failure to Derate
„
Analog / Power Designs
‰
‰
„
Derating is typically overlooked during transient
events
Especially turn-on, turn-off
Digital
‰
© 2005
2004 - 2010
2007
Excessive number of components and
connections tends to limit attempts to perform
component stress analysis
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101
Failure to Derate (Case Study)
„
Customers of embedded system industrial
controls experiencing intermittent failures
‰
„
Intensive failure analysis effort ($) and loss of
customers
‰
„
Parametric drift measured on output control lines
Many months to identify the problem
Failure site identified as thick film resistor
© 2005
2004 - 2010
2007
5110 Roanoke Place, Suite 101, College Park, Maryland 20740
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102
Resistors (Pulse Conditions)
„
Minimal variation when
operated within specification
‰
„
Thin film and thick film resistors
use laser trimming
‰
„
‰
Power on, brown-outs, etc.
Up to 350C
Failure mode
‰
„
Resistance adjustment
Can induce hot spots during
transient conditions
‰
„
0.5% at 70C for 30 years
Gradual increase in resistance
Two approaches
‰
‰
© 2005
2004 - 2010
2007
Obtain peak pulse guidelines
Design larger copper bond pads
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Courtesy of S. Silvus
103
The Foundation of Derating
„
To be effective, derating must have a practical and scientific
foundation
‰ Problem: Manufacturer’s ratings are not always based on a
practical and scientific foundation
„
Manufacturers’ viewpoint
‰ Ratings are based on specific design rules based on materials,
process, and reliability testing
„
The reality
‰ Ratings can be driven by tradition and market forces as much as
science
„
Best practice
‰ Based on data from field returns
‰ Based on test to failure qualification (especially for new suppliers)
© 2005
2004 - 2010
2007
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104
Manufacturer’s Derating (example)
„
Tantalum capacitor
‰
„
Derating based on desired
failure rate
‰
„
„
MnO2 cathode
10 ppm at startup
Why not 10 ppm failure
rate at rated voltage?
Was 0.3% failure rate
acceptable?
‰
50% derating is a legacy
Courtesy of Kemet
© 2005
2004 - 2010
2007
5110 Roanoke Place, Suite 101, College Park, Maryland 20740
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105
Scientific Approach to Derating (Ta Caps)
High Impedance Circuits
„
„
„
„
Self healing in Ta capacitors
involves leakage paths in the
MnO2 being healed by the
transformation to the higher
resistance compound Mn2O3
Process requires enough current to allow internal
temperatures to reach 500°C
Small amounts of current (< 50 uA) will prevent self healing
‰ Leads to degradation and potential component failure
Avoid use in circuits with impedances greater than 100 kΩ
© 2005
2004 - 2010
2007
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106
Derating Decision Tree
„
Step 1: Derating guidelines should be based
on component performance, not ratings
‰ Test to failure approach (i.e., HALT of
components)
‰ Quantifies life cycle cost tradeoffs
‰ For smaller OEMs, limit this practice to
critical components
© 2005
2004 - 2010
2007
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107
Derating based on Test to Failure
Derived
Derating
Limit
Manuf.
Rating
Test
Results
Stress
„
„
„
OEM was concerned with voltage rating of tantalum capacitors
after 2 reflows and use on low resistance line
Performed step stress surge test (SSST)
Derived voltage derating based on a sub-ppm failure rate
© 2005
2004 - 2010
2007
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108
Derating Decision Tree (cont.)
„
Step 2: Derating guidelines should be based on
recommendations from the component manufacturer
‰
‰
They built it; they should know it
Don’t trust the manufacturer? Use someone else
„
Step 3: Derating guidelines should be based on
customer requirements
„
Step 4: Derating guidelines should be based
industry-accepted specification/standard
Be flexible, not absolute
© 2005
2004 - 2010
2007
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109
Wearout Mechanisms and
Physics of Failure (PoF)
© 2005
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2007
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110
Physics of Failure: Reliability Assurance
„
Reliability is the measure of a product’s ability to
‰
‰
‰
„
…perform the specified function
…at the customer (with their use environment)
…over the desired lifetime
Physics of failure therefore requires an
understanding of the desired lifetime and the use
environment
‰
‰
© 2005
2004 - 2010
2007
Desired lifetime: When the customer will be satisfied
Use environment: Must include assembly, transportation,
storage, operation
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111
PoF-Based Reliability Prediction
„
All physics-of-failure (PoF) based models are
semi-empirical
‰
‰
„
Calibration testing should be performed over several
orders of magnitudes
‰
„
The basic concept is still valid
Requires calibration
Allows for the derivation of constants
The purpose of PoF is to limit, but not eliminate, the
influence of material and geometric parameters
‰
© 2005
2004 - 2010
2007
E.g., Solder: Testing must be re-performed for each package
family (ball array devices, gullwing, leadless, etc.)
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112
Failure Rate
Why is PoF Important?
Electronics: Today and the Future
Electronics: 1960s, 1970s, 1980s
Wearout!
No wearout!
Time
© 2005
2004 - 2010
2007
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113
Physics of Failure (PoF) Algorithms
⎛ ~ 0.51eV ⎞
T f ∝ exp⎜
⎟ × exp(~ −0.063% RH )
kT
⎠
⎝
n
t1 ⎛ V2 ⎞
E ⎛1 1⎞
= ⎜⎜ ⎟⎟ exp a ⎜⎜ − ⎟⎟
t 2 ⎝ V1 ⎠
K B ⎝ T1 T2 ⎠
⎛ L
⎛ 2 −ν ⎞ ⎞
h
h
L
⎟⎟ ⎟
+
+ s + c + ⎜⎜
⎟
⎝ E1 A1 E2 A2 As Gs Ac Gc ⎝ 9 ⋅ Gb a ⎠ ⎠
(α 2 − α1 ) ⋅ ∆T ⋅ L = F ⋅ ⎜⎜
Can be mind-numbing! What to do?
© 2005
2004 - 2010
2007
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114
PoF and Wearout
„
What is susceptible to long-term degradation in electronic designs?
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
‰
© 2005
2004 - 2010
2007
Ceramic Capacitors (oxygen vacancy migration)
Memory Devices (limited write cycles, read times)
Electrolytic Capacitors (electrolyte evaporation, dielectric dissolution)
Resistors (if improperly derated)
Silver-Based Platings (if exposed to corrosive environments)
Relays and other Electromechanical Components
Light Emitting Diodes (LEDs) and Laser Diodes
Connectors (if improperly specified and designed)
Tin Whiskers*
Integrated Circuits (EM, TDDB, HCI, NBTI)
Interconnects (Creep, Fatigue)
Industry-accepted models exist
„
Plated through holes
„
Solder joints
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115
Part Selection
(Lifetime)
© 2005
2004 - 2010
2007
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116
Lifetime Example: Memory Devices
„
„
Limited lifetime based on read-write cycles and retention time
Parameter
Minimum Guarantee
Units
Endurance
100,000
Data changes per bit
Store cycles
1,000,000
Store cycles
Data retention
100
Years
Some memory devices provide data retention time for different
operating temperatures (20 years at 125°C and 10 years at
150°C).
© 2005
2004 - 2010
2007
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117
Light and Laser Diode Wearout
„
„
Increasing importance with adoption of optical communications and
LCD backlight
Standard model for on-die wearout is:
⎛ Ea ⎞
t f = A( J ) exp⎜ ⎟
⎝ kT ⎠
n
„
where A is a constant, J is the current density, n is an exponent
‰
‰
„
Expression applies for units run in automatic current control (ACC), or
constant current.
‰
‰
„
n =1.5 - 2 for a large number of different LED structures
n = 6 – 7 for laser diodes with facet passivation
Units run at constant output power (APC), power substitutes current density
(n may be higher)
Some models will combine power and current density
Note: Model does not apply to die attach fatigue
‰
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2007
A risk in high power, cyclic applications
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Light and Laser Diode Wearout
(cont.)
„
Estimated lifetime is
not always provided
„
When lifetime is provided,
it is MTBF at room temp.
‰
‰
‰
„
Time to 5% failure can be
half the time
Time to failure at 40C can
be half the time
50K hrs can turn into 12.5K hrs
Lifetime is not always be equivalent to failure
‰
© 2005
2004 - 2010
2007
50% reduction in intensity
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119
Lifetime Example: Relays/Switches
„
„
Relays are an
electromechanical switch
Minimum of four I/Os
‰
‰
„
Control voltage
Signal voltage
What are the major
concerns in regards to relay
reliability?
‰
‰
‰
© 2005
2004 - 2010
2007
Number of cycles to failure
Long-term non-use
Power dissipation and
contact resistance (heating
and voltage drops)
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Relays/Switches (cont.)
„
„
„
„
„
Selection of appropriate plating
‰ Idle for long periods of time: Gold contacts
‰ Numerous cycles: AgCd contacts
Sealed packages if cleaning operations
Use of protective devices
‰ Diode, resistor, capacitor, varistor, etc.
‰ Prevents arcing during switching (accelerates degradation)
‰ Must be nearby
Temperature rise
‰ Wide range of contact resistance in specifications
Ensure margin between design life requirements and
manufacturer’s specifications
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Wearout of Relays/Switches
100%
Cumulative Failures %
90%
Catalog Life =
100,000 Cycles
Mean Time Between
Failures = 102,900
80%
70%
60%
50%
Characteristic
Life = 113,545
40%
30%
20%
10%
0%
60,000
70,000
80,000
90,000
100,000
110,000
120,000
130,000
Number of Cycles
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122
Lifetime Example: Ceramic Capacitors
„
Ceramic caps are typically not expected to experience
‘wearout’ during normal operation
n
Ea ⎛ 1 1 ⎞
t1 ⎛ V2 ⎞
⎜⎜ − ⎟⎟
= ⎜⎜ ⎟⎟ exp
t 2 ⎝ V1 ⎠
K B ⎝ T1 T2 ⎠
„
„
where t is time, V is voltage, T is temperature (K), n is a
constant (1.5 to 7; nominally 4 to 5), Ea is an activation energy
(1.3 to 1.5) and KB is Boltzman's constant (8.62 x 10-5 eV/K)
Lifetime may be limited for extended value capacitors
‰
‰
© 2005
2004 - 2010
2007
Sub-2 micron dielectric thickness
Greater than 350 layers (increased failure opportunity)
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Voltage
Derating
Temperature
Mfg. A
Mfg. B
Mfg. C
Mfg. D
0.8
60oC
145
340
655
285
„
Difference between MTTF and t5% is a factor of 40
‰
For a design with 20 ceramic capacitors, all product could fail within 3 - 15 yrs
Randall, et. al., CARTS 2003
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„
Voltage
Derating
Temperature
Mfg. A
Mfg. B
Mfg. C
Mfg. D
0.8
60oC
145
340
655
285
Extrapolation can result in a factor of 250 difference between MTTF and t1%
‰
1% failure rate in less than 10 years in benign conditions (0.5 derating, 45oC)
Randall, et. al., CARTS 2003
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125
Ceramic Capacitor Wearout (cont.)
„
„
When to be concerned?
Dielectric thickness less
than 2 - 3 microns
‰
Approx. 2 - 10 µF/mm3
http://www.murata.com/articles/ta0463.pdf
„
Case size/capacitance guide
‰
X7R
„
‰
X5R/Y5V
„
© 2005
2004 - 2010
2007
0402 > 0.05 µF; 0603 > 0.2 µF; 0805 > 1 µF; 1206 > 5.6 µF
0402 > 0.5 µF; 0603 > 2 µF; 0805 > 5.6 µF; 1206 > 16 µF
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126
Desired Lifetime (IC Wearout)
Process Variability
confidence bounds
1000
100
Airplanes
Mean
Service 10
life, yrs.
Computers
laptop/palm
cell phones
1.0
0.1
Technology
0.5 µm
0.25 µm
1995
130 nm
65 nm
2005
Year produced
35 nm
2015
Known trends for TDDB, EM and HCI degradation
(ref: extrapolated from ITRS roadmap)
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127
IC Wearout: Background
Guaranteeing the conventional 10-year life of ICs is going to become increasingly
difficult….the progressive degradation of the electrical characteristics of transistors and wires
will start dominating over abrupt functional failures. Furthermore, the mean-time-to-first-softbreak will significantly diminish."
Antonis Papanikolaou, IMEC, Leuven, Belgium, 2007
…the progress of Moore's Law means that transistor wear-out and statistical performance
issues are beginning to cross over from the realm of academic and hypothetical discussion to
real-world R&D engineering.
EE Times Europe, 2007
”The notion that a transistor ages is a new concept for circuit designers,” says Chris Kim (U of
Minnesota). Transistor aging has traditionally been the bailiwick of engineers who design the
processes that make transistors; they also formulate recipes that guarantee the transistors will
operate within a certain frequency and other parameters typically for 10 years or so…But as
transistors are scaled down further and operated with thinner voltage margins, it’s becoming
harder to make those guarantees… transistor aging is emerging as a circuit designer’s
problem.
IEEE Spectrum, June 2009
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128
IC Wearout (cont.)
10
FIT (000)
8
Dielectric
breakdown
failure rate vs.
feature size
Future…
In
design
6
4
It is becoming more challenging to achieve very
high reliability for products made with advanced
technologies (90nm and smaller)
Phil Nigh, IBM Microelectronics
Estimated
In
production
2
0
Measured
180
130
90
65
45
Feature size, nm
“failure rate increases as we scale to smaller
technologies…hard failures will present a
significant and increasing challenge in future
technology generations.”
Pradip Bose, Jude A. Rivers, et al., IBM T.J.
Watson Research Center
Increasing need for
Repairable electronics
Disposable electronics
Fault-tolerant electronics
Figure adapted from industry published data, 2008
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Industry Testing Falls Short
„
Limited degree of mechanism-appropriate testing
‰
‰
‰
„
Only at transition to new technology nodes
Mechanism-specific coupons (not real devices)
Test data is hidden from end-users
Questionable JEDEC tests are promoted to OEMs
‰
‰
© 2005
2004 - 2010
2007
Limited duration (1000 hrs) hides wearout behavior
Use of simple activation energy, with incorrect assumption
that all mechanisms are thermally activated, can result in
overestimation of FIT by 100X or more
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Generic CMOS Wearout Models
EM:
HCI:
TDDB:
NBTI:
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Electromigration
„
Occurs when collisions of electrons cause metal
atoms in a conductor to dislodge and move
downstream of current flow (proportional to current
density)
„
Electromigration primarily controlled through
design rule checks
‰
Certain architectures are immune
„
‰
© 2005
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2007
Polygons around an angle
versus sharp angles
Increasing concerns with
via connections
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Time Dependent Dielectric Breakdown
„
Degradation occurs when electric fields from charges
trapped in various parts of the oxide exceed dielectric
breakdown
„
Feature scaling
‰
‰
‰
‰
Gate dielectric (oxide)
thickness is scaled down
Power supply voltage is
approximately the same as
previous node
Increase in electric field on
gate dielectric
Breakdown is becoming a
constant failure rate
(independent of time)
© 2005
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2007
Weibull Beta values as observed by Wu et al (IBM)
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Electron Tunneling
„
Similarities of HCI and NBTI
‰
‰
‰
Dependent on the electric field from the gate
Phenomenon of electrons and holes (carriers) gaining
sufficient energy to overcome the direction of induced
current and become injected in the gate oxide
Degradation exponentially increases after the first injection
occurrence
Depiction of hot carrier
effects on MOSFET
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Hot Carrier Effects
„
Hot Carrier Effects or Injection (HCI) Characteristics
‰
‰
„
HCI has inverse Arrhenius relationship
‰
‰
„
Caused by a single carrier gains sufficient kinetic energy, or
Multiple carriers undergoing collisions that force them out of the
directional path of electric field
Activation energy -0.2 to -0.1 eV
Lower temperatures ( ~35 to ~55°C) increase vulnerability
Probability of HCI increases with increases in bias voltage
and cyclic changes in bias voltage (switching on/off)
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Bias Temperature Instability
„
Combined bias-temperature stress is required for activation
‰
‰
Affects transistors that are turned-on
Fluctuations in temperature
„
‰
„
Noticeable influence on failure rate in submicron nodes
Trap formation from electric fields are worse under
negative bias
‰
„
High temperatures cause molecular instability
Requires lower electric fields than HCI
‰
„
overall device + self heating property
PMOS transistors with negative gate voltage
The molecular instability strongly increases with temperature
and higher negative gate bias
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136
Multiple Mechanism Theory
„
Simultaneous influence of multiple failure mechanisms
‰
‰
‰
‰
„
Electromigration (EM)
Time Dependent Dielectric Breakdown (TDDB)
Negative Bias Temperature Instability (NBTI)
Hot Carrier Injection (HCI)
Each mechanism is driven by different conditions
‰
‰
‰
Activation energy
Electrical and thermal conditions
Transistor use conditions
„
© 2005
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2007
switching vs. constant bias
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Validation Study
„
„
Field return data was gathered from a family
of telecommunication products
‰ 56 different ICs comprised 41.5%
of the failed part population
The validation activity was utilized failure data
from 5 integrated circuits
CAP
1%
TRANSISTOR
19%
RESONATOR
6%
CARD
44%
RESISTOR
8%
INDUCTOR
0.07%
IC
21%
FUSE
0.54%
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DIODE
0.13%
FILTER
0.02%
138
Failure Rate Calculation
„
Failure rate was calculated from raw data
‰
‰
‰
Environmental conditions to determine in-field operating
temperature
Thermal measurements to determine power dissipation
Cumulative failure distributions
Weibull
Exponential
„
„
Probability Plot for Days
Probability Plot for Days
Exponential
Censoring Column in Censor - LSXY Estimates
Weibull - 95% CI
Censoring Column in Censor - LSXY Estimates
Table of S tatistics
S hape
1.02661
S cale
118401
M ean
117136
S tD ev
114111
M edian
82853.1
IQ R
127575
F ailure
96
C ensor
9099
A D*
2501.362
C orrelation
0.989
Probability
0.2
0.05
0.02
0.01
0.95
0.8
Table of S tatistics
M ean
141824
StD ev
141824
M edian
98305.0
IQ R
155810
F ailure
96
C ensor
9099
A D*
2501.362
0.5
0.2
Probability
0.95
0.8
0.5
0.05
0.02
0.01
0.0001
0.0001
0.
1
0
1.
.0
10
0.
10
0
00
10
.0
Days
0
0.
00
10
0
10
0.
00
0
0
10
00
00
.0
1
10
100
1000
Days
10000
100000 1000000
Failure distribution graphs for part: Freescale Microcontroller
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Lifetime Prediction
„
„
Determine functional group breakdown (component complexity)
Calculate HTOL test ambient operating temperature
‰
‰
„
Thermal resistance (junction to ambient)
Power dissipation (PD, or Vdd(max) * Idd)
Uses operating conditions and HTOL test conditions
Part Number
MT16LSDF3264HG-10EE4
M470L6524DU0-CB3
HYMD512M646BF8-J
MC68HC908SR12CFA
RH80536GC0332MSL7EN
© 2005
2004 - 2010
2007
Field Temperature
(°C)
42
42
42
40
58
Calculated Test
Temperature (°C)
62.28
70.00
66.68
77.40
99.70
Vdd Field (V) Vdd Test (V)
3
2.5
2.6
5
1.276
3.3
2.7
2.7
5.5
1.34
Functional Groups
DRAM: 268435456 bits
DRAM: 536870912 bits
DRAM: 1073741824 bits
microcontroller: 512B RAM, 10-bit ADC
microprocessor: 2080KB RAM
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Results of Validation Study
„
Results demonstrate the accuracy and repeatability of the
multi-mechanism model to predict the field performance of
complex integrated circuits
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141
Solder Wearout (1st and 2nd Level)
„
Component Packaging Requirements
Higher frequencies and data transfer rates
‰
„
Tradeoff between ‘hard’ and ‘soft’ underfills
‰
„
More inside less
Lower voltage, but higher current
‰
„
Solder wearout vs. cracking of high-K dielectrics
Higher densities
‰
„
Lower resistance-capacitance (RC) constants
Joule heating is I2R
Has resulted in less robust package designs
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142
Solder Wearout (cont.)
„
Elimination of leaded devices
‰
‰
Provides lower RC and higher package densities
Reduces compliance
Cycles to failure
-40 to 125C
© 2005
2004 - 2010
2007
QFP: >10,000
BGA: 3,000 to 8,000
CSP / Flip Chip: <1,000
QFN: 1,000 to 3,000
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Solder Wearout (cont.)
„
„
Design change: More silicon, less plastic
Increases mismatch in coefficient of thermal
expansion (CTE)
BOARD LEVEL ASSEMBLY AND RELIABILITY
CONSIDERATIONS FOR QFN TYPE PACKAGES,
Ahmer Syed and WonJoon Kang, Amkor Technology.
© 2005
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2007
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Solder Wearout (cont.)
„
Hotter devices
‰
Increases change in temperature (∆T)
tf = ∆Tn
n = 2 (SnPb)
n = 2.3 (SnNiCu)
n = 2.7 (SnAgCu)
Characteristic Life (Cycles to Failure)
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
50
100
150
200
o
Change in Temperature ( C)
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Alternatives to PoF
„
„
Step 1: Rules of Thumb
Step 2: Best Practice
‰
„
Follow part selection guidelines
Step 3: Norris-Landsberg
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146
Rules of Thumb (Constant Temperature)
„
Electrolytic Capacitor lifetime
becomes an issue when ambient
temperatures begin to exceed
40C on a constant basis
‰
„
85C/2000 hour ratings tend to be
insufficient for more than 5 year life
Many companies limit solder joint
temperature to a maximum of 75ºC – 85ºC
‰
© 2005
2004 - 2010
2007
Some limit IC junction temperature to a similar
range
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Rules of Thumb (Temperature Cycling)
„
In nominal environments, solder joint wearout is
unlikely
‰
‰
‰
„
Low power, diurnal cycling
∆25C, 1 cycle per day
Lifetime of less than 10 years
Greater concerns in more severe environments
‰
‰
‰
© 2005
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2007
Diurnal heat sources with sufficient fluctuation (∆40C)
Diurnal power dissipation of ∆40C and greater
Power cycling greater than 4 cycles/day (mini-cycling)
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Rules of Thumb (Temp Cycling)(cont.)
„
If a solder joint fatigue is a concern, manage
package styles
‰
‰
‰
‰
‰
© 2005
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2007
MELF parts (SMA and SMB available)
Crystals on ceramic substrates (especially large
ones)
Chip resistors greater than 1812 or capacitors
greater than 2225
Large memory devices (44, 56, 66 I/O) with Alloy
42 leadframes
Large I/O (≥ 44) quad flat pack no-lead (QFN)
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Rules of Thumb (Vibration)
„
Maintain high board natural
frequency
‰
‰
„
Two to three times greater than low
frequency peaks (>250-300 Hz)
Use of attachments, stiffer rail
guides
When peaks in the power spectral density
(PSD) curve exceeds 0.01 G2/Hz
‰
© 2005
2004 - 2010
2007
Lower threshold for higher frequency peaks
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Vibration (cont.)
„
„
Failures primarily occur when peak loads
occur at similar frequencies as the natural
frequency of the product / design
Natural frequencies
‰
‰
‰
‰
© 2005
2004 - 2010
2007
Larger boards, simply supported: 60 – 150 Hz
Smaller boards, wedge locked: 200 – 500 Hz
Gold wire bonds: 2k – 4kHz
Aluminum wire bonds: >10kHz
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151
Norris-Lanzberg (SnPb)
1/ 3
No ⎛ fo ⎞
= ⎜⎜ ⎟⎟
AF =
Nt ⎝ ft ⎠
„
“o” refers to operating environment and “t” refers to test
environment
Provides comparison of test results to field reliability
‰
‰
„
⎞⎤
⎟⎥
⎟
⎠⎥⎦
f is cycling frequency, ∆T is change in temperature, and Tmax
is the maximum temperature
‰
„
⎡
⎛ 1
⎛ ∆Tt ⎞
1
⎜⎜
⎟⎟ exp ⎢1414⎜
−
⎜
⎢⎣
⎝ ∆To ⎠
⎝ Tmax,o Tmax,t
2
Usable if the component manufacturer provides accelerated life
testing (ALT) results for 2nd level interconnects
Warning: Component manufacturers can cheat (use very thin
boards)
Can not provide an absolute prediction
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152
Norris-Lanzberg (SAC)
N o ⎛ ∆Tt ⎞
⎟⎟
AF =
= ⎜⎜
Nt ⎝ ∆To ⎠
„
⎛ tt ⎞
⎜⎜ ⎟⎟
⎝ to ⎠
0.136
⎧⎪
⎞⎫⎪
⎛ 1
1
⎟⎬
exp⎨2185⎜⎜
−
⎟⎪
T
T
⎪⎩
max,
o
max,
t
⎠⎭
⎝
t is the hot-side dwell time, ∆T is change in
temperature, and Tmax is the maximum temperature
‰
„
2.65
“o” refers to operating environment and “t” refers to
test environment
Not yet widely accepted
‰
Found to be inaccurate within some datasets
1
N. Pan et al, “An Acceleration Model For Sn-Ag-Cu Solder Joint Reliability Under Various Thermal Cycle Conditions”.
pp. 876-883, SMTAI, September 2005, Chicago, IL
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153
Long-Term Reliability
„
Rules of Thumb, Best Practices, and NorrisLandzberg are not always sufficient
‰
„
Good first pass
When the risk is too high, physics of failure
(PoF) calculations are irreplaceable
‰
‰
‰
© 2005
2004 - 2010
2007
Need to understand the basis for PoF models
(broad range of test results)
Trends are more important than single set of test
data
PoF Example: Pb-Free Solder
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154
Physics of Failure
(Pb-Free Solder – Thermal Cycling)
© 2005
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2007
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155
Long-Term Reliability of Pb-free
„
How to develop PoF for Pb-free Solder?
As specified in GEIA-STD-0005-1:
‰
‰
‰
‰
„
Test and analysis
Knowledge of environmental and operating conditions
Reliability data (test or in-service)
Extrapolation of reliability data to applicable conditions
(acceleration factor)
Translation: Understand how Pb-free material fails and
determine if / when these mechanisms will initiate in your
design in the customer’s use environment over the
lifetime of the product
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2007
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156
Thermal Cycling
„
Thermo-mechanical fatigue of
solder joints is one of the
primary wear-out mechanisms
in electronic products
‰
„
May be changing
Especially true in products used
outside of commercial/
consumer environments
‰
‰
© 2005
2004 - 2010
2007
Longer required lifetime
More severe operating conditions
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157
Thermal Cycling: SnPb vs. SAC
„
Where does SnPb outperform Pb-free?
„
Leadless, ceramic components
‰
‰
‰
„
Leadless ceramic chip carriers (crystals, oscillators, resistor
networks, etc.)
SMT resistors
Ceramic BGAs
Severe temperature
cycles
‰
‰
-40 to 125ºC
-55 to 125ºC
Syed, Amkor
© 2005
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2007
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158
Thermal Cycling: SnPb vs. SAC (Cont.)
„
Pb-free alloy exhibits a higher acceleration factor
‰
© 2005
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2007
Failures under accelerated life testing (ALT) equivalent to longer field life
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159
Thermal Cycling: SnPb-SAC Transition
I. Kim, ECTC 2007
© 2005
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2007
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160
Thermal Cycling: Stress Relaxation
„
Pb-free alloys demonstrate higher creep resistance
‰
‰
When will Pb-free be less reliable in the field?
Stress
„
Results in greater durability under accelerated testing (fast ramps, short dwells)
Exception: Very high temperatures (>125oC), high stress loadings (leadless, ceramic)
SAC
SnPb
Temperature
Time
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161
Thermal Cycling: Effect of Dwell Time
10
Based on creep laws developed by Schubert
and damage model developed by Syed
SAC life / SnPb life
8
6
2512 Resistor on FR4
25 to 80C (modeling, Blattau, 2005)
4
Ceramic BGA on FR4
0 to 100C (experimental data, Bartello, 2001)
2
0
0
100
200
300
400
500
Dwell Time (min)
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162
Test
Life Requirement
Test
Spec
∆ Temperature
Thermal Cycling: When is a Failure Not a Failure?
Field Condition
SnPb
Pb-Free
Time to Failure
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2007
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163
Thermal Cycling: Study on SnAgCu Solder
„
Data gathering
‰
‰
„
Time to failure data for Pb-free solder under a variety
of standard test conditions
Two parameter Weibull model (characteristic life,
shape parameter)
Focused on:
‰
‰
‰
© 2005
2004 - 2010
2007
BGA (area array devices – CSP, PBGA, CBGA)
Thin-Shrink Small Outline Package (TSSOP)
Leadless chip resistors, 2512 and 1206
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164
Resistor – Cycles to Failure
1206 Case Size
2512 Case Size
Characteristic Life (Cycles to Failure)
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
50
100
150
200
Change in Temperature (oC)
© 2005
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2007
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165
TSSOP – Cycles to Failure
Characteristic Life (Cycles to Failure)
10000
Type 1
Type 2
Type N/A
9000
8000
7000
Type 1
6000
5000
4000
3000
2000
1000
Type 2
0
0
50
100
150
200
Change in Temperature (oC)
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2007
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166
BGA Results
Normalized Characteristic Life
10
Life as a function of
delta T from tests in
which two or more
thermal profiles
were used, includes
CSP, PBGA and
CBGA data
y = 301550x-2.7427
1
0.1
10
100
1000
Change in Temperature (oC)
AN ACCELERATION MODEL FOR Sn-Ag-Cu SOLDER JOINT
RELIABILITY UNDER VARIOUS THERMAL CYCLE CONDITIONS
N. Pan, G. A. Henshall, F. Billaut, S. Dai, M. J. Strum, R. Lewis, E. Benedetto, J.
Rayner
© 2005
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2007
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167
Thermal Cycling: Effect of Dwell Time
Normalized time to failure as a function of dwell time at
maximum temperature for SAC solder
• 40% to 60% drop in the number of cycles to failure as dwell is increased past 8 hours
• As the CTE mismatch decreases and the part becomes more compliant, the effect of
dwell decreases
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2007
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168
Long-Term Dwell
„
Flip-chip BGA
‰
„
„
(-25C) to 100C
Both SAC and SnPb
experienced shorter
time to failure when
exposed to long-term
dwells
Rate of degradation was faster for SAC
‰
SAC still far superior to SnPb
Intel Technology Journal, Materials Technology for Environmentally Green Micro-electronic Packaging, Volume 12, Issue 01, 2-21-2008
Vasu Vasudevan et al., "Slow Cycle Fatigue Creep Performance of Pb-free (LF) Solders," ECTC, 2008.
© 2005
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2007
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169
SnPb vs. SAC: Resistors
10000
SAC (75%)
SnPb
SAC (50%)
Time to 1% Failure (Cycles)
9000
8000
7000
Time to 1% failure for
2512 resistors
attached with SAC or
SnPb solder and
subjected to long
dwells (~8 hours)
6000
5000
4000
3000
2000
1000
0
0
20
40
60
80
100
o
Change in Temperature ( C)
© 2005
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2007
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170
SnPb vs. SAC: TSOP
10000
SAC (75%)
SnPb
SAC (50%)
Time to 1% Failure (Cycles)
9000
8000
7000
Time to 1% failure for
TSOPs attached with
SAC or SnPb solder
and subjected to long
dwells (~8 hours)
6000
5000
4000
3000
2000
1000
0
0
20
40
60
80
100
o
Change in Temperature ( C)
© 2005
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2007
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171
SnPb vs. SAC: Area Array Devices
2.5
SAC Life / SnPb Life
2.0
1.5
1.0
0.5
0.0
0
2000
4000
6000
8000
10000
12000
14000
16000
Characteristic Life (Cycles)
Ratio of SAC/SnPb reliability for area array devices as a function of
characteristic lifetime of the SAC component
© 2005
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2007
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172
SnPb vs. SAC: Findings
„
2512 Resistors and TSOPs with Alloy42 leadframes
have limited lifetimes
‰
‰
500 cycles of -40 to 125ºC
1500 cycles of 0 to 100ºC
„
Long dwells up to 8 hours would be expected to reduce
lifetime between 40 and 60%
„
Once long dwell and differences in shape parameters
are taken into account, there is likely to be minimal
statistical difference between SAC and SnPb in most
operating environments
© 2005
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2007
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173
2nd Generation Solders
„
Reliability data on 2nd generation Pb-free alloys
(non-SAC) are relatively scarce
„
DfR recently completed accelerated life testing on
Ni-modified SnCu (SN100C)
‰
Three package styles
„
„
„
‰
Three test environments
„
„
„
© 2005
2004 - 2010
2007
Leadless: 2512 Resistor
Leaded: 44 I/O TSOP
Ball: 98 I/O CSP
Temperature cycling
Vibration
Mechanical shock
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174
Results: Thermal Cycling - Resistor
Resistor samples
exposed to ∆T of
75°C (blue), 100°C
(red and green) and
165°C (violet).
Dwell time has a
minimal effect on
time to failure.
Time to 1% failure
of 2000 cycles
matches
expectation of
SnPb and SAC305
© 2005
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2007
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175
Results: Thermal Cycling – TSOP, all solders
TSOP samples
exposed to ∆T of
165°C soldered with
SAC (blue), SN100C
(green) and SnPb
(red).
Characteristic life
(eta, η) and shape
factor (beta, β) are
nearly identical.
Tails may indicate
infant mortalities
(defect driven).
© 2005
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2007
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176
Results: Thermal Cycling – CSP, all solders
CSP samples
exposed to ∆T of
165°C soldered with
SAC (blue), SN100C
(green) and SnPb
(red).
Characteristic life
(eta, η) is nearly
identical for SAC and
SnPb, with SN100C
marginally higher.
© 2005
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2007
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177
Expected Field Failure Time (1%)(NEW)
n = 2.18
n = 1.75
n = 1.55
© 2005
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2007
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178
Estimation for 1% Field Failure Rate
© 2005
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2007
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179
2nd Gen Pb-Free Solders (cont.)
„
Study of certain Pb-free solders (SAC and SNC) strongly
suggests they should provide similar or better reliability
than SnPb
‰
‰
„
Requires no manufacturing defects
Does not include environments with drop/mechanical shock
SNC may be an appropriate middle ground between
SnPb and SAC
‰
‰
‰
© 2005
2004 - 2010
2007
Not as brittle as SAC
More creep resistant than SnPb
Widely accepted in wave solder and HASL processes
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180
Flip Chip (1st Level Interconnects)
„
There is limited test data on thermal cycling
reliability of Pb-free flip chip solder bumps
‰
„
Scenario 1
‰
‰
„
Partially driven by existing exemption
Underfill properties dominate solder bump performance
Changes from high-Pb to Pb-free would be a second-order
effect
Scenario 2
‰
‰
© 2005
2004 - 2010
2007
Potential for 1 – 3 addition reflows (SMT, rework)
Could have detrimental effect through dissolution of plating,
thick intermetallics, etc.
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181
Physics of Failure
(Pb-Free Solder – Mechanical Cycling)
© 2005
2004 - 2010
2007
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182
Fatigue: Overview
„
Mechanical fatigue failures occur due to low cycle/high
amplitude events (shock) and high cycle/low amplitude
events (vibration)
„
Limited number of studies completed to assess the
performance of Pb-free under high-cycle fatigue
‰
„
Initial understandings of failure behavior based on limited number
of publications and results of internal testing
Two approaches
‰
‰
© 2005
2004 - 2010
2007
Bend cycling
Vibration testing
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183
Mechanical Cycling (Background)
„
Lifetime under mechanical cycling is
divided into two parts
Low cycle fatigue (LCF)
High cycle fatigue (HCF)
‰
‰
„
Fatigue of Structures and Materials,
J. Schijve, Springer, 2001
LCF is driven by plastic strain
(Coffin-Manson)
ε p = ε f (2 N f ) c
-0.5 < c < -0.7; 1.4 < -1/c < 2
„
HCF is driven by elastic strain
(Basquin)
εe =
σf
E
(2 N )
b
f
-0.05 < b < -0.12; 8 < -1/b < 20
© 2005
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184
Fatigue: Background
„
Most test results plot life as a function of boardlevel strain
‰
„
Equivalent to solder strain only in the elastic regime
Bend cycling is ½ to ¼ less severe than vibration
‰
© 2005
2004 - 2010
2007
Not fully reversed
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185
Fatigue: Bend Cycling (KAIST)
„
Test sample
‰
‰
„
1.27mm pitch 256 I/O BGA (27 x 27 mm)
90-mil (2 mm) printed circuit board
Test setup
‰
‰
‰
© 2005
2004 - 2010
2007
Span of 100 mm
Frequency N/A
Loads 25 to 60 N
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186
Fatigue: Bend Cycling (KAIST)
100
SnPb
nSnPb = 2.9
nSAC = 4.2
Applied Load (N)
SAC405
Seems to display transition
or high-cycle behavior
(good fit to MIL-STD-810)
10
1.E+03
1.E+04
1.E+05
1.E+06
Time to Failure (Cycles)
I. Kim, ECTC 2007
© 2005
2004 - 2010
2007
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187
Fatigue: Bend Cycling (Motorola)
Test sample
‰
‰
„
Test setup
‰
‰
‰
„
0.8mm pitch 179 I/O BGA (14 x 14 mm)
22-mil (0.56 mm) printed circuit board
Span of 44 mm
Frequency of 1Hz
Displacements
0.2 to 0.5 mm
Results
‰
SnPb ≈ SAC
Board Level Strain (microstrain)
„
SnPb
SAC
Motorola
1400
1200
1000
800
600
400
200
0
1,000
10,000
100,000
1,000,000
Fatigue Life (cycles)
© 2005
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2007
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188
Fatigue: Bend Cycling (DfR Solutions)
„
Test sample
‰
‰
„
2512 chip resistors
(6.25mm x 3mm)
62-mil (1.5 mm) PCB
Strain (µε)
SnAgCu
SnPb
800
2,929,200
1,870,00
1200
69,399
26,395
2400
10,508
7,732
19,485
Test setup
‰
‰
‰
© 2005
2004 - 2010
2007
SnPb
Span of 100 mm
Frequency 4 Hz
Board level strain
800 to 2400 µε
SAC305
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189
Fatigue Predictions Using Coffin-Manson
SnPb
SAC305
© 2005
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2007
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190
Vibration (JGPP)
„
„
„
„
Random Vibration
‰ 9.8 to 28 Grms (0.07 to 0.5 G2/Hz)
Natural Frequency (72 Hz)
Results
‰ With BGA’s, SnPb solder always
outperformed lead-free
‰ Less conclusive for leadless/
leaded parts
Some MAS companies are using
these results to incorrectly conclude
SnPb is better than SAC in
vibration
All BGA-225
© 2005
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2007
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Woodrow, IPC/APEX 2006
191
Fatigue Exponent – Coffin Manson
„
„
Assume the solder
strain is directly
proportional to the
board level strain
Coffin – Manson
N field
N test
„
Fit to data provides c = 1.5
‰
„
⎡ ε test ⎤
=⎢
⎥
⎢⎣ ε field ⎥⎦
c
Exponent value is too low; representative of low-cycle fatigue
High-cycle fatigue exponent is typically 4 to 6 or higher
‰
MIL-STD-810, Steinberg
© 2005
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192
Fatigue: Intel Vibration Study
„
Sinusoidal Vibration
‰
„
0.75g to 4.0g input
Note change in Pb-free behavior at
high loads, compared to SnPb
‰
© 2005
2004 - 2010
2007
S.F. Wong, ECTC 2007
Similar behavior observed at DfR
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193
Fatigue: Intel Vibration Study (Cont.)
Normalized Board Strain
1
SAC405
SnPb
0.1
0.01
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Normalized Time to Failure (Cycles)
Results do not display power-law behavior
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2007
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194
Experimental Procedures – Test Matrix (NEW)
„
One component type : 15 mm x 15 mm CBGA
‰
‰
‰
„
Three preconditioning states
‰
‰
‰
„
No preconditioning
Thermal Cycling from -20C to 85C 120 cycles
Isothermal 150C for 100 hours
Seven loading conditions
‰
‰
„
208 I/O perimeter array
0.8 mm pitch
12.7 x 12.7 mm die, CSP
Four harmonic vibration levels
Three shock levels
Two alloys
‰
‰
© 2005
2004 - 2010
2007
Sn3.0Ag0.5Cu
63Sn37Pb
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Vibration Results – Analysis (NEW)
„
© 2005
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2007
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Large
variation
in time
to failure
due to
multiple
stress
states
present
at each
load
level
196
Vibration Results – Analysis (NEW)
„
„
FEA to determine the stress levels
6 Stress levels Identified for each vibe level
U1
U20
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2007
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197
Vibration Results – Analysis (NEW)
SnPb Vibe Results: Stress/Location Corrected
1.00E+08
Cycles to Failure
1.00E+07
SnPb
Fatigue
Relationship
No
Precondition
σ = 116 .8 ⋅ N −.116
Thermal
Cycling
σ = 68.2 ⋅ N −.081
Isothermal
σ = 79.0 ⋅ N −.097
1.00E+06
y = 2E+14x
-5.9271
y = 5E+14x
-6.3281
y = 3E+14x
-6.3956
SnPb NPC
SnPb TC
SnPb ISO
1.00E+05
1.00E+04
10
15
20
25
30
35
Stress (MPa)
© 2005
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2007
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198
Vibration Results – Analysis (NEW)
SAC305 Vibe Results: Stress/Location Corrected
Fatigue
Relationship
No
−.058
Precondition σ = 52.3 ⋅ N
1.00E+08
y = 6E+11x-4.2163
Thermal
Cycling
1.00E+07
Isothermal
-3.692
Cycles to Failure
SAC305
y = 1E+11x
1.00E+06
y = 4E+11x-4.0694
σ = 78.1 ⋅ N −.09
σ = 71.0 ⋅ N −.082
SAC305 NPC
SAC305 TC
SAC305 ISO
1.00E+05
1.00E+04
10
15
20
25
30
35
Stress (MPa)
© 2005
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2007
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199
Vibe Results – 2X Safety Factor SnPb (NEW)
High Cycle Fatigue S-N Curve for SnPb, 3 Preconditions
35
SnPb NPC
SnPb TC
SnPb ISO
2X Safety Factor
30
Solder Alloy
Stress (MPa)
25
No Safety
Factor
15
2X Safety Factor
Determined at
108 cycles
Fatigue Exponents
Precondition
None
8.628
Temperature
Cycling
12.34
Isothermal
Aging
10.31
SnPb fatigue
exponent
8.333 [1]
© 2005
2004 - 2010
2007
20
6.51
10
Steinberg uses 6.4
8.427
5
1.00E+04
7.42
1.00E+05
1.00E+06
1.00E+07
1.00E+08
1.00E+09
Cycles to Failure
6.34
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Vibe Results – 2X Safety Factor SAC (NEW)
High Cycle Fatigue S-N Curve for SAC305, 3 Preconditions
35
SAC305 NPC
SAC305 TC
SAC305 ISO
30
2X Safety Factor
Stress (MPa)
25
Solder Alloy
No Safety
Factor 15
2X Safety Factor
Determined at
108 cycles
Fatigue Exponents
10
Precondition
None
17.24
Temperature
Cycling
11.11
Isothermal
Aging
12.195
© 2005
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2007
20
10.5
5
1.00E+04
7.83
1.00E+05
8.36
1.00E+06
1.00E+07
1.00E+08
1.00E+09
Cycles to Failure
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Vibe Results (NEW)
Solder Alloy
SnPb
SAC305
Precondition
Fatigue Relationship
−6.4
Cycles to Failure
© 2005
2004 - 2010
2007
⎛σ⎞
Nf =⎜ ⎟
⎝116⎠
−7.8
⎛σ ⎞
Nf =⎜ ⎟
⎝71⎠
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202
Fatigue: Interpretation of Pb-Free Data
„
SAC is ‘stiffer’ than SnPb
‰
„
Low-cycle fatigue (plasticity driven)
‰
‰
„
For a given force / load, it will respond with a lower displacement
/ strain (elastic and plastic)
Under displacement-driven mechanical cycling, SnPb will tend to
out-perform SAC (e.g., chip scale packages [CSP])
Under load-driven mechanical cycling, SAC will tend to outperform SnPb (e.g., leads of thin scale outline packages [TSOP])
High-cycle fatigue (elasticity driven)
‰
© 2005
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2007
SAC will tend to out-perform SnPb for all package types
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Fatigue: Conclusions (NEW)
„
If you have a problem with SnPb solder and
vibration, you will have a problem with SAC
solder and vibration
„
If you do not have a problem with SnPb
solder and vibration, you will not have a
problem with SAC solder and vibration
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2007
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204
Mechanical Shock
„
SAC can be significantly less robust than SnPb
‰
„
Crossover into board failure
‰
„
Not always consistent
Very strain-rate dependent
Plating is an important
driver
‰
SnNi vs. SnCu
intermetallics
Chai, ECTC 2005
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2007
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Results: Mechanical Shock Testing
Unaged CSPs (blue)
versus CSPs
exposed to 125°C
(green) and 150°C
(red) for 10 hours
demonstrated that
aging reduces drops
to failure.
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2007
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206
Results: Mechanical Shock Testing
Unaged CSPs (blue)
versus CSPs
exposed to 125°C
(green) and 150°C
(red) for 100 hours
demonstrated that
aging reduces drops
to failure. Formation
of “tails” indicates
that infant mortality
(due to randomized
induced defects) is
present.
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2007
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207
Results: Mechanical Shock Testing
Unaged CSPs (blue)
versus CSPs
exposed to 125°C
(green) and 150°C
(red) for 1000 hours
is evidence for a
transition from
ductile failures
(wearout) to brittle
(random).
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2007
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208
High Temp Storage: Embrittlement
Mechanical shock results after extended aging (1000 hrs/150ºC) of CSPs:
„
SN100C and SAC305 exhibit similar performance after exposure
„
SnPb slightly superior
„
Failures occur predominantly at or near CSP interface
„
Mixed failures typical, with brittle fraction increasing with exposure time
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2007
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Experimental Procedures – Shock (NEW)
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Shock Results (NEW)
Table 8: Summary of Weibull Variables for SAC305 Shock Testing.
Solder
Precondition
Effective Shock Level Characteristic
Life (η)
(tower level)
Shape Factor
(β)
SAC305 None
694 (1000)
56
1.48
SAC305 None
570 (1500)
59
1.59
SAC305 None
520 (750)
160
1.86
SAC305 150°C Isothermal
694 (1000)
49
1.23
SAC305 150°C Isothermal
570 (1500)
79
2.29
SAC305 150°C Isothermal
520 (750)
111
2.14
SAC305 -40°C - 85°C Cycled
694 (1000)
55
2.33
SAC305 -40°C - 85°C Cycled
570 (1500)
83
3.22
SAC305 -40°C - 85°C Cycled
520 (750)
136
1.83
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2007
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Shock Results (NEW)
Table 9: Summary of Weibull Variables for SnPb Shock Testing
Solder
Precondition
Effective Shock Level
(tower level)
Characteristic
Life (η)
SnPb
None
694 (1000)
41
1.60
SnPb
None
570 (1500)
78
1.47
SnPb
None
520 (750)
154
2.17
SnPb
150°C Isothermal
694 (1000)
25
1.08
SnPb
150°C Isothermal
570 (1500)
44
1.90
SnPb
150°C Isothermal
520 (750)
61
1.48
SnPb
-40°C - 85°C Cycled
694 (1000)
56
2.26
SnPb
-40°C - 85°C Cycled
570 (1500)
76
2.65
SnPb
-40°C - 85°C Cycled
520 (750)
184
1.81
© 2005
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2007
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Shape
Factor (β)
212
Shock Results – Analysis (NEW)
Pulse
Time
Frequency
Frequency
Ratio
Amplification
Factor
Adjusted G
Load
1500 G
0.5 mS
1000 Hz
0.17
0.38
570
1000 G
1.00 mS
500 Hz
0.34
0.694
694
750 G
1.00 mS
500 Hz
0.34
0.694
520
© 2005
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2007
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213
Shock Results – Analysis (NEW)
750
700
Shock Level (G)
SAC305 NPC
650
SnPb NPC
SAC305 150C
SnPb 150C
600
SAC305 TC
SnPb TC
550
500
0
50
100
150
200
Num ber of Drops
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2007
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Long-Term Aging
„
Intermetallic Growth
‰
‰
„
Aging before thermal cycling
‰
„
Can influence drop / shock performance
Rates in SAC seem faster; SnPb / SN100C may
be equivalent
Work by HDPUG and UMD seem to suggest
minimal difference (-10%)
Dwell
‰
© 2005
2004 - 2010
2007
Work by Intel demonstrates degradation of both
SAC and SnPb
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PoF Example: SnAgCu Life Model
„
Modified Engelmaier
‰
‰
„
Semi-empirical analytical approach
Energy based fatigue
Determine the strain range (∆γ)
LD
∆γ = C
∆α∆T
hs
„
C is a correction factor that is a function of dwell
time and temperature, LD is diagonal distance, α is
CTE, ∆T is temperature cycle, h is solder joint height
© 2005
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2007
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216
PoF Example – SAC Model (cont.)
„
Determine the shear force applied to the solder joint
⎛ L
⎛ 2 −ν ⎞ ⎞
hs
hc
L
⎟⎟ ⎟
(α 2 − α1 ) ⋅ ∆T ⋅ L = F ⋅ ⎜⎜
+
+
+
+ ⎜⎜
⎟
⎝ E1 A1 E 2 A2 As Gs Ac Gc ⎝ 9 ⋅ Gb a ⎠ ⎠
‰
‰
„
F is shear force, L is length, E is elastic modulus, A is the
area, h is thickness, G is shear modulus, and a is edge
length of bond pad
Subscripts: 1 is component, 2 is board, s is solder joint, c is
bond pad, and b is board
Takes into consideration foundation stiffness and
both shear and axial loads
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2007
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217
PoF Example – SAC Model (cont.)
„
Determine the strain energy dissipated by the
solder joint
F
∆ W = 0 .5 ⋅ ∆ γ ⋅
As
„
Calculate cycles-to-failure (N50), using energy
based fatigue models for SAC developed by
Syed – Amkor
N f = (0.0019⋅ ∆W )
−1
© 2005
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2007
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Validation – Chip Resistors
Cycles to Failure (Predicted)
10000
1000
100
100
1000
10000
Cycles to Failure (Experimental)
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2007
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PoF Example – SAC Reliability (cont.)
„
How to ensure 10 year life in a realistic
worst-case field environment for
industrial controls?
‰
‰
American Southwest (Phoenix)
Dominated by diurnal cycling
o
o
Month
Cycles/Year
Ramp
Dwell
Max. Temp ( C)
Min. Temp. ( C)
Jan.+Feb.+Dec.
March+November
April+October
90
60
60
6 hrs
6 hrs
6 hrs
6 hrs
6 hrs
6 hrs
20
25
30
5
10
15
May+September
June+July+August
60
90
6 hrs
6 hrs
6 hrs
6 hrs
35
40
20
25
+10C at max temperature due to solar loading
© 2005
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2007
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PoF Example – SAC Reliability (cont.)
„
Total damage in desert
environment over 10 years
0.02604
„
Total damage in one cycle of
-40C to 85C test environment
0.00012
„
Total cycles at -40C to 85C
to replicate 10 yrs in desert
222 cycles
At 1 cycle/hour, approximately 1 day of test equals 1 year in the field
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2007
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Pb-Free DfR
(Microstructure / HALT)
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Microstructural Evolution: SnPb
„
It is well known that SnPb coarsens when subjected to thermal cycling
‰
„
Morphology provides valuable data on failure behavior
Drivers for grain growth
‰
‰
Larger grains -> fewer grain boundaries -> lower free energy
Thomson-Freundlich solubility relationship
„
„
„
„
The solubility in the matrix in contact with a particle increases as the radius of the
particle decreases
Solute diffuses in the direction of largest particles and away from smallest particles
Small particles dissolve to compensate
Thermo-mechanical cycling (TMC) increases grain growth rate (Ostwald
ripening)
‰
‰
Plastic deformation during TMC results in an excess concentration of
vacancies, which increases rate of diffusion
Relatively high solid solubilities of Pb in Sn and vice versa lead to
microstructural instability (changes in the miscibility of the two phases over the
temperature range)
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Microstructural Evolution: SnPb
200 hours
© 2005
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2007
1000 hours
1800 hours
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Microstructural Evolution: SAC
„
„
Reflowed SAC solder joints tend to
contain relatively few grains
Plastic deformation during TMC and
high-angle grain boundaries creates
initiation sites for recrystallization
‰
‰
‰
„
„
Starts at highest stress regions
Grains get smaller!
Behavior similar to brass
After reflow
After 1000 cycles
Occurs faster and more uniformly in
solder attached to copper-based
platings
Leads to inter-granular fracture
‰
© 2005
2004 - 2010
2007
SnPb tends to be intra-granular
Mattila, J. Mat. Res. 2004
-40 to 125C
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After failure (~1500 cycles)
225
HALT/HASS and Pb-Free
„
As discussed in previous sections, SnPb will
outperform Pb-free solders in high temperature/high
vibration amplitude environments
‰
‰
Thus, Pb-free assemblies may perform worse under HALT
HASS conditions must be re-evaluated
„
However, Pb-free assemblies will likely have longer
lifetimes in actual field environments
„
HALT/HASS continue to offer value in highlighting
weak links of a design and/or process
„
HALT/HASS results should not be used for lifetime
prediction without substantial studies in less
accelerated conditions
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2007
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Design for Reliability
(Conclusions)
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2007
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Transition to Pb-Free: Other Issues
„
Be aware of the ‘greening’ of packaging materials
‰
‰
„
Recent examples of failing to capture new failure behavior when
new materials were introduced
‰
‰
„
More than just Pb-free
Do not accept ‘form-fit-function’
Red phosphorus flame retardants
Low ESR electrolyte
Why?
‰
‰
© 2005
2004 - 2010
2007
Strong drivers in industry to limit the value of testing and product
qualification
Hear no evil, see no evil
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228
New Technology: Supply Chain Failures
„
Failure in experimental design
‰
„
Failure to properly pre-condition
‰
‰
„
No attempt to understand how the new
technology could fail and adjust
qualification procedures accordingly
Testing not performed after reflow
Most component testing not performed
after exposure to all realistic
manufacturing stresses
Failure to use appropriate samples
‰
© 2005
2004 - 2010
2007
Must be representative of realistic
worst-case (materials, manufacturing,
use)
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Outliers and Technology Qualification
Range in field failure rates (approximately 1.5%)
Environmental Stress
Failures
© 2005
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2007
Material Strength
No Failures!
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Failures of Inadequate Testing
„
Failure to monitor relevant behavior
‰
E.g., leakage currents not monitored during temperature / humidity / bias
(THB) testing
„
‰
„
Assumed a particular failure mechanism (Kirkendall voiding, which induces a
voltage drop)
Functional tests not performed in-situ
Failure of testing
‰
THB testing not performed
„
„
‰
Failures during integrity testing not always communicated to customers
„
‰
Interfered with launch date
Not aware of new compound
Strong impetus to report zero failures
Changes in materials not always communicated to the customer
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2007
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231
Summary
„
To avoid design mistakes, be aware that
functionality is only the beginning
„
Be aware of industry best practices
‰
When to use heuristic rules; when to use physics of failure
„
Maximize knowledge of your design as early in the
product development process as possible
„
Do not overly rely on supplier statements
‰
© 2005
2004 - 2010
2007
Their view: Reliability is application dependent
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