i
University of Twente
Faculty of Electrical Engineering,
Mathematics & Computer Science
A Low Power NMOS LDO in
the Philips CO50PMU
Process
S.N.Easwaran
MSc. Thesis
March 2006
Supervisors:
Dr. ir. R.A.R van der Zee
Prof.dr. ir. B.Nauta
Report number: 067.3144
Chair of Integrated Circuit Design
Faculty of Electrical Engineering,
Mathematics & Computer Science
University of Twente
P. O. Box 217
7500 AE Enschede
The Netherlands
Abstract
In this report a new architecture of an NMOS Low Drop Out (LDO) Regulator
is proposed. It features a new frequency compensation technique to enable better
regulation. The LDO Regulator handles large load currents with good stability
(25° phase margin for low load currents from no load till 2mA and then towards
90°for larger load currents) and a good transient response (overshoot and
undershoot less than 3% for a load step from 1mA to 500mA). The quiescent
current of the LDO is 50µA, with a load capacitor of 470nF. The LDO is
scalable for different maximum load currents without impact on stability. In
Standby mode the LDO is stable with a quiescent current three times smaller
than the normal operation. The application of the NMOS LDO is in Power
Management Units for all the handheld and mobile application devices like the
mobile phones, Apple IPODs etc.
iii
Acknowledgement
This thesis describes the result of a Master of Science assignment at Philips
Semiconductors, Nijmegen, The Netherlands. This assignment has been carried
out from August 2005 to March 2006 at the PMU-ABB (Power Management
Unit-Analog Base Band) for completing the Master degree in Electrical
Engineering in the section of ICD at the University of Twente, The Netherlands.
I would like to thank Ir.Alberto van Burgh, Development Manager as he hired
me to the PMU-ABB group which enabled me to move from Philips
Semiconductors (PS), Zurich to PS, Nijmegen to continue my Analog Design
Career. I would like to thank Ir.Ferdinand Sluijs, Innovation Manager and
Ir. Johan.M. van der Wiel, Development Group Leader for their support and for
offering me the NMOS LDO topic as my Master Thesis subject.
I would like to thank Prof.Dr.ir. Bram Nauta (Head ICD, University Of Twente
(UT)) for his wonderful support and he and his team were the backbone for my
success during my Master Studies at the UT.
At the outset I would like to thank Dr.ir.Ronan van der Zee for all his support,
guidance and patience. As my supervisor, he has constantly enforced me to be in
focus towards achieving this goal. His observations and comments helped me to
establish the overall direction of the research and move forward with
investigation in depth. I met him only once a week but his overall support with
several exchange of e-mails and phone calls were at the best in order to help me
carry out the NMOS LDO research and write the Thesis in a better manner. His
way of work coupled with intuitive analysis helped me to understand the
concepts in a better way.
I greatly appreciate Ing. Max Martin, my supervisor at PS, Nijmegen for his
whole hearted support and suggestions during the whole thesis work. As my
supervisor at PS, Nijmegen he helped me to know more about the specifications
of the NMOS LDO, its environment in the real application which helped me
stay with in the specifications and limitations. I have no words to express his
wonderful support to me during this research period.
I would like to thank Dr.ir.K.J.de Langen, BU Automotives, PS,Nijmegen for
his help and fruitful discussions during this research. I would like to thank my
friends from Talent Telecom Solutions (supporting PMU-ABB group at PS,
Nijmegen) for fruitful discussions to gather some information on the competitor
LDOs in the market. I would like to thank other colleagues at PS, Nijmegen for
the pleasant working environment. I would like to thank my fellow students at
UT for the pleasant learning environment. I would like to thank my friends
Balaji, Shankar and Vishnu for providing me a lot of support and enthusiasm
during my stay at the UT campus. I acknowledge many friends in Enschede who
have made my 1.5 year study so cheerful. For me, UT campus looked as a Home
away from Home. Last, but not the least, I would like to dedicate this thesis to
my family in India, for their love, patience, and understanding.
iv
List Of Abbreviations
PMU - Power Management Unit
BOM - Bill Of Materials
LDO - Low Drop Out Regulator
UGB - Unity Gain Band Width
LHP - Left Half Plane
RHP - Right Half Plane
ESR - Equivalent Series Resistance
ESL - Equivalent Series Inductance
SMD - Surface Mounted Device
v
Table Of Symbols
gm*- Transconductance of in Siemens (S)
R*- Output Impedance in Ohms (Ω)
A(s) - Open Loop Gain in decibels (dB)
β - Feedback Factor
ϕ - Phase Margin in degrees (°)
CL- Load Capacitor
fp* - Frequency Of The Pole in Hertz (Hz)
fz* - Frequency Of The Zero in Hertz (Hz)
fτ - Unity Gain Bandwidth in Hertz (Hz)
µn - Mobility of the electron in m2/Vsec
Cox – Oxide Capacitance of the MOS Transistor in (F) Farads
Cgs- gate to Source Capacitance of the MOS Transistor in (F) Farads
Avt – Slope Factor Of Threshold Voltage in (mVµm)
σvt - Standard deviation of the Threshold Voltage in mV
vi
Contents
1 PMU And The Need for NMOS LDOs .........................1
1.1 Power Management Unit (PMU).........................................................................1
1.2 DC/DC Converters.............................................................................................2
1.3 Low Drop Out (LDO) Regulators .......................................................................2
1.4 Introduction to NMOS LDOs ...............................................................................3
1.5 PMOS Low Drop Out Regulator..........................................................................3
1.6 Low Voltage Drive ...............................................................................................4
1.7 Specifications of the NMOS Regulators..............................................................5
1.8 Summary ..............................................................................................................7
1.9 References ............................................................................................................7
2 PMOS Low Drop Out Regulators ...............................9
2.1 Choice of the Dimension of the PMOS Power Transistor ...................................9
2.2 Conventional Design Approach for the PMOS LDO...........................................9
2.3 Load Capacitor with a certain ESR and ESL ....................................................11
2.4 ESR Zero ............................................................................................................12
2.5 Compensation Scheme for PMOS LDO.............................................................13
2.6 Summary ............................................................................................................13
2.7 References ..........................................................................................................13
3 Conventional Design Of NMOS LDOs .......................15
3.1 Architecture of the NMOS LDO.........................................................................15
3.2 Dimensioning The NMOS Power Transistor .....................................................15
3.3 Stability of the NMOS LDO ...............................................................................17
3.4 Conventional Design Approach-I ......................................................................19
3.5 Conventional Design Approach -II....................................................................19
3.6 Pole-Zero Calculations For Conventional-I Approach.....................................20
3.7 Pole-Zero Calculations For Conventional Design Approach-II ......................22
3.8 Implementation Of The Conventional Circuit...................................................24
3.9 AC and Transient Response Of The NMOS LDO .............................................26
3.10 Problems With The Scalability Requirement ...................................................29
3.11 Summary ..........................................................................................................31
3.12 References ........................................................................................................31
vii
4
Compensation Of The NMOS LDO.........................33
4.1 Introduction.......................................................................................................33
4.2 Proposed Compensation with Small Signal Model............................................33
4.3 Small Signal Analysis.........................................................................................34
4.4 Pole Zero Locations for Full Load and No Load Conditions...........................35
4.5 Choice of the Compensation Capacitor Cc ........................................................36
4.7 Trade Off At No Load and Small Load Currents..............................................39
4.8 Implementation Of The Miller Compensated Circuit .......................................40
4.9 AC Response And Transient Characteristics....................................................42
4.10 Ringing in Time Domain and Poor Gain Margin in AC Domain....................45
4.11 High Frequency Peaking ................................................................................46
4.12 Summary .........................................................................................................46
4.13 References .......................................................................................................46
5 Damping Factor Enhancement, Power Sense
Construction with Simulation Results............................47
5.1 Introduction.......................................................................................................47
5.2 Non-Dominant Poles.........................................................................................47
5.3 Improved Damping ............................................................................................49
5.4 Power Sense Construction .................................................................................50
5.5 Peaking At High Frequencies ............................................................................50
5.6 AC Characteristics.............................................................................................53
5.7 Transient Response ............................................................................................54
5.8 DC Response......................................................................................................54
5.9 PSRR Calculations.............................................................................................56
5.10 Monte-Carlo Simulations.................................................................................56
5.11 Equivalent Output Noise ..................................................................................57
5.12 Summary ..........................................................................................................58
5.13 References ........................................................................................................58
6 Additional Features In The NMOS LDO..................59
6.1 Programmability of the output voltage ..............................................................59
6.2 ECO Mode .........................................................................................................61
6.3 Adaptability Of The LDO To Scalable Load Currents ......................................64
6.4 Cap Free Option ................................................................................................66
viii
6.5 Summary ............................................................................................................66
7 Conclusions And Future Work..................................67
Future Work .............................................................................................................67
Appendix- I...............................................................................................................68
Appendix- II .............................................................................................................73
1
1
PMU And The Need for NMOS LDOs
____________________________________________________________________
We live in an era where we like to access information when we are on the
move. Electronic gadgets like the cellular phones, mobile audio, video systems
like the Apple IPODs become more complex. More power is consumed by both
active and standby systems. Consequently, power-management design for
portable wireless devices imposes new challenges in the areas of I/O interface,
energy management and battery lifetime. Power regulation and management
IC’s have become one of the fastest growing segments of the electronics
industry largely due to the proliferation of portable electronic devices such as
cell-phones, MP3 players, PDA’s, and game machines. This has led to
increasing demand for higher levels of integration in order to reduce boardspace requirements and lower the BOM (Bill of materials) [2].
1.1 Power Management Unit (PMU)
Battery is the only source of power that we can use to supply the circuits.
Battery management is very important in this mobile era. We need to ensure that
optimum use is made of the energy inside the battery that powers the portable
product [1].
Power management involves the implementation of functions that ensure a
proper distribution of power throughout the system ensuring minimum power
consumption by each system. Examples are active hardware and software
design changes for minimizing power consumption, such as reducing clock rates
in digital system parts and powering down system parts that are not in use. A
PMU consists of DC-DC converters [1] and LDOs (Low Drop Out Regulators)
[1]. An overview of a PMU is given in the Figure (1.1).
LDO
DIGITAL
Battery
LDO
ANALOG
DC/DC
CONVERTER
Load
Currents
Figure (1.1) A Typical Power Management Unit
2
1.2 DC/DC Converters
DC/DC converters convert one DC voltage to another DC voltage. The main
input DC voltage is the Lithium ion battery voltage that always stays between
2.75V to 4.25V. The generated output voltage may need to be even higher than
the input DC voltages as in the display driver applications [1]. Apart from that,
the digital circuits operate at voltages lower than 1V. This conversion is done by
the DC-DC converters.
In general, two approaches exist for converting one voltage into another. The
first approach involves a time-continuous circuit with a dissipative element,
whereas the second approach involves a time-discrete circuit with an energystorage element.
The first approach is only suitable for converting a higher voltage into a lower
voltage, which is down-conversion, whereas the second approach enables upand down-conversion. The two approaches are illustrated in the Figure (1.2) in
which the battery voltage Vin is converted into Vout.
Figure(1.2) Two approaches to convert a battery voltage into another voltage.
(a): Time continuous with dissipative element (Vin > Vout only)
(b) Time-discrete with energy-storage element
The dissipative element in the Figure (1.2a) remains connected between the
battery and the load. The efficiency of the voltage conversion will always be
lower than 100%, because of its dissipative nature. The energy-storage element
in Figure (1.2b) is first connected to the battery to store energy, after which it is
connected to the load to supply this energy. The efficiency of the voltage
conversion process is 100% in the theoretical case in which no energy is lost in
the energy-storage element and switches. The type of time-discrete voltage
converter employed and the characteristics of the employed components will
determine the efficiency in practice. An energy buffer Cbuf is necessary, because
of the time-discrete nature of converters of this type.
1.3 Low Drop Out (LDO) Regulators
Regulate as the name clearly says, the function is to regulate the output voltage
despite the variations in the load currents. In other words a LDO is a voltage
source which delivers a constant output voltage despite variations in the load
current. The low noise characteristics and smaller size and complexity of these
regulators, make them ideal candidates for many applications, especially where
the (Vin-Vout) difference is small.
3
For very low power applications, linear regulators are actually preferable even if
the efficiency is low not only due to the lower cost and complexity, but also
because their quiescent currents are lower.
Due to their lower noise contribution, LDO regulators are favoured for powering
many sections of the typical cellular handset. LDO’s are very suitable for
powering the baseband, RF, TCXO, RTC, and audio sections of the typical
handset. They are also being used to power white LED’s for backlighting in
other portable applications. Each of these applications has different
requirements which have traditionally been met by off-chip regulator IC’s.
Keeping the regulators off-chip not only increases BOM cost, it also lowers
system reliability, requires valuable board space and creates more stringent
requirements on the regulator due to losses on the PC-board itself.
1.4 Introduction to NMOS LDOs
To overcome the disadvantage mentioned in Section 1.3, in modern PMUs the
DC-DC converters are used to convert one voltage level to the another because
of their high efficiency. The DC-DC converters have ripple on their outputs. In
order to remove the ripple, LDOs are used as the post regulators to regulate the
output voltage of the DC-DC converters. This is pictorially represented in the
Figure (1.3).
DC/DC
CONVERTER
LDO
LDO
Battery
DC/DC
CONVERTER
LDO
Load Current
Figure(1.3) LDOs as Post Regulators
1.5 PMOS Low Drop Out Regulator
Most of the existing LDOs are PMOS LDOs. It is discussed here in order to give
an overview of the design approaches for a LDO. A schematic representation of
a PMOS LDO is shown in Figure (1.4).
4
It consists of a PMOS transistor, controlled by an error amplifier, which
compares a fraction of Vldo_out with a reference voltage Vref. The transistor
(MP_LDO) is operated in the saturation region [3]. The error amplifier is
supplied by the VISA ( Voltage Internal Supply Analog). (Vldo_in - Vldo_out),
which is the dropout voltage, has to be present for proper operation.
MP_LDO
PMOS, Power Transistor
Vref
Vldo_out
VISA
-
Vgate
+
VSS
R1
R2
Vldo in
Vgate
Vldo out
Figure (1.4) PMOS LDO Regulator
1.6 Low Voltage Drive
As we move towards low voltage ranges the input to the LDOs from the DCDC converters will be getting lower and lower. When we think of the option of
a PMOS LDO, we can easily see that the source voltage of the PMOS power
transistor in the Figure (1.4) is getting lesser than VISA which also needs a low
gate voltage even lesser than VSS in order to drive a certain load. The error
amplifier will no more function in this case and we need DC-DC converters that
generate voltages lower than VSS in order to supply the error amplifier and to
pull down the gate voltage below the VSS level. The other solution is to replace
5
the PMOS power transistor in the Figure (1.4) with an NMOS Power transistor,
paving way to the design of the NMOS LDO regulators. This is shown in the
Figure(1.5).
Vldo_in
Vref
+
MN_LDO
NMOS, Power Transistor
Vldo_out
VISA
Vgate
-
VSS
R1
R2
Vldo in
Vgate
Vldo out
Figure (1.5) NMOS LDO Regulator
As shown in the Figure (1.5) even if the Vldo_in level gets lower, the gate
voltage of the NMOS power transistor needs to stay at a positive level (i.e. a
positive Vgs) in order to drive the NMOS transistor for a certain load current.
Like the PMOS LDO regulator, we need to bias the NMOS Power transistor in
the NMOS LDO in the saturation region [3]. Hence we see a need for NMOS
LDO regulators when the regulator inputs get lower.
1.7 Specifications of the NMOS Regulators
The specifications of the NMOS LDO Regulators are shown in Table(1.1).These
specifications have to be translated in terms of the design parameters like the
open loop gain of the LDO, UGB etc. A higher open loop gain will result in
lower offset voltage [3] which translates into the accuracy specification of the
output voltage. Load step indicates a measure of the stability and speed of the
6
LDO. The UGB is a measure in terms of speed of the LDO translating to the
overshoot and undershoot during the load step. The reference voltage has to be
chosen based on the regulator input and the output voltage to be delivered. The
drop out voltage is 300mV. During stand by mode of the application, the LDO
needs to draw very less current and should be stable.
Table 1.1 Detailed Specifications Of The NMOS LDO
Tamb: -40°C to 85°C Output current within nominal range; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Vldo_in
1.8
V
1.5
V
V
mV
Vldo_out
Vs
Regulator supply
voltage
0.9
Programmable output
voltage
Programming step
size
0.6
(Vp+Vdropout)
25
Vpacc
Absolute accuracy of
output voltage
Iout=10% of
Ioutmax
1
%
Vpload
Load regulation
delta Iout
1mA....Ioutmax
1
%
Vpline
VISA
Line regulation
Internal analog supply
voltage
Dropout voltage
External reference
voltage
output current in
normal mode
output current in eco
mode in % of
Ioutnormal
Regulator Output
Capacitor
Series resistance load
capacitor
Total supply current in
active mode
Total supply current in
ECO mode
Total supply current in
OFF mode
relative to Vin
band-gap off
band-gap on
Iout=Ioutmax
0.1
2.7
2.45
300
0.605
%/V
V
mV
V
500
mA
10
%
470
nF
Vdropout
Vref
Ioutnormal
Iouteco
Cdec
ESR_Cdec
Isupact
Isupeco
Isupoff
Scalable
ESL<2nH
Iout=0mA
2.1
2.35
2.4
2.4
0.595
0.600
50
100
5
mΩ
As low as possible
(50µ +0.25%*Iout)
As low as possible
(15µ +1%*Iout)
1
µA
*Note: Vdrop is defined as the Vldo_in – Vldo_out voltage, when Vldo_out is 1% below the
set output voltage. The voltage drop over the bond wires is included
7
1.8 Summary
In this chapter, the PMU and the LDOs were introduced. The need for the
NMOS LDO has been discussed with its specifications.
1.9 References
[1] Battery Management Systems, A Design by Modelling by H.J.Bergveld,
Ph.D Thesis , Universiteit Twente, June 2001.
[2] Power Management Unit ,Electronic Letters
[3] Analog Integrated Circuit Design by B.Razavi.
8
9
2
PMOS Low Drop Out Regulators
_____________________________________________________________________
2.1 Choice of the Dimension of the PMOS Power Transistor
In modern PMUs the DC-DC converters are used in order to convert one DC
level to another. The DC-DC converters have high efficiency. But the output
voltage in DC-DC converters has a lot of ripple [1]. The main reason why a
LDO would be used after the DC-DC converter is to remove this ripple. Hence
the Power Supply Ripple Rejection (PSRR)[1] is a very important item on the
list of boundary conditions. In Section 1.3 we refer LDO to be a voltage source
which means that the LDO should have a low output impedance. The power
transistor is dimensioned based on its current and |Vgs-Vth|. Calculations in [3]
show that a transistor with 1V overdrive may need thousands of micron wide
transistor to handle hundreds of milliamps of currents. Also a large W/L is
opted in order to maintain a low drop out voltage. A larger W/L helps to
dissipate the heat within its area whereas a smaller W/L spreads the heat to the
near by transistors, thereby causing problems. On the other hand the total
dimension of the MP_LDO has to be minimized because of chip costs and gate
current (due to parasitic gate capacitors). A trade-off has to be made at this
juncture.
2.2 Conventional Design Approach for the PMOS LDO
From the Figure (1.4) we can see that the open loop gain of the PMOS LDO is
the product of the gains of the error amplifier and the gain of the single stage
amplifier built by using the MP_LDO transistor. This means that we can see a
two pole [2] transfer function, one pole coming from the output of the amplifier
and the other from the MP_LDO and the load capacitor. The transfer function
can be given as
AoL ( s ) =
Aerror _ amp * AMP _ LDO
( s + ω pa )( s + ω pL)
→ (2.1)
where AoL(s) is the open loop gain of the PMOS LDO
Aerror_amp is the gain of the error amplifier
AMP_LDO is the gain of the output stage of the LDO with the Power
Transistor
ωpa is the pole from the amplifier
ωpL is the pole from the Output Stage
For a stable system, the poles have to be far apart with the second pole far off
from the Unity Gain BandWidth (UGB)[2] of the LDO. Unity Gain Bandwidth
Will be determined by the capacitor that sets the dominant pole along with the
transconductance of the error amplifier that sets the gain.[3]
10
Line and load transient measurements show the LDO’s ability to respond to
abrupt changes in line voltage and load currents. These test reveal significant
overshoot, or sustained ringing in the output as it attempts to maintain
regulation. We need to have a response without any overshoots and ringing at
the output. The basic step for this is to place a capacitor at the output which will
remove the overshoots. At the same time the ringing of the LDO shouldn’t
occur by placing this capacitor. This ringing is a measure of the phase margin of
the LDO when we talk about its gain and phase characteristics in open loop.
Equation (2.1) can be explained a bit more in detail. The gain of the amplifier
stages are specified in terms of a certain transcondutance and output impedance.
If the transconductances of the error amplifier and the output PMOS power
transistor MP_LDO are gma ,gmo respectively with their output impedances Ra
and Ro respectively then the overall open loop gain of the LDO can be expressed
as
AoL( s ) =
gmaRagmoRo
( s + RaCa )( s + RoCL)
→ (2.2)
Ca and CL are the capacitance seen at the output of the amplifier and the load
capacitance respectively.
It is a very common design approach to have the LDO, output pole dominant
[1]. This means that the dominant pole is determined by the load capacitor. The
expression for the dominant pole fpL will be
fpL =
1
2π RoCL
→ (2.3)
The UGB can be expressed as fτ .
fτ =
gmaRagmo
2π CL
→ (2.4)
Now the design technique is to keep the pole from the error amplifier outside the
UGB. To do that we need a low output impedance from the amplifier. By
sacrificing the gain of the error amplifier, we achieve low output impedance and
thereby the stability is obtained.
11
2.3 Load Capacitor with a certain ESR and ESL
We connect an external capacitor in order to improve the transient response of
the LDO. This is a Ceramic SMD (Surface Mounted Device) Capacitor. This
external capacitor is not ideally capacitive in nature [13]. The capacitor has with
it an Equivalent Series Resistance (ESR) and an Equivalent Series Inductance
(ESL). Hence the load seen by the LDO is an R-L-C circuit rather than a purely
capacitive one. The realistic capacitor is shown in the Figure (2.2).
Figure (2.2) Realistic Ceramic SMD Capacitor
Apart from that we also have the inductance of the bond wire from the bond pad
to the pin and the routing tracks from the pin to the load capacitor offer some
inductance and resistance. Hence the realistic load the LDO sees is shown in
Figure (2.3). This is used in the simulations. The capacitor should be placed as
close as possible to the pin because placing it a bit far away from the pin results
in a larger track inductance of the order of 10nH, which could result in stability
problems [2].A bondwire is made out of Gold metal. It has a diameter of 25µm.
The resistance of the bondwire for a 1mm length can be calculated as
12
R=
ρL
A
' ρ ' is the specific resistance of the Gold wire
of the order of 2.2e − 8 Ωm @ Temperature T = 293K
⇒R=
2.2e − 8*1e − 3
~ 50mΩ
π (12.5e − 6) 2
In most of the situations the bondwire is 1mm to 2mm long and so the
bondwire resistance is of the order of 50mΩ to 100mΩ. Also the bondwire of
1mm length has an inductance of 1nH. To lower the bondwire resistance ,two
bondwires are used in parallel offering a resistance of 25mm and an
inductance of 0.5nH.
Bond Wire
50mΩ
1nH
LDO
Bond Pad
Track Resistance
5mΩ
Track Inductance
2nH
Load
Current
ESR = 5mΩ
ESL = 2nH
Capacitor = 470nF
Figure (2.3) Realistic Load of the LDO
2.4 ESR Zero
The ESR along with the load capacitor produces a zero. A higher ESR pushes
the zero towards low frequencies. This would be a Left Half Plane Zero [4]
which produces a positive phase shift. At higher frequencies the inductive
reactance increases and a RLC combination could produce complex poles and
13
zeroes which will have a big impact on the stability of the LDO and are
discussed in the ensuing chapters.
2.5 Compensation Scheme for PMOS LDO
An output pole compensated PMOS LDO will often result in the choice of a big
capacitor when large load currents are handled. This big capacitor helps the
output pole to be restricted within a certain KHz band. Then at the expense of a
reasonable current it may be easy to place the poles of the amplifier beyond the
UGB. Also in many designs, the amplifier pole is pushed to a low frequency
region and is cancelled by the zero from the ESR [4]. Pushing the amplifier to
the low frequency region gains us the gain of the LDO. Unfortunately these
approaches demand the need of a big output capacitor. A smaller capacitor
takes a smaller area and so the integration on the Printed Circuit Board (PCB)
becomes easier. Frequency compensation techniques have been developed in
order to address the stability of the LDO with a smaller load capacitor. The
compensation techniques deal with pole-splitting techniques widely discussed
and verified in [5,6,7,8,9,10]. In these compensation techniques the dominant
pole changes to the amplifier pole while the load pole is moved beyond the
UGB or is cancelled with an ESR Zero. The ESR of these capacitors is of the
order of 200mΩ. In [11] another approach of mirroring the load current is
suggested where the variation in the load pole is compensated by a varying zero.
In [12] another compensation technique has been proposed. This compensation
scheme introduces a zero that is independent of the ESR of the capacitor and
this would work only when this ESR is low, possibly lesser than 50mΩ.
2.6 Summary
In short an overview of the functionality of the PMOS LDO and the techniques
to get them stable have been discussed.
2.7 References
[1] LDO Topologies by G.E.de Vrieze, March 29th,2000, Philips
Semiconductors, Internal Document.
[2] Line and Load Transient Testing for Power Supplies, Dallas
Semiconductor,Maxim Editorial on Power Supply Circuits,Dec30,2004.
[3] Analog Integrated Circuit Design by B.Razavi
[4] Technical Review Of Low Drop Out Voltage Regulator, Operation and
Performance, Application Report, Texas Instruments Ltd.
[5] Operational Amplifiers, Theory and Design by Johan.H.Huising, Kluwer
Academic Publishers.
[6] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent Current
low drop-out regulator,” IEEE J. Solid-State Circuits,vol. 33, pp.36–44, Jan.
1998.
[7] “A new method for multiplying the Miller capacitance using active
components ,” by G.de Cremoux, Y.Christoforou, I.van Loo
[8] “Optimized frequency-shaping circuit topologies for LDOs,”
IEEE Trans. Circuit and Systems II, vol. 45, pp. 703–708, June 1998.
[9] G. A. Rincon-Mora, “Active Capacitor Multiplier in Miller Compensated
Circuits,”, IEEE J. Solid-State Circuits, vol.35, pp.26-32,Jan.2000.
14
[10] Ka Nang Leung and Philip K.T.Mok , “A Capacitor-Free CMOS Low
Dropout Regulator With Damping Factor Control Frequency
Compensation,”, IEEE J. Solid-State Circuits, vol.38, pp.16911702,Oct.2003.
[11] Ka Chun Kwok and Philip K.T. Mok , “Pole Zero Tracking Frequency
Compensation For Low Dropout Regulator, ”
[12] “A Frequency Compensation Scheme for LDO Voltage Regulators,”
by K.Chava and J.Silva-Martinez, IEEE J. Solid-State Circuits, vol.51,
June 2004
[13] “ Improve Your Designs with Large Capacitance Value Multi-Layer
Ceramic Chip ( MLCC ) Capacitors ” by George M. Harayda,
Akira Omi, & Axel Yamamoto, from Panasonic Electronic Equipments.
15
3 Conventional Design Of NMOS LDOs
_____________________________________________________________________
3.1 Architecture of the NMOS LDO
The architecture of the NMOS LDO is shown in the Figure (3.1). The NMOS
LDO consists of an error amplifier and a level shifter. The error amplifier of the
LDO is supplied by an Internal Analog Supply Voltage(VISA) and the battery
voltage VBAT is used to supply the Level Shifter. The level shifter is used in
order to boost the gate voltage of the power transistor to a level greater than the
VISA level. This is essential to handle large load currents with an optimal
dimension of the power transistor. A bigger power transistor results in large
parasitic capacitances there by hampering the speed of the LDO. The Input
Voltage to the LDO (Vldo_in) ranges between 1.8V to 0.9V. The output voltage
(Vldo_out) is between 1.5V to 0.6V. The load current is from 0 to 500mA at a
quiescent current consumption of 50µA with a load regulation accuracy of
1%.
Vbat
Vldo_in (Regulator Input)
Level shifter
Error Amplifier
Vref
+
-
Power Transistor
Vgate
MN_LDO
VISA
Vldo_out (Regulator Output)
VSS
R1
R2
IL: Load Current = 500mA
Figure (3.1) Proposed NMOS LDO Architecture
3.2 Dimensioning The NMOS Power Transistor
The first step in the design is to dimension the power transistor. The transistor
should be biased in the saturation region [1].The maximum current through the
transistor and the drop out voltage are known. The process parameters like the
threshold voltage (Vth), process gain µnCox of the transistor are known. For our
output requirements, we know that we need a low voltage NMOS transistor. It is
available in the Philips C050PMU process [1]. The normal NMOS transistor
suffers from body effect [2] which in turn will increase the threshold voltage of
the transistor thereby demanding an increase in the dimension of the transistor
or demanding a higher over drive to handle a certain current .
16
Hence in Philips C050PMU process [1], special NMOS transistor called as the
Isolated NMOS transistor is available, whose body effect is zero because the source
and the bulk of the NMOS transistor can be tied together. The Figure (3.2) shows the
cross section and the symbol of the NMOSISO transistor. The PW1 (special Pwell)
which is the bulk of the transistor is tied to the source. The Nwell is tied to the drain.
ProMOST, the Internal Philips tool helps us to determine the W/L of the transistor, for
a certain Vds, Vgs-Vth and drain current Id. Table 3.1 gives us an insight of the needed
W/L for a certain Vgs-Vth. The conclusion is that if we can boost the gate of the NMOS
Power Transistor to 2.5V even if the VISA is 2.2V, we would be able to optimize its
dimension .From[1] we infer that the maximum gate voltage that can be applied to
the gate of the NMOS power transistor is 2.5V. So now we choose between our
voltage that we need to generate and the W/L.
n+
n
+
Nwell
Gate
PW1
PW1
NWELL
Substrate
Figure (3.2) NMOSISO transistor ; Cross Section and Symbol
Table 3.1 Necessary (W/L) of The Power Transistor (vs) its Vgs, Vds, Id
S.No
1.
2.
3.
4.
6.
7.
Current
through the
NMOS Power
Transistor
500mA
500mA
500mA
500mA
500mA
500mA
W/L of the
NMOS Power
Transistor
375,000µ/0.25µ
50,000µ/0.25µ
40,000µ/0.25µ
30,000µ/0.25µ
20,000µ/0.25µ
11,500µ/0.25µ
Gate Voltage of
the NMOS
Power
Transistor
2.16V
2.28V
2.30V
2.33V
2.40
2.5V
Vldo_in
(Drain
Voltage)
Vldo_out
(Source
Voltage)
1.8
1.8
1.8
1.8
1.8
1.8
1.49994
1.50003
1.50001
1.49998
1.49999
1.4996
17
3.3 Stability of the NMOS LDO
We have to map the Figure (3.1) into the small signal model which is shown in,
the Figure (3.3) from which we analyze the stability. The stability of the NMOS
LDO is analyzed by the Bode plot that is obtained from the Open Loop
Simulation of the LDO.
Vbat
Vldo_in (Regulator Input)
Level shifter
Error Amplifier
Vgate
MN_LDO
Vref
+
-
VISA
Vldo_out (Regulator Output)
VSS
Ra
Loop opened here. This path shown in dotted lines
is open for AC and closed for DC.
Rb
V1
Vref
gmxVx
βVo
gm1V1
gmL(VL-Vy)
gmp(VL-Vo)
Figure (3.3) Large Signal and Small Signal Model of the NMOS LDO
Error Amplifier is modeled as a two stage amplifier. First stage is a differential
stage without any high impedance node to obtain a voltage gain. Hence it is
modeled as a subtracting node that subtracts (Vref-βVo) where ‘β’ is the
Rb
to 1 when the output voltage is
feedback fraction. It varies from
Ra + Rb
programmable from 1.5V to 0.6V.
18
Output Impedance of the first stage is R1||C1. Output impedance of the output
stage is Rx||Cx.
Level Shifter is modeled as a Voltage Controlled Current Source (VCCS) with
an output impedance,
RL =
1
gmL
where gmL is the transconductance of the LevelShifter .
Power transistor is modeled as a VCCS with an output impedance equal to the
transconductance of the Power Transistor. Cp is the Gate to Source Capacitance
of the Power transistor. Load Capacitor has an Equivalent Series Resistance
(ESR) and Equivalent Series Inductance (ESL) associated with it. The ESL is
omitted to make the mathematical expressions that are calculated from the small
signal model simpler.
g mp
; Load Pole;
2π C L
g mp is the transconductance of the power transistor ;
f p1 =
C L is the load capacitor
fpa
1
; Amplifier Pole; R x Output impedance of the amplifier .
2π R xC x
C x is the Capacitance seen at the output of the amplifier
=
Pole due to R 1C 1 can be neglected if we design such
that R 1C 1 << R xC x
Load capacitor sets the dominant pole and LDO gain rolls off after fp1
As a result , the input impedance of the power transistor is its C gs
and so there occurs a pole due to the levelshifter at
fpL =
g mL
2π Cp
( output impedance of the levelshifter =
fz
=
1
)
g mL
1
; Zero due to the ESR & the Load Cap
2π R esrC L
The pole from the power transistor moves from low frequencies in Hertz to mid
frequencies in KHz. For a particular load current, the pole from the power
transistor may clash with the pole from the error amplifier which leaves the
LDO unstable.
19
3.4 Conventional Design Approach-I
In the conventional designs, the LDO has a dominant pole from the power
transistor. The remaining poles are moved outside the Unity Gain Bandwidth
(UGB). This has a big disadvantage of burning a lot of quiescent current to
reduce the output impedance of the error amplifier in order to move the error
amplifier pole outside the UGB, which in fact has to result in a lower output
impedance. Lower output impedance lowers the DC gain which in turn affects
our output accuracy. The Bode plot is shown in the Figure (3.4).
fp,no load fp,full load
x
x
Gain (dB)
Gain and phase for No Load
Condition
0
Phase (degree)
x amplifier, fz,esr
fp,error
0
-45 °
-90 °
-180°
Frequency
Figure (3.4) Bode Plot of a Conventional Design Approach in a NMOS LDO
3.5 Conventional Design Approach -II
If we target a moderate gain of the LDO we increase the output impedance of
the error amplifier and move pole of the amplifier within the UGB. Choosing a
big load capacitor along with the ESR and bond wire resistance could produce a
zero within the UGB. This would cancel the pole from the error amplifier and
leaves us with an output pole dominant LDO. This is shown in Figure (3.5). We
place the pole of the level shifter outside the UGB and so it is not shown in the
Figure(3.5).
20
fp,no load
x
Gain (dB)
fp,full load
x
x
fp,error amplifier, fz,esr
0
Phase (degree)
0
-45°
-90°
-180°
Frequency
Figure (3.5) Bode Plot of a Conventional Design Approach in a NMOS LDO
3.6 Pole-Zero Calculations For Conventional-I Approach
The position of the poles and zeroes can be calculated as follows.
Let us assume the following values for full load
which is 500 mA.
Conventional Approach − I
g mp = 1.5 S ; R x = 10 M Ω ; C x = 20 fF ; g mL = 400 e − 6 S ; C p = 6.65 pF
g m1 = 20 e − 6 S ; R 1 = 48 K Ω ; C 1 = 10 fF ; g mx = 20 e − 6 S .
C L = 470 nF ; R esr = 30 mΩ (including the bondwire resistance )
DCGain = g m1 R1 g mxR x = 20 e − 6 * 48e + 3 * 20 e − 6 *10 e + 6 = 192 = 45 dB
1
1
fpa =
~ 800 KHz
=
2π R xC x 2 * 3.141*10 e + 6 * 20 e − 15
g mp
1.5
fp1 =
~ 510 KHz
=
2π C L 2 * 3.141* 470 e − 9
g mL
400 e − 6
fpL =
~ 10 MHz
=
2π C p 2 * 3.141* 6.65e − 12
1
1
~ 11MHz
fz 1 =
=
2π R e srC L 2 * 3.141* 30 e − 3 * 470 e − 9
The UGB is given by
fτ =
1
2π
g m1 R 1 g mxg mp
1
=
C LC x
2π
20 e − 6 * 48e + 3 * 20 e − 6 *1.5
~ 8.8 M Hz
470 e − 9 * 20 e − 15
Under the full load condition, the LDO is unstable as there are two poles within
the UGB.
21
Gain
45 (dB)
fp1
fpa
fτ
0
fpL, fz1
Frequency
Phase (degree)
0°
-45°
-90°
-135°
-180°
Frequency
Figure (3.5a) Conventional Approach- I : Location of Poles and Zeroes
We can see from the calculations and its Bode-Plot in the Figure (3.5a) that the
phase margin is poor because of the two poles lying with in the UGB. This
reflects the ringing behavior during the load step in the transient.
In order to get the LDO stable with a good phase Margin of 60° as per the
conventional approach-I, we need to push the pole of the error amplifier outside
the UGB. This means that we should reduce the value Rx by a factor of 12 so
that we move the pole of the error amplifier outside the UGB leaving the LDO
output pole dominant.
Hence when we decrease the output impedance of the error amplifier by a factor
of 12, which in turn decreases the gain to 24dB which is less for accuracy.
Under no load condition, gmp would decrease to say 347µS which moves the
load pole to 117Hz and would also decrease the UGB proportionately. But the
error amplifier pole is not that far away from the UGB thereby affecting the
stability. The conclusion is that the LDO is stable for currents only if the error
amplifier pole is moved beyond the UGB at the expense of the decrease in the
gain. This is explained graphically in the Figure (3.5a).
22
3.7 Pole-Zero Calculations For Conventional Design Approach-II
By choosing a little bigger load capacitor, let us calculate our poles and Zeroes.
Let us assume the following values for full load
which is 500 mA.
Conventional Approach − II
gmp = 1.5 S ; Rx = 10 M Ω; C x = 20 fF ;
gmL = 400e − 6 S ; C p = 6.65 pF
gm1 = 20e − 6 S ; R1 = 48 K Ω;
C 1 = 10 fF ; gmx = 20e − 6 S .
C L = 4.7 µ F ; Resr = 30 mΩ (including the bondwire resistance )
DC Gain = gm1 R1 gmxR x = 20e − 6 * 48e + 3* 20e − 6 *10e + 6 = 192 = 45dB
1
1
~ 800 KHz
=
2π R xC x 2 * 3.141*10e + 6 * 20e − 15
gmp
1.5
f p1 =
~ 51KHz
=
2π C L 2 * 3.141* 4.7 e − 6
gmL
400e − 6
fpL =
~ 10 MHz
=
2π C p 2 * 3.141* 6.65e − 12
1
1
fz1 =
=
~ 1.1MHz
2π ResrC L 2 * 3.141* 30e − 3* 4.7 e − 6
fpa =
The UGB is given by
fτ =
1 ⎛ gm1 R1 gmxgmpResr ⎞
⎜
⎟
2π ⎝
Cx
⎠
fτ =
1 ⎛ 20e − 6 * 48e + 3* 20e − 6 *1.5 * 35e − 3 ⎞
⎜
⎟ ~ 8 MH z
2π ⎝
20e − 15
⎠
Under the full load condition, the LDO is stable as there are two poles and a zero
within the UGB.
Here we can see that the error amplifier pole and the ESR zero lie within
the UGB. As a result of this, the -90° phase shift by the error amplifier
pole would be compensated by a +90° phase shift from the ESR zero there
by providing a good phase margin. This is shown graphically in the Figure
(3.5b).
23
Gain
45 (dB)
fp1
fpa, fz1
fτ
0
Phase (degree)
fpL
Frequency
0°
-45°
-90°
-135°
-180°
Frequency
Figure (3.5b) Conventional Approach- II ; Location of Poles and Zeroes
From the Figure (3.5b) we see that the phase margin is 49˚.
Phase Margin ' Φ' is calculated by using the relation :
⎛ fτ ⎞
⎛ fτ ⎞
⎛ fτ ⎞
⎛ fτ ⎞
Φ = 180°− tan−1 ⎜ ⎟ − tan−1 ⎜ ⎟ + tan−1 ⎜ ⎟ − tan−1 ⎜ ⎟
⎝ fp1 ⎠
⎝ fpa ⎠
⎝ fz1 ⎠
⎝ fp2 ⎠
⎛ 8e + 6 ⎞
−1 ⎛ 8e + 6 ⎞
−1 ⎛ 8e + 6 ⎞
−1 ⎛ 8e+ 6 ⎞
⇒Φ = 180°− tan−1 ⎜
⎟
⎟ − tan ⎜
⎟ + tan ⎜
⎟ − tan ⎜
⎝ 10e + 6 ⎠
⎝ 51e + 3 ⎠
⎝ 800e + 3 ⎠
⎝ 1.1e + 6 ⎠
⇒Φ = 180°− 90°− 84°+ 82°− 39°
⇒Φ = 49°
24
3.8 Implementation Of The Conventional Circuit
The circuit that is realized from the small signal model is shown in the Figure
(3.6). The transistors MP135 and MP136 form the differential pair biased by a
current source of 15µA. The reference voltage is supplied to the non-inverting
terminal of the differential amplifier. The currents from the transistors MP135
and MP136 are mirrored through the NMOS current mirrors MN1, MN3 and
MN2, MN4. Additional current sources have been added into MN1 and MN2 in
order to control the output impedance of the error amplifier independent of the
gm of the differential stage. The current in MN3 is mirrored again by the PMOS
current mirror MP134, MP138. The drain of MP138 and MN4 is a high
impedance point where we obtain the voltage gain of the error amplifier.
The output voltage of the error amplifier drives the level shifter. The Level
shifter is a simple implementation with a current source and a PMOS transistor.
This provides an output voltage greater than the minimum supply (VISA) of the
error amplifier. The output of the level shifter drives the NMOS power
transistor. The dimension of the power transistor is chosen from the Table (3.1).
It is opted to be 11500µ/0.25µ in order to handle a load current of 500mA.
The source of the NMOS power transistor is connected to the resistive divider
whose output voltage from a certain tap point is fed back to the inverting
terminal of the differential amplifier. The source of the NMOS LDO which is our
output point is connected to the pin via the bond pad and the bond wires.
The Load capacitor is connected to the pin. The load capacitor has a certain ESR
and ESL of around 5mΩ and 2nH. The bond wires (two bondwires in parallel)
have a resistance of 25mΩ to 30mΩ to and an inductance of 0.5nH (i.e.
1nH/mm). The resistance produces a zero with in the UGB which helps to
improve the phase margin. This has a disadvantage that we have voltage drop of
Iload*30 mΩ. For larger load currents of the order of 500mA, the voltage drop
would be around 15mV. When the output targeted is 1.5V, we would achieve
1.485V after the 15mV drop which reflects that an accuracy of 99% or the error
in the output voltage is 1%.
%error =
1.5 − 1.485
*100 = 1%
1.5
When our regulator input would be only 400mV, then we would have a voltage
drop of 15mV, leading to an output voltage of 385mV. The error is 3.75% and is
not acceptable.
%error =
0.4 − 0.385
*100 = 3.75%
0.4
So this problem can be overcome and is explained in the later chapters. The AC
response and the transient characteristics are discussed in section 3.8.
25
Figure (3.6) Realized Transistor Topology for NMOS LDO
26
3.9 AC and Transient Response Of The NMOS LDO
The open loop simulation set up is shown below in Figure (3.7). The loop is
opened at the source of the NMOS LDO. This means that the resistor divider is
disconnected from the source of the NMOSLDO for an AC signal. However it is
closed for the DC levels. This is implemented by using the switches that are
available in the Library “analogLib”. Two switches are used with one switch
closed (“OFF” state) for DC and open (“ON” state) for AC, through which an
AC signal of amplitude 1V is applied. The other switch is open for DC and
closed for AC.
Vbat (min)=2.75V, Vdd(min)=2.2V(VISA); iload =0 till 500mA;
Load Capacitor Cdec=4.7µF
Figure(3.7) Open Loop Simulation of the NMOS LDO
The AC simulation results for a range of load currents are shown in the Figure
(3.7) followed by the transient load step simulation results in Figure(3.8). Phase
Margin is good for lower range load currents around 90° and as the load current
increases the phase margin decreases as the load pole comes closer to the error
amplifier pole. The ESR zero helps to stabilize the phase margin.
27
Load Current 0 to
20mA
Load Current 50mA
to 500mA
Figure (3.8) AC response for load currents split in two graphs from 0 to 500mA
28
Figure (3.9) Transient Response For Rising and Falling Load Steps
29
From the AC characteristics we see that the phase margin is approximately 45°
and in the transient response we see no oscillations for a load step of 0 to
500mA.
3.10 Problems With The Scalability Requirement
As discussed in the specification of the NMOS LDO ( Section 1.7), we would
like to have the LDO scalable. It means that, when the maximum load current
would be set to 10 times a lower current value, then we would like to have our
schematic in Figure (3.6) scaled down proportionately. For example, in the
Schematic in Figure (3.6), the power transistor has a dimension of
11500µ/0.25µ. When the load current is scaled down by 10 times, then we
would scale down our power transistor to 1150µ/0.25µ. At the same time it
would really be nice to scale down the output capacitor by 10 times i.e. to 470nF
from 4.7µF.
We also would like to scale down the level shifter current and scale down the
dimensions of all the transistors by a factor of 10. According to [3], the scaling
down of all transistors by a factor of 10 will increase the offset of the LDO. This
is because the W.L is reduced by a factor of 10 and the offset will increase by 10
as the offset is inversely proportional to the gate area according to the equation
below,
Avt
WL
Avt
σ vt ( scaled ) =
W L
.
10 10
10 Avt
⇒ σ vt ( scaled ) =
= 10* σ vt ( unscaled )
WL
σ vt ( unscaled ) =
Hence we don’t scale down the device dimensions. We scale down only our
bias currents, dimension of the power transistor and the load capacitor. The
bias current to the level shifter is not scaled down in order to retain the level
shifter pole outside the UGB. After the load capacitor is scaled down, the ESR
zero moves to the high frequencies because of the reduced load capacitor. This
has a big impact on stability of the LDO because the ESR zero is moving to
high frequencies and will not cancel the error amplifier pole as shown in the
Figure (3.10) below. The calculations are shown below.
30
Let us assume the following values for full load
which is 50mA.
Conventional Approach − II for low load currents.
gmp = 150e − 3S ; Rx = 10M Ω; Cx = 20 fF ; gmL = 400e − 6 S ; Cp = 665 fF
gm1 = 20e − 6S ; R1 = 48K Ω; C1 = 10 fF ; gmx = 50e − 6S .
CL = 470nF ; Re sr = 30mΩ (including the bondwire resistance)
DCGain = gm1R1 gmxRx = 20e − 6* 48e + 3* 20e − 6*10e + 6 = 192 = 45dB
1
1
fpa =
~ 800 KHz
=
2π RxCx 2*3.141*10e + 6* 20e − 15
gmp
150e − 3
fp1 =
~ 51KHz
=
2π CL 2*3.141* 470e − 9
⎛
⎞
⎜
⎟
⎜
⎟
W
⎜
⎟
2 Id µCox
gmp
⎜
⎟
L
⎜ fp1 = fp 500 mA = 2π CL =
⎟
2π CL
⎜
⎟
⎜ Since the current is 10 times less gmp scales down by 10 and 10 times smaller capacitor ⎟
⎜
⎟
W
⎜
⎟
Id
W
10
⎜
⎟
2 µCox
2 Id µCox
gmp
⎜
⎟
10
L =
L = fp 500 mA
⎜ fp1 = 2π CL =
⎟
CL
2π CL
2*3.141*
⎜
⎟
10
⎝
⎠
So our load pole doesn ' t change.
gmL
400e − 6
fpL =
~ 10MHz
=
2π Cp 2*3.141*6.65e − 12
1
1
=
fz1 =
~ 11MHz
2π Re srCL 2*3.141*30e − 3* 470e − 9
The UGB is given by
1 ⎛ gm1R1 gmxgmp R esr ⎞ 1 ⎛ 20e − 6* 48e + 3* 20e − 6*150e − 3*35e − 3 ⎞
⎜
⎟=
⎜
⎟ ~ 8MHz
Cx
2π ⎝
20e − 15
⎠ 2π ⎝
⎠
Similarly the UGB doesn ' t change.
Under the full load condition, the LDO is unstable as there are two poles
within the UGB.
fτ =
31
Gain
45 (dB)
fp1
fpa
fτ
0
fpL, fz1
Frequency
Phase (degree)
0°
-45°
-90°
-135°
-180°
Frequency
Figure (3.10) AC Response Of the NMOS LDO showing the
movement of Zero towards High Frequencies
The conclusion is that the conventional Approach is not suited when scaling
down the LDO requirements towards lower load currents with lower load
capacitors.
3.11 Summary
The conventional design approaches I and II for the NMOS LDO have been
discussed. The stability issues have been discussed with small signal models ,
Bode Plots and equations. Also the load scalability and LDO adaptability have
been discussed only to conclude that the conventional approach is not suited
when we scale down the LDO requirements towards lower load currents with
lower load capacitors. So frequency compensation is necessary in order to
overcome the scalability and LDO adaptability issue.
3.12 References
[1] Philips Semiconductors, C050PMU Process Manual.
[2] Device Physics by Muller and Kamins.
[3] Matching Properties of MOS Transistors by M.Pelgrom et al.
32
33
4
Compensation Of The NMOS LDO
_____________________________________________________________________
4.1 Introduction
It is understood from Chapter 3, that we need an LDO which could be adapted
when load currents scale down with the scaling down of the load capacitors.
Hence we need a robust frequency compensation technique in order to design an
LDO that meets the specification mentioned in the Section 1.7. Lot of frequency
compensation techniques have been proposed for the operational amplifiers [1]
and the PMOS LDOs [2-6].
A study has been made in order to apply a similar strategy for the NMOS LDO
or if the topology in [7] can be adapted for the specifications in Section 3.2. The
advantage of the topology in [7] is that ideally there is no pole from the power
transistor as the power transistor is not a part of the feedback loop. Another way
to design is to avoid the load capacitor, then the LDO can be made stable for all
currents but this approach has a poor transient response.
4.2 Proposed Compensation with Small Signal Model
The proposed compensation technique is shown in the Figure (4.1). The
error amplifier has a differential input stage with current mirror loads. The
compensation capacitor is connected across the input of the output stage of
the error amplifier to the output of the NMOS LDO. This compensation is
referred to as the Miller Compensation. Now the LDO has a
dominant pole contributed by the Miller Capacitor and the output pole
gmp
due to the load capacitor is moved beyond
, outside the UGB
2π CL
guaranteeing a phase margin of 90°.
In Section 4.3 we will also see that for the no load and small current ranges less
than 1mA, the load pole is dominant and we don’t see the Miller Effect. The
Phase Margin is only 25˚ but can be tolerated because of the short range of the
currents.
34
V1
Vref
gmxVx
gm1V1
gmL(VL-Vy)
gmp(VL-Vo)
βVo
Figure (4.1) Compensated NMOS LDO
4.3 Small Signal Analysis
Writing the nodal equations at the nodes Vx, Vy ,VL and Vo to solve for
we get ( See Appendix-I for the complete analysis)
⎡ sCc
⎤
− gmp ⎥ [1 + sCL Re sr ]
gm1R1 gmxRx ⎢
Vo
⎣ gmxRx
⎦
=
→ (4.1)
V 1 [− gmxgmpRxsCcR1 − {( gmp + sCL )(1 + sCxRx )(1 + sCcR1)}]
The poles and zeroes are given by
p1 =
p2 =
− g mp
C L + (C xR x + g mxR xC cR1) gmp
− ( C L + g mpC xR x + g mxg mpR xC cR 1 )
C LC xR x
→ (4.2)
→ (4.3)
z1 =
−1
R e srC L
→ (4.4)
z2 =
g mpg mxR x
Cc
→ (4.5)
Vo
V1
35
Equation (4.1) shows us the transfer function of the NMOS LDO from the input
to the output i.e. from the point V1 to Vo. V1 is the output of the subtractor
circuit that performs the difference (Vo -βVref).The poles are the LHP Poles,
The Resr Zero is a LHP zero whereas the fz 2 is a RHP Zero.
4.4 Pole Zero Locations for Full Load and No Load Conditions
The targeted DC gain would decide on the values of transconductances gmx, gm1
and the output impedances R1,Rx. The load capacitor CL is known to us.
Let us tabulate the poles and zeroes for the full load condition and the
no load condition
S.No
Pole/Zero
1.
fp1
First Pole
2.
fz1
First Zero
4.
fz2
Second Zero
5.
No Load
− gmp
2π CL
−1
2π gmxRxR1Cc
∵ CL + gmpCxRx << gmpgmxRxCcR1
∵ CL >> gmpCxRx + gmpgmxRxCcR1
gmpgmxCCR1
2π CLCx
∵ CL + gmpCxRx << gmpgmxRxCcR1
1
−
2π Re srCL
1
2π RxCx
∵ CL >> gmpCxRx + gmpgmxRxCcR1
1
−
2π Re srCL
fp2
Second Pole
3.
Full Load (500mA)
fτ
Unity Gain
Bandwidth
−
−
gmpgmxRx
2π Cc
gm1
2π CC
gmpgmxRx
2π Cc
1
2π
gm1R1 gmxgmp
CLCx
Table (4.1) Pole-Zero Locations For Full Load and No Load
36
4.5 Choice of the Compensation Capacitor Cc
Let us analyse a simple way of choosing the value of Cc that guarantees a good
phase margin and then verify it with simulations. Based on the DC gain and the
current consumption we target, we set the values of the transconductances and
the output impedances. Let us consider the full load situation of 500mA and try
to find out the value of the compensation capacitor.
Let us target for a phase margin of 60°.
The phase margin (Φ ) is given by the equation
⎛ fτ ⎞
⎛ fτ ⎞
Φ = 180° − tan −1 ⎜ ⎟ − tan −1 ⎜
⎟ → (5.6)
⎝ fp1 ⎠
⎝ fp 2 ⎠
From [2] we know that for a phase margin of 60°, we need the
second pole to be more than a factor of 2 more than the UGB.
f p 2 >> 2 f τ
1
fτ
⇒ >>
2
fp 2
g m1
2π C L C x
*
2π C C g mpg mxC C R 1
g m1C L C x
⇒ 0.5 >>
g mpg mxC C 2 R 1
⇒ 0.5 >>
⇒ C C >>
2 g m1C L C x
→ (5.7)
g mpg mxR 1
4.6 Calculations of Poles and Zeroes
Let us choose gm1=50µS, gmx=50µS, R1=48KΩ, Rx=120MΩ, gmp=2S
Resr = 5mΩ, CL=470nF, Cx=50fF
Our DC Gain and Cc are about
Adc= gmxgm1R1Rx = 50e-6 * 50e-6 * 48e+3 * 120e+6 = 84dB
Cc >>
2gm1CLCx
2*50e − 6*470e − 9*50e −15
=
gmpgmxR1
2*50e − 6*48e + 3
>> 49*10e − 26 = 0.7 pF
Therefore the minimum Cc we need is 0.7pF. So let us choose it as 1.7pF.
37
So our poles and zeroes turn out to be
S.No
Parameters
1.
fp1
Full Load
(500mA)
373Hz
No Load
8.46Hz
52MHz
26KHz
9 MHz
9 MHz
3200G Hz
1.4GHz
5.7MHz
56KHz
First Pole
2.
fp2
Second Pole
3.
fz1
First Zero
4.
fz2
Second Zero
5.
fτ
Unity Gain Bandwidth
Table (4.2) Pole-Zero Locations For The NMOS LDO
------ No Load
____ Full Load
fp1
Gain
84dB
fτ
fp2
Frequency
fz1
fp2
0°
-45°
-90°
-135°
-180°
Frequency
Figure (4.1a) Pole Locations Of The Compensated NMOS LDO
38
Hence we see that the NMOS LDO is stable after compensation. It has two poles
and two zeroes. Under full load conditions the dominant pole comes from the
error amplifier because of the Miller effect [1].
Under full load conditions, the NMOS LDO has a single pole response with its
second pole located beyond the UGB. This is because the load pole is moved to
gmpgmxCCR1
from the actual pole location of the NMOS Power transistor at
2π CLCx
gmp
. The main advantage of this compensation technique is that the active
2π CL
feedback loop through the compensation capacitor buffers a lot of current even
at KHz frequencies which gives enough gain to the LDO. This could also be
seen as a shunt-shunt feedback active loop which offers a low output impedance.
gmpgmxCCR1
from the actual pole
In other words the output pole is moved to
2π CLCx
gmp
. This guarantees a phase
location of the NMOS Power transistor at
2π CL
margin of 90° at full load condition.
Under no load condition we see that the dominant pole is contributed by the load
capacitor. This means that the output of the LDO is same as the ground node
after 8.46Hz and so the shunt-shunt feedback at the full load condition is not
applicable to the no load condition. Also RxCx contributes another pole within
the UGB. So at no load condition we have low phase margin (45°) unlike the
full load condition. The Bode plot from the Spectre Simulation is shown in the
Figure (4.2).
39
Figure (4.2) Bode Plot For Full Load and No Load Condition
4.7 Trade Off At No Load and Small Load Currents
Since there are two poles within the UGB for small load currents, stability
issue arises. Hence the LDO is brought back to stability by reducing the
value of R x which moves the second pole beyond the UGB. This is
evident from the table (4.1)because R x is the only term that is
independent of the UGB at no load. This means that we are reducing our
DC gain, A dc . We should only take care that the gain shouldn’t go lower
than 30dB as it affects the accuracy of the output voltage. Then as soon as
the load current starts increasing we don’t have an impact as the equations
totally change with Miller effect dominating.
40
4.8 Implementation Of The Miller Compensated Circuit
The circuit that is realized from the small signal model is shown in the Figure
(4.3). It is the same schematic as the one shown in the Figure (3.6) with an
additional Miller capacitor . The transistors MP135 and MP136 form the
differential pair biased by a current source of 1.5µA. The reference voltage is
supplied to the non-inverting terminal of the differential amplifier. The currents
from the transistors MP135 and MP136 are mirrored through the NMOS current
mirrors MN1, MN3 and MN2, MN4. Additional current sources have been
added in MN1 and MN2 in order to control the output impedance of the error
amplifier independent of the gm of the differential stage. The current in MN3 is
mirrored across by the PMOS current mirror MP134, MP138. The drain of
MP138 and MN4 is a high impedance point where we obtain the voltage of the
error amplifier. The Miller compensation capacitor is connected from the drain
of the MN3 transistor to the source of the NMOS power transistor. This is
similar to the Nested Miller Compensation as mentioned in [1].
The output voltage of the error amplifier drives the level shifter. The output of
the level shifter drives the NMOS power transistor.
The source of the NMOS power transistor is connected to the resistive divider
whose output voltage from a certain tap point is fed back to the inverting
terminal of the differential amplifier. The source of the NMOS LDO which is
our output node is connected to the pin via the bond pad and the bond wires. The
Load capacitor is connected here. The load capacitor has a certain ESR and ESL
of around 5mΩ and 2nH.
The bond wires (two bondwires in parallel) have a resistance of 25mΩ to30mΩ
and an inductance of 0.5nH. The resistance produces a zero with in the UGB
which helps to improve the phase margin. This has a disadvantage that we have
voltage drop of Iload*30 mΩ. The AC response and the transient characteristics
are discussed in Section 4.9.
41
Figure (4.3) Realized Transistor Topology for NMOS LDO with
Miller Compensation
42
4.9 AC Response And Transient Characteristics
The open loop simulation has been performed to analyze the AC characteristics
and the load step has been performed for load currents from 1mA to 500mA
rising and falling in 1µs. The Figure (4.4) describes it all.
Figure (4.4) AC characteristics of Miller Compensated NMOS LDO
We see that the phase margin decreases from 90˚ to 30˚ from no load current
till 1mA and then as the current starts increasing the phase margin
increases back to 90˚. This is shown in the Figure (4.5). This is because for
small load currents we have two poles with in the UGB and we could
achieve 30˚ phase margin by reducing the DC gain of the LDO. Under
small load conditions, the first pole comes from the load capacitor and the
second pole comes from the error amplifier. The Miller capacitive
multiplication doesn’t take place here because the load capacitor rolls of earlier
43
than the compensation capacitor and it is equivalent to connecting the
compensation capacitor to ground. Plot of the phase margin and load currents on
a logarithmic axis is shown below.
Figure (4.5) Plot of Phase margin Plot vs Load Currents on a Logarithmic scale
The transient response for a load step between 1mA to 500mA is shown in the
Figure (4.6) below. There is some ringing observed when the load current
increases to 500mA. This is observed for all temperatures and all process
corners. The magnified version of the ringing is shown in the Figure (4.7).
44
Figure (4.6) Transient Response for a load step 1mA to 500mA
Figure (4.7) Zoomed Version Of The Ringing
45
The frequency of the ringing was noted to be 2.5MHz which was initially
thought to be the resonating feature of the LC tank at the load point. But the
resonance frequency is
1
1
f =
=
= 3.6 MHz
2π ( Ltrack + LESL )CLOAD 2π 4e − 9 * 470e − 9
So the ringing is not due to resonance. A retrace back to the AC domain was
made in order to analyse the cause for the ringing behaviour. A couple of issues
associated with the ringing and the peaking seen in the Figure (4.7) are
discussed in the Sections 4.10 & 4.11.
4.10 Ringing in Time Domain and Poor Gain Margin in AC Domain
In AC domain for a particular load current of 50mA, the peaking in the gain is
observed. This is because the non-dominant pole from the error amplifier
clashes with the output pole of the power transistor for a particular range of load
currents. This produces a complex pole (here we see that at 2.5MHz) that has a
peaking in the gain with a 180˚ phase shift. This is shown in the Figure (4.8). In
other words the damping at high frequencies is not sufficient enough to reduce
this peaking.
Figure (4.8) Gain Bump in Bode Plot @ Iout = 50mA.
46
4.11 High Frequency Peaking
At high frequencies a strange peaking is observed. Along with the bondwire
inductance and the ESL of the load capacitor, capacitance of the load capacitor,
transcondutance of the power transistor and the parasitic capacitance at the
source of the power transistor a tank circuit is formed . The parasitic
capacitance for instance could be the Source to Nwell capacitance. This peaking
is seen in hundreds of MHz range only for low load currents and is in several
Giga Hertz range for the higher load currents that are outside our simulation
range and are not shown in the Figure (4.4).
The compensation of the NMOS LDO is still not yet complete because of the
issue with poor gain margin for some load currents and the peaking at very high
frequencies. Also we have a drop over the bondwire which could be eliminated.
Improvements to overcome these problems are discussed in Chapter 5.
4.12 Summary
In this chapter the Miller compensation technique of the NMOS
LDO has been discussed. The advantage of this compensation is that we
could move the load pole to higher frequencies from its actual location
before compensation. We don’t need to rely on the ESR of the capacitor for
the stability. However we have a trouble due to poor gain margin and are
disturbed by the peaking in gain at very high frequencies.
4.13 References
[1] Operational Amplifiers, Theory and Design by Johan.H.Huising, Kluwer
Academic Publishers.
[2] “A new method for multiplying the Miller capacitance using active
components ,” by G.de Cremoux, Y.Christoforou, I.van Loo
[3] “Optimized frequency-shaping circuit topologies for LDOs,”
IEEE Trans. Circuit and Systems II, vol. 45, pp. 703–708, June 1998.
[4] G. A. Rincon-Mora, “Active Capacitor Multiplier in Miller Compensated
Circuits,”, IEEE J. Solid-State Circuits, vol.35, pp.26-32,Jan.2000.
[5] Ka Nang Leung and Philip K.T.Mok , “A Capacitor-Free CMOS Low
Dropout Regulator With Damping Factor Control Frequency
Compensation,”, IEEE J. Solid-State Circuits, vol.38, pp.16911702,Oct.2003.
[6] “ A Frequency Compensation Scheme for LDO Voltage Regulators,”
by K.Chava and J.Silva-Martinez, IEEE J. Solid-State Circuits, vol.51,
June 2004
[7] Embedded 5 V-to-3.3 V Voltage Regulator for Supplying Digital IC’s in
3.3 V CMOS Technology Gerrit W. den Besten and Bram Nauta,
IEEE, J. Solid -State Circuits Vol. 33, No. 7, July 1998.
47
5
Damping Factor Enhancement, Power
Sense Construction with Simulation
Results
____________________________________________________________________
5.1 Introduction
The compensation technique discussed in Chapter 4 had the main
disadvantage of obtaining a poor gain margin. The gain margin has to be
improved, otherwise we will see oscillations during a closed loop operation of
the NMOS LDO. The gain margin is poor because of the insufficient damping.
A number of techniques have been proposed in order to improve the damping of
the compensated operational amplifiers and LDOs [1-6]. The literatures
mentioned above, suggest a common way to improve the damping factor by
increasing the capacitance at the output of the error amplifier. Unfortunately in
this architecture, this would have an impact on the stability at very low load
currents say of the order of 100µA to 2mA. Hence a different approach has to be
adopted in order to increase the damping ratio of the NMOS LDO.
5.2 Non-Dominant Poles
The bump in the gain plot is observed because the non-dominant pole from the
error amplifier clashes with the output non-dominant pole from the power
transistor. As a result of this, for a particular current, the non-dominant poles
clash thereby resulting in the peaking in the gain. The other way of seeing this is
a poor damping factor.
V1
Vref
gm1V1
gmxVx
gmL(VL-Vy)
gmp(VL-Vo)
X
βVo
Figure (5.1) Closed Loop In An Open Loop
In open loop simulation, we open the loop at the “X” point. Despite opening
the loop at “X”, we can still see that there is a closed loop through the
48
compensation capacitor Cc from the node Vo to Vx. When the gain in this
internal closed loop is 1 with a phase shift of 180°, then the we can see the
peaking in the gain or the Gain Bump is unavoidable.
The damping factor can be calculated by opening the internal closed loop as
discussed in [3]. In Figure (5.2) the internal closed loop is broken in order to
analyze the damping factor.
Vt
gmxVx
gmL(VL-Vy)
gmp(VL-Vo)
Figure (5.2) Open Loop Analysis Of The Internal Closed Loop
Vo
. This is now the open loop transfer function A( s ) β of our Inner
Vt
loop that we want to analyze. Solving now for 1 + A( s ) β = 0 we would be able
to find out the damping coefficient and the frequency at which the peaking
occurs.
Solve for
Vo
− g mxg mL sC c ( g mp + sC p )
= A( s ) β =
g mp g mL g oxg o1 + s ( C L g mL g ox ) + s 2 ( C L C xg o1 g mL + C L C cg oxg mL )
Vt
Here g o1 =
1
1
and g ox =
R1
Rx
Simplifying further by neglecting the terms that are smaller
than C Lg mLg ox , we get 1 + A( s ) β = 0 as
g mpg mLg oxg o1 + s ( C Lg mLg ox ) + s 2 ( C LC xg o1 g mL + C LC cg oxg mL ) = 0
⎡
⎤
C Lg mLg ox
g mpg mLg oxg o1
s+
⇒ ⎢s2 +
=0
C LC xg o1 g mL + C LC cg oxg mL
C LC xg o1 g mL + C LC cg oxg mL ⎥⎦
⎣
T his when compared with the standard equation
s 2 + 2ξω ns + ω n 2
We get ω n =
g mpg oxg o1
C L (C xg o1 + C cg ox )
and
ξ=
g oxg o1C L
g mp (C xg o1 + C cg ox )
49
The damping factor ‘ξ’ and the natural frequency ‘ωn’ have been derived and in
order to increase the damping factor we have to decrease the open loop gain or
increase the load capacitor or increase compensation capacitor ‘Cc’ or increase
the transconductance of the power transistor. Unfortunately we can’t change the
design parameters already fixed because of our targeted gain, smaller capacitor
we want to use and the capability of the power transistor to handle 500mA load
current.
5.3 Improved Damping
Even though we don’t see the term Cp in the expressions of ξ, simulations
confirm that ξ depends on Cp also. In the analysis done so far we have treated
the LDO as a second order system but in reality we could relate the behavior of
the LDO to a 4 th order system whose transfer function is very complex.
Improvement in the damping factor could be achieved by connecting
another capacitor (Cdamping) as shown in the Figure(5.3) between Vx and VL.
V1
Vref
gmxVx
βVo
gm1V1
gmL(VL-Vy)
gmp(VL-Vo)
Figure (5.3) Improved Frequency Compensation
With the addition of the Cdamping capacitor we move the parasitic pole due to Cp
to higher frequencies because of Miller effect. Now our first pole moves to
lower frequency determined by gmxRxR1(Cc+Cdamping). In this design Cdamping
capacitor of 800fF has been used to increase ‘ξ’ and remove the gain bump.
Also in this design Cc+Cdamping ~ Cc and it is good that our UGB is not reduced
further to hamper the transient response. The AC characteristic for 1.5V output
along with the improved damping factor compensation is shown in the Figure
(5.4). The transistor level schematic is shown in the Figure (5.5).
50
Figure (5.4) AC Characteristics with Improved Damping
5.4 Power Sense Construction
We have seen that there is a drop of 15mV across the bondwire. We wish to
avoid this drop by using an additional bondwire eventually demanding the need
of an additional bondpad. The bondpads are named as Vldo_out and
Vldo_regulate. This is called as the Power Sense Construction. The difference
between this construction and the previous one is that the feedback in the Power
Sense Construction is taken after the bondwires of the Power transistor. This is
shown in the Figure (5.5).
As a result of this we will not have a zero contributed by the bondwire to the
stability of the LDO. But since our LDO is not dependant on this zero for
stability, we don’t need to worry if we use the Power Sense construction.
Topologies discussed in Chapter 3 suffer a lot in stability if we use the Power
Sense Construction.
5.5 Peaking At High Frequencies
At high frequencies we saw some peaking as explained in Section 4.11. This
peaking is mainly seen for low load currents as the g mp is less and the
peaking is because the damping in the path is poor. This is solved by adding
a capacitor of 10pF in series with a 100Ω resistor from the source of the
power transistor to ground. This is shown in the Figure (5.6).
Also a resistor of 100Ω, has been added to the gates of the differential pair
that helps to improve the damping in the tank formed by the bond wire in
the feedback path along with the Cgs of the differential pair. This is important
only when the feedback is taken directly from the Vldo_regulate node. (See
section 6.1) This is shown in both the Figures (5.5) and (5.6).
51
Figure (5.5) Power Sense Construction Of The NMOS LDO
52
Figure (5.6) Additional RC circuit to remove the peaking at High Frequencies
53
5.6 AC Characteristics
The AC response for the final schematic shown in Figure (5.6) is shown
below. The phase margin is plotted as a separate part. They are shown in the
Figure (5.6) and (5.7) respectively. We can see that the peaking at high
frequencies disappeared.
Figure (5.6) AC Response with Power Sense Construction & Improved Compensation
Figure (5.7) Phase Margin Plot for the AC Response
54
5.7 Transient Response
The transient response of the NMOS LDO with the power sense construction
is shown in the Figure (5.8). The voltage drop of 15mV is not seen anymore.
The load step is between 1mA to 500mA.
Figure (5.8) Transient Response Of the NMOS LDO
5.8 DC Response
The DC simulation is performed by a DC sweep on the regulator input Vldo_in.
We measure the regulator output Vldo_out. The Drop Out voltage is a difference
between Vldo_in and Vldo_out when the output voltage drops to 1% of its
value. This is shown in the Figure(5.9) where Vldo_in, Vldo_out and their
difference is plotted.
Also a DC sweep of load current from no load till 1A was swept in order to
observe the maximum current handling capability of the NMOS LDO. It is seen
in the Figure (5.10), that the output voltage Vldo_out drops to 1.475V when the
load current is 1A. This means that the % error is only 1.6%. The DC load
regulation is calculated for a current load from 1mA to 500mA from the
Figure (5.9) to be
% DC Load regulation =
1.495 − 1.492
*100 = 0.6%
(500 − 1)e − 3
which is within our specification of 1% (See Table 1.1, Section 1.7)
55
Drop Out Voltage=160mV
Figure(5.9) DC Sweep and the Drop-Out Voltage Simulation
Figure (5.10) LDO Output voltage vs Load Current
56
5.9 PSRR Calculations
The Power Supply Rejection Ratio is defined as the ratio of the variation in the
output voltage to the variation in the supply voltage. The variation is modelled
as a small signal in the supply Vldo_in and VBAT . The variation in the output
voltage is measured and the output voltage (Vldo_out) in decibels is plotted.
Ideally for a NMOS LDO, the PSRR is infinity because the NMOS power
transistor is biased in saturation region and any variation in Vldo_in doesn’t
change its current, provided the error amplifier has no variations. For 1.5V
output scenario at 500mA load current and 470nF load capacitor, the PSRR at
1MHz is –32dB. This is shown in the Figure (5.11).
Figure(5.11) PSRR of the NMOS LDO
5.10 Monte-Carlo Simulations
The transistors have been dimensioned in such a way that the mismatch spread
of these transistors should result in a 4σ spread of 2%. This is possible only if
the W.L is big enough according to [6]. At the same time bigger W.L results in a
bigger parasitic capacitances and could hamper the speed of the LDO. Hence
optimisation is done by analysing the spread by running Monte-Carlo
simulations and then re-running the AC and Transient simulations. The
Histogram indicating the spread in terms of σ is shown in the Figure (5.12).The
simulation has been performed for lower voltage ranges of VISA and VBAT.
From this σ value, the mismatch spread in terms of percentage is calculated.
57
4σ
*100
X
where X is the mean value and σ is the standard deviation.
% spread =
Here we get σ as 11.6mV and X = 1.4759V
4*11.6e − 3
% spread =
*100 = 3%
1.4759
Figure(5.12) % Spread of the Output Voltage of the NMOS LDO
5.11 Equivalent Output Noise
The equivalent output noise is also small in µV per sqrt(Hz) range at
low frequencies with the noise decreasing at high frequencies. This is
shown in Figure(5.13). The equivalent output noise is a measure of the
performance of the LDO. This can also be considered as a Figure Of Merit of
the LDO(FoM). Lower the noise output, higher the FoM.
58
Figure (5.13) Equivalent Output Noise of the NMOS LDO
5.12 Summary
The improved frequency compensation of the NMOS LDO has been discussed
in this chapter. The issues associated with the LDO in Chapter 4 have been
solved and verified through simulations. The Power Sense Construction that
enables the LDO output to have an output voltage error of less than 1%has been
discussed. Very important to be noted is that the load capacitor should be
placed as close as possible to the pin. Placing away results in larger inductance
which would result in a higher gain at high frequencies when the phase would
be greater than 180° resulting in oscillations at the output.
5.13 References
[1] Analog Circuit Design by J.Huising, R.J van der Plassche and W.Sansen
[2] Advanced Low Voltage and High Speed Techniques for BiCMOS, CMOS
and Bipolar Operational Amplifiers, by K.J.de Langen, Kluwer Publishers.
Ph.D Thesis, TU Delft.
[3] Microelectronic Circuits, 5th edition, Sedra/Smith.
[4] Design Of Analog Integrated Circuits & Systems, Kenneth.R.Laker and
Willem.M.C.Sansen.
[5] Positive feedback Compensation in Operational Amplifiers by J.Ramos and
M.Stayeart.
[6] Analogue-Digital ASICs circuit techniques,design tools and applications,
Edited by R.S.Soin,F.Maloberti and J.Franca, Peter Peregrinus Ltd for
IEEE.
59
6Additional Features In The NMOSLDO
_____________________________________________________________________
6.1 Programmability of the output voltage
The NMOS LDO has been designed for 1.5V output. The output of the NMOS
LDO can be changed by changing the feedback point. This is explained in the
Figure (6.1) with a simple NMOS LDO structure.
Vref
VLdo_in
+
-
VLdo_out
Ra
IL
CL
Rb
Figure (6.1) Programmable Output NMOS LDO
The value of Ra can be varied and so the feedback factor ‘β’ which in turn
generates a different output voltage. In the design discussed here so far the
output could be programmed from 1.5V down to 0.6V. Every tap point is
connected through a switch to the inverting terminal of the error amplifier.
The switches will be selected by means of decoder. The number of inputs
to the decoder depends upon the number of programmable taps we
would like to have.
We have the worst case feedback when ‘β’=1. We open the loop
during the open loop AC simulation (Section 3.6). Even though the
parameters of the transistors remain the same, the open loop gain and the
UGB of the LDO increase when the output voltage is programmed from
1.5V to 0.6V. Hence the worst case situation of the LDO to guarantee stability
is the 0.6V scenario.
The AC characteristics for the 0.6V output are shown in the Figure (6.2)
and the phase margin is plotted versus load currents separately in the
Figure (6.3). The phase margin is 90° for larger load currents and no load
situation. A decrease in phase margin close to 25° is observed for smaller
60
currents around 200µA. The phase margin then increases towards 90° for
larger load currents.
Figure (6.2) AC Characteristics for 0.6V output
Figure (6.3) Phase Margin at 0.6V output
61
The transient characteristics of the 0.6V output for a load step from 1mA to
500mA is shown in the Figure (6.4).
Figure (6.4) Transient Output for 0.6V
6.2 ECO Mode
There always arises a situation when the load current can reduce to 15mA. This
mode is called as the ECO mode or the Stand By Mode of the applications like
the Cellular Phones, Apple IPODs etc.
In this mode the expected quiescent current is only of the order of the 15µA
and the stability should be guaranteed. The design approach is straight forward
by reducing the bias currents to the error amplifier and the level shifter. This is
shown in the Figure (6.5) for 0.6V output. Also the simulation results are
shown for the 0.6V output. The AC response for the ECO mode is shown in
the Figure (6.6). The phase margin plot is shown in the Figure (6.7).
If the load current in the ECO mode increases to 40mA then we need to
increase the C damping capacitor or the bias currents in order to avoid the
gain bump. The first solution is preferred in order to stay within 15µA
quiescent current consumption.
62
Figure (6.5) ECO Mode Implementation
63
Figure (6.6) ECO Mode: AC Characteristics at 0.6V
Figure (6.7) Phase Margin in ECO Mode for 0.6V output
64
The transient characteristics for a load step of 100µA to 20mA at 0.6V output is
shown in the Figure (6.8).
Figure (6.8) Transient Response in ECO Mode
6.3 Adaptability Of The LDO To Scalable Load Currents
The NMOS LDO shown in the Figure (5.5) delivers a programmable
voltage. The resistive divider is made programmable by changing the
feedback point across the Resistors .i.e. ‘β’.The second feature is the
adaptability of the NMOS LDO. The LDO in the Figure (4.5) handles a
maximum current of 500mA. In case the maximum current is set to 250mA or
even lower the LDO can be adapted just by scaling down the dimension of the
power transistor and the load capacitor accordingly. When we decrease the
current by a factor of 2, we also decrease the dimension of the power transistor
by a factor of 2 and the load capacitor by a factor of 2. This means that in the
AC domain our poles remain the same as the scaling is proportionate. This is
shown in Table 6.1. Since the pole locations remain the same and the UGB
unchanged, the overshoot and undershoot remain the same in the transient
domain. The zeroes fall at very high frequencies and have no impact on the
performance of the LDO. This means that if we use 470nF for a load of
500mA, we can scale down our load capacitor accordingly for lower load
currents as shown in Table 6.2.
65
Table 6.1 Impact of Poles and UGB with Load Current Scaling
S.No Load
Currents
1.
ILoad
First Pole
UGB
Second Pole
1
2π gmxRxR1Cc
gm1
2π CC
gmpgmxCCR1
2π CLCx
2.
500mA
1
2π gmxRxR1Cc
gm1
2π CC
gmpgmxCCR1
2π CLCx
3.
350mA
250mA
Independent
of the load
Current
Independent
of the load
Current
0.7 * gmpgmxCCR1
= Same as 500 mA condition
2π CL * 0.7Cx
4.
Independent
of the load
Current
Independent
of the load
Current
5.
150mA
Independent
of the load
Current
Independent
of the load
Current
6.
100mA
Independent
of the load
Current
Independent
of the load
Current
7.
50mA
Independent
of the load
Current
Independent
of the load
Current
g mp
gmxC CR1
2
= Same as 500 mA condition
CL
2π
Cx
2
g mp
g mxC C R 1
3
= Same as 500 mA condition
CL
2π
Cx
3
g mp
g mxC C R 1
5
= Same as 500 mA condition
CL
2π
Cx
5
gmp
gmxCCR1
10
= Same as 500mA condition
CL
2π
Cx
10
Table 6.2 Load Currents Vs Load Capacitors
S.No
Load Current
Load Capacitor
1.
500mA
470nF
2.
350mA
330nF
3.
250mA
235nF (220nF)
4.
150mA
150nF
5.
100mA
94nF (100nF)
6.
50mA
47nF
66
6.4 Cap Free Option
gmp
, we
2π CL
could also connect a wide range of capacitors for the LDO. This is called as the
cap free option. From calculations, we see that we can connect any load
capacitor between 470nF to 470µF. This still will make the output pole to be
beyond the UGB. Connecting the maximum capacitor will have a better phase
margin at no load, medium load current situation. The dominant pole is from the
Load capacitor for a range of currents from 0 to 10mA and as the current
increases, the Miller capacitor dominates and the phase Margin at full load is
around 45°. This is because the second pole has moved closer to the UGB such
that the phase margin is 45°. The phase margin plot (vs) the load current on a
logarithmic scale is shown in the Figure (6.9).
Since we see that the output pole moves beyond its limiting value
Figure (6.9) Phase margin Vs Load Current with a 470µF load capacitor
6.5 Summary
The additional features like the programmability of the output voltage, ability to
use the same NMOS LDO in the ECO mode and the adaptability of the NMOS
LDO transistor dimensions and load capacitors when load currents scale down
were discussed.
67
7
Conclusions And Future Work
_____________________________________________________________________
The thesis is about the design techniques of an NMOS power transistor based
LDO. In Chapter 1, the PMU was introduced along with the need for the NMOS
LDOs.
In Chapter 2, the design approaches for the PMOS LDOs were discussed in
order to verify if the same approach can be used while designing the NMOS
LDOs.
In Chapter 3, the conventional design of the NMOS LDOs were discussed,
along with the problems associated while adapting the LDO to scalable load
currents.
In Chapters 4 and 5, the motivation for the frequency compensation of the
NMOS LDO along with the improved damping technique was discussed.
In Chapter 6, the additional features related to the NMOS LDO like its
programmable output voltage, ECO mode and load adaptability were discussed.
In Chapter 7, a summary of the first 6 chapters has been presented in nutshell.
Future Work
Even though this NMOS LDO design has met the specifications that are needed
for an LDO to be used in a mobile PMU, there is always a scope for
improvement. The major improvement should be to improve the phase margin
of the NMOS LDO at low load currents. In this design the phase margin is about
25° to 30° for load currents between 200µA to 2mA. The phase margin should
be improved for these currents. Also the NMOS LDO could be made faster or
the UGB can be increased in order to achieve the best transient response.
68
Appendix- I
Small Signal Analysis Of The Compensated NMOSLDO
Writing the nodal equations At the node Vx
gm1V 1 +
Vx
+ (Vx − Vo)sCc = 0 → (1)
R1
⇒ gm1V 1 = Vx(1 + sCcR1)
⇒ Vx =
sCcVo − gm1V 1
→ (2)
1 + sCcR1
Assuming C1<Cc. We neglect C1 to simplify the calculations
At the node Vy
gmxVx +
Vy (1 + sCxRx)
= 0 → (3)
Rx
⇒ Vy = −
gmxVxRx
→ (4)
1 + sCxRx
At the level shifter node VL
VL
gmL (VL − Vy ) +
+ (VL − Vo) sCp = 0 → (5)
RLS
1 ⎞
⎛
⇒ ⎜ gmL + sCp +
⎟ VL − gmLVy = sCpVo → (6)
RLS ⎠
⎝
Since RL ~ 1/gmLS equation (6) gets reduced to
(2 g m L + sC p )V L − g m L Vy = sC pVo
(2g m L or g m L doesn't m ake m uch difference here)
⇒ ( g m L + sC p )V L − g m L Vy = sC pV o
⇒ VL =
⇒ VL =
g m L Vy + sC pVo
g m L + sC p
− gmL
g m xV xR x
+ sC pVo
1 + sC x R x
→ (7)
g m L + sC p
69
At the output node Vo we get
(V x − V o ) sC c + (V L − V o ) sC p = g mp (V o − V L ) +
⇒ (V x − V o ) sC c + (V L − V o ) sC p =
Vo
1 ⎞
⎛
⎜ R e sr +
⎟
sC
L ⎠
⎝
sC L V o
+ g mp V o − g mp V L
sC L R e sr + 1
sC L
⎛
⎞
⇒ sC cV x + ( g mp + sC p )V L = V o ⎜
+ g mp ⎟
⎝ sC L R e sr + 1
⎠
∵ C c , C p << C L
g mxV xR x
⎡
⎛
⎞⎤
⎢
⎜ − g mL 1 + sC xR x + sC p V o ⎟ ⎥
sC L
⎛
⎞
⇒ sC cV x + ⎢ ( g mp + sC p ) ⎜
+ g mp ⎟
⎟⎥ = Vo ⎜
g mL + sC p
⎝ sC L R e sr + 1
⎠
⎢
⎜
⎟⎥
⎝
⎠ ⎦⎥
⎣⎢
sC p << g mp & sC p << g mL
⎡ ⎛ g mp ⎞ ⎛
g mxV xR x
sC L
⎞⎤
⎛
⎞
⇒ sC cV x + ⎢ ⎜
+ sC p V o ⎟ ⎥ = V o ⎜
+ g mp ⎟
⎟ ⎜ − g mL
1 + sC xR x
⎠⎦
⎝ sC L R e sr + 1
⎠
⎣ ⎝ g mL ⎠ ⎝
⎛
g mp g mxR x ⎤
sC L
g mp sC p ⎞
⎡
⇒ V x ⎢ sC c −
= Vo ⎜
+ g mp −
⎟
⎥
e
1
R
1
+
sC
R
sC
+
g mL ⎠
x
x
L
sr
⎣
⎦
⎝
g mp g mxR x ⎞
⎛ ( sC cV o − g m 1V 1) R 1 ⎞ ⎛
⇒⎜
⎟ ⎜ sC c −
⎟
1 + sC cR 1
1 + sC xR x ⎠
⎝
⎠⎝
⎛ sC L g mL + g mp g mL ( sC L R e sr + 1) − g mp sCp ( sC L R e sr + 1) ⎞
= Vo ⎜
⎟
g mL ( sC L R e sr + 1)
⎝
⎠
⎡ s 2 ( C c ) 2 R 1 − sC cg mxg mp R xR 1 { g mp g mL ( sC L R e sr + 1 ) − sC p g mp ( sC L R e sr + 1 ) + s C L g mL} ⎤
⎥
⇒ Vo ⎢
−
g mL ( sC L R e sr + 1 )
⎢⎣ (1 + sC xR x )(1 + sC cR 1 )
⎥⎦
g m 1V 1 R 1 ⎡⎣ sC c (1 + sC xR x ) − g mxg mp R x ⎤⎦
=
→ (8)
(1 + sC cR 1)(1 + sC xR x )
In the above calculations, VL has been expressed in terms of Vx. Refer to
equation (7).
The s2 terms can be neglected in order to make the calculations simpler and
By substituting similar values for the parameters like the previous
Calculations we infer that, the s 2 terms will have an impact only at
frequencies in the Giga Hertz range. Still simplifying the equation (8) we get
approximately
70
⎡ − gmxgmpRxsCcR1
{gmpgmL(1 + sCL Re sr ) + sCLgmL)} ⎤ gm1V 1R1 [ sCc (1 + sCxRx) − gmxgmpRx ]
Vo ⎢
−
⎥=
(1 + sCxRx )(1 + sCcR1)
gmL(1 + sCL Re sr )
⎣ (1 + sCxRx )(1 + sCcR1)
⎦
⇒
=
Vo [ − gmxgmpRxsCcR1 gmL (1 + sCL Re sr ) − {{gmpgmL (1 + sCL Re sr ) + sCLgmL)}(1 + sCxRx )(1 + sCcR1)}]
(1 + sCxRx )(1 + sCcR1) gmL (1 + sCL Re sr )
gm1V 1R1 [ sCc (1 + sCxRx ) − gmxgmpRx ]
(1 + sCxRx )(1 + sCcR1)
⇒
gm1 gmLR1 [ sCc(1 + sCxRx ) − gmxgmpRx ][1 + sCL Re sr ]
Vo
=
V 1 [− gmxgmpRxsCcR1 gmL(1 + sCL Re sr ) − {{gmpgmL (1 + sCL Re sr ) + sCLgmL)}(1 + sCxRx )(1 + sCcR1)}]
⎡ sCc
⎤
gm1R1 gmxRx ⎢
− gmp ⎥ [1 + sCL Re sr ]
Vo
⎣ gmxRx
⎦
⇒
=
→ (9)
V 1 [− gmxgmpRxsCcR1(1 + sCL Re sr ) − {{gmp (1 + sCL Re sr ) + sCL}(1 + sCxRx )(1 + sCcR1)}]
(∵ sCc >> s 2CcCxRx )
Equation (9) highlights us the transfer function of the NMOS LDO which
has been derived from the basic model as in fig(1).
Poles and Zeroes
The numerator in the transfer function when equated to zero results in the
“Zeroes” of the transfer function while the denominator when equated to
zero results in the “poles” of the transfer function.
Starting with the poles we equate the denominator of the equation to the
standard format
s
s2
+
→ (10)
p1 p1 p 2
with the assumption that p1 is dominant that p 2. p1 and p 2 are the two poles.
1+
By neglecting the s 2 terms and the sC L R esr term we can simplify the
denominator of equation(9) as
⎛ CL
⎞ s 2CLCxRx
1+ s ⎜
+ CxRx + gmxRxCcR1 ⎟ +
→ (11)
gmp
⎝ gmp
⎠
71
Equating the ‘s’ and the ‘s2’ terms we can get the expressions for the first and
the second pole.
1 CL
=
+ CxRx + gmxRxCcR1
p1 gmp
⇒ p1 =
gmp
CL + (CxRx + gmxRxCcR1) gmp
Similarly
⇒ p2 =
p1 p 2 =
→ (12)
gmp
CLCxRx
( CL + gmpCxRx + gmxgmpRxCcR1) → (13)
gmp
=
CLCxRxp1
CLCxRx
Now we look at the zeroes in the transfer function by equating the numerator to
Zero with an assumption that sCc << s2CcCxRx
⇒ gmLgm1( s 2C cC xRx − gmpgmxRx ) = 0
⇒ fz1 ~
gmpgmx
2π C cC x
(1 + sC L R e sr ) = 0
−1
⇒ fz 2 = −
2π R e srC L
→ (14)
→ (15)
The zero due to the compensation capacitor is located at high frequencies in the
order of hundreds of Giga Hertz range at no load to thousands of Giga Hertz in
the full load condition. Also we have a Left Hand Plane Zero due to the load
capacitor and its equivalent series resistance.
A single pole system is unconditionally stable. At low load situations we
have a two pole system. But the second pole can be moved by reducing the
output impedance of the amplifier i.e. the value Rx.
72
73
Appendix- II
Load Step Simulations from 0 to 500mA
We saw in the previous sections, that the transient step was from 1mA to
500mA which means that the minimum current load is 1mA and the maximum
load current is 500mA. Nevertheless the minimum load current can be zero, say
for example the load gets switched off or in real life situation when the LDO is
powered first before the load. Very important is that in real life situations the
LDO never sees a step of 500mA as soon as the load is turned ON. Over a span
of time the maximum load current is 500mA. This is shown in the Figure below.
LDO
Sum of the Load Currents is 500mA
CLOAD
The load current in most of the applications reaches its maximum value of
500mA in a staircase fashion.
500mA
Load
Current
0 mA
Time in µs
Load Current Reaching its Maximum Value
74
The transient simulation for such a staircase load step is shown below for the
1.5V and 0.6V voltage outputs.
Transient Response For A Staircase Load Current Step
75
Also the transient simulation for the load step from 0 to 500mA is shown below
for 1.5V and 0.6V output voltages. Here the overshoot and undershoot are high,
even around 7.5% because the LDO is not fast for load currents less than
100µA. The duration of the output voltage peaks and dips are 4ms.
LDO Output Voltage For A 0 to 500mA, Load Step rising and falling in 1µs
76