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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998
A 723-MHz 17.2-mW CMOS Programmable Counter
Hun-Hsien Chang and Jiin-Chuan Wu
Abstract—A high-speed complementary metal–oxide–semiconductor (CMOS) programmable divide-by-N frequency divider
was proposed. Using a new end-of-count (EOC) detecting and
reloading algorithm, the reloading delay is distributed over three
clock cycles, which increases the operating frequency. The simulated operating frequency of the new counter is 581 MHz, which
is 2.2 times higher than that of a conventional programmable
counter. The new programmable counter was implemented in a
0.8-m CMOS technology. The active die area is 480 2 100 m.
The counter was measured to operate at 723 MHz with 5 V power
supply and dissipates 17.12 mW.
[10], a reloading scheme for a CMOS programmable counter
was proposed to extend the operating speed to 1.75 GHz.
In this paper, we propose a low-power, high-speed reloading
algorithm, which has a lower power/megahertz than that of
[10]. Section II of this paper discusses the counter reloading
algorithm, which is the most critical speed-limiting factor.
Section III gives the experimental results, and Section IV is
the conclusion.
Index Terms— CMOS digital integrated circuits, flip-flop circuits, logic design, phase-locked loops, programmable circuits.
II. COUNTER RELOADING ALGORITHM
I. INTRODUCTION
F
REQUENCY synthesizers are widely used in communication systems [1], [2] and microprocessors [4], [5]. The operating frequency of a frequency synthesizer is limited by the
frequency divider and the voltage-controlled oscillator (VCO).
There are three kinds of frequency dividers: cascaded divideby-two counter, dual-modulus prescalar, and programmable
divide-by- counter. Asynchronous cascaded divide-by-two
counter has the highest operating frequency because its operating speed is only limited by the delay of a -type flip-flop.
However, it has limited usage because it can only divide
where
is the number of cascaded stages.
frequency by
Both dual-modulus prescalar and programmable divide-bycounters are slower because the programming circuit adds additional delay. Dual-modulus prescalars have higher operating
frequency than programmable counters because their programming circuit has smaller loading. Implemented in complementary metal–oxide–semiconductor (CMOS) technology, dualmodulus prescalars operated at 1.2–1.8 GHz [5]–[7], and programmable counters operated at 400–550 MHz [8], [9]. Dualmodulus prescalar is configured as a divide-bycounter, where
is typically set to
Hence, its frequency
dividing ratio has limited range. However, in communication
systems, the desired output range of the frequency synthesizer
is usually limited. Thus, using dual-modulus prescalar in communication systems is the most efficient solution in terms of
speed, power, and die area. However, when the dividing ratio
where
is an arbitrary integer, then
must be from two to
the programmable divide-by- counter is the only choice. In
Manuscript received January 2, 1997; revised March 24, 1998. This work
was supported by the National Science Council, Taiwan, R.O.C., under
Contract NSC 87-2215-E-009-027 and by the Chip Implementation Center,
National Science Council, Taiwan, R.O.C.
The authors are with the Integrated Circuits and Systems Laboratory,
Department of Electronics Engineering, National Chiao-Tung University,
Hsinchu, Taiwan 300 R.O.C.
Publisher Item Identifier S 0018-9200(98)07000-0.
The programmable counter’s basic function is to obtain a
lower frequency from a higher frequency. In the conventional
counter, shown in Fig. 1, the
programmable divide-bycounter stages are fed to the end-ofoutputs of all the
count (EOC) detector. It is assumed that a countdown counter
was used. Once the counter reaches the terminal count state
(state 0), the EOC detector signals the reloading circuit to
and the cycle repeats. Thus,
reinitialize the counter to state
the relationship between the input and output frequencies is
With
counter stages, the frequency dividing
can be varied from 2 to 2
factor
The timing diagram in Fig. 2 shows the activities during the
EOC clock cycle of a six-stage programmable counter. It is
assumed that the counter stage is positive edge triggered and
the counter state is 000 001, i.e.,
and
(see Fig. 1). Following the rising edge
of the next clock cycle, five events occur in sequence.
1) After a clock-to- delay of the -type flip-flop
the counter enters the terminal state 000 000, i.e., all the
inputs to the EOC detector are zero.
the EOC detec2) After an EOC detector delay time
tor’s output (the reload signal) becomes high to reload
Note that the reload signal is the
the counter to state
output signal of the programmable counter because its
For the convenience of discussion,
frequency is
or 100 010 in binary format.
let
the counter state is
3) After the reloading delay time
i.e., the inputs of the EOC detector are not all zeros.
4) The output of the EOC detector will become low after
to disable the reloading
another EOC delay time
circuit so that the counter can count down at the rising
and
were used
edge of the next clock. Note that
to denote the first and second EOC gate delays because
these two delays are different.
exists
5) To actually enable the counter, a time delay
between when reload becomes low and the counter
leaves the reset status. Since all the activities mentioned
above must be completed within one clock cycle, the
0018–9200/98$10.00  1998 IEEE
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998
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Fig. 1. Block diagram of a programmable counter.
N counter.
Fig. 2. The timing of a conventional divide-by-
Fig. 4. The simulation result of the traditional programmable counter operated at 263 MHz.
Fig. 3. The traditional end-of-count detecting circuit.
clock period
must be greater than
From the above analysis, it is clear that decreasing counter
alone is not enough to increase the programmable
delay
counter’s speed greatly. The EOC detector delay and reloading
delay also need to be minimized. Fig. 4 shows the simulation
results of a conventional six-stage programmable counter, with
the EOC detector shown in Fig. 3. The frequency dividing
factor was set to 34. Comparing Figs. 2 and 4, one can find
is 0.41 ns,
is 0.66 ns,
is 0.99 ns,
is 1.12
that
is 0.58 ns. The minimum clock cycle time is 3.8
ns, and
ns, i.e., the maximum operating frequency is 263 MHz. Note
that the first EOC delay TE1 is substantially smaller than the
second EOC delay
The new EOC circuit is shown in Fig. 5. This EOC detector
is modified to detect the 000 010 state instead of the allzero condition. The output of the EOC detector (node
is connected to a one-bit register that is clocked by the input
The simulated timing diagram of the last three clock
clock
cycle is shown in
cycles in a countdown-by-
Fig. 5. The new end-of-count detector with
Q0 feedback.
0
Fig. 6. Following the rising edge of the third to last clock
cycle, the counter state changes from 000 011–000 010 after a
Then, the EOC detector output
clock-to- delay
becomes high after an EOC delay time
(delay from node
to
in Fig. 5), which is equal to one NAND gate delay
plus one NOR gate delay. These two operations must be finished
Following
within one clock cycle, i.e.,
the rising edge of the second to last clock cycle, the output
becomes low after the clock-toof the one-bit register
delay of the one-bit register
The node
becomes
which is node
to
low after another EOC delay
delay. Node D0 must return to zero within this clock cycle,
In the meantime, the reload signal
i.e.,
becomes high after an inverter delay, which causes the counter
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998
Fig. 7. The photograph of the proposed chip.
Fig. 6. The simulation result of the new programmable counter operated at
581 MHz.
to be reset to state
The counter reloading time
is the
time from
’s becoming low to the counter state’s becoming
Note that the resetting of the counter state to
does not
have to finish within this cycle; this will be explained below.
Following the rising edge of the last clock cycle, the counter
remains in state
because the reload signal is high at the
clock’s rising edge. Since
must be low by the end of the
previous clock cycle, the rising edge of this clock cycle sets
to high after a
- delay, which releases the counter stages
from the reloading status so that the counter stages can count
down again at the next rising edge of the input clock. This
(set signal of counter stage
being
condition is seen as
reset to zero. The counter enabling delay
is the time from
’s becoming high to ’s becoming low. Thus, the timing
constraint is
However, there is another
timing constraint. After
becomes one,
is no longer
forced to zero by
and the value of
is now determined
by the value
i.e., before the end of this clock cycle,
must
be set to zero by the EOC detector. The timing constraint starts
at the second last cycle. After a - delay,
becomes low;
delay, the counter value is set to
after an EOC
after a
detector delay
which is the delay from the higher four
bits to
node
should be zero within two clock cycles.
Thus, the timing constraint is
In this way, the time to reinitialize the counter stages is
extended to three clock cycles, i.e., the operating frequency
will be increased. From the simulation results shown in Fig. 6,
one can find that
is 0.73 ns,
- is 0.38 ns,
- is
0.54 ns,
is 0.46 ns,
is 0.8 ns,
is 1.37 ns, and
is 1.35 ns. The minimum clock cycle time is 1.72 ns, i.e., the
maximum operating frequency is 581 MHz, which is 2.2 times
higher than the 263 MHz of a conventional programmable
counter. Note that slower speed static -type flip-flops and
logic gates, instead of the faster dynamic gates in [5]–[7] and
[10], were used in this design because our emphasis is on
Fig. 8. Block diagram of test chip.
reducing the critical path delay by means of a better algorithm,
not by using a faster gate. The power consumption of the
counter is 13.8 mW. The power of the six counter stages is
5.625, 2.933, 1.314, 0.677, 0.350, and 0.330 mW, respectively.
The power consumption of the end-of-count and reloading
circuits is 0.831 and 1.715 mW, respectively. It can be seen
that most of the power is consumed in the counter stages. Note
that the power consumption of the end-of-count and reloading
e.g., if
then
circuits is inversely proportional to
its power consumption will be doubled.
III. EXPERIMENTAL RESULTS
The proposed six-stage programmable counter was implemented in a 0.8- m CMOS technology. The active die area
100 m A chip photograph is shown in Fig. 7.
is 480
The block diagram of the test chip is shown in Fig. 8. To
avoid high-frequency input, an internal three-stage VCO and
clock buffer were used to generate the input clock signal of
the counter. A divide-by-eight frequency divider was added
to reduce the frequency at Fvco8 output pin. Since the reload
signal is high only for one clock period, i.e., about 1.7 ns
at maximum operating frequency, a divide-by-two divider
was used to obtain a 50%-duty Fout2 signal. Thus, the
is the input clock
measured Fout2 frequency multiplied by
is the counter dividing factor. The
frequency, where
output of the fourth counter stage (Fq4b) is also probed.
Fig. 9 shows the measured results of the programmable
and 5 V power
counter operating at 723 MHz, with
supply. The horizontal scale is 10 ns per division. The upper
trace is Fvco8, the middle trace is Fout2, and the lower trace
the frequency of Fout2 is 1/48
is Fq4b. With
The frequency of Fvco8 is 1/8
Thus, the frequency
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 10, OCTOBER 1998
SUMMARY
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TABLE I
MEASURED RESULTS
OF
from 2 to 2
According to simulation, the new algorithm
improves the operating frequency by 2.2 times, from 263
to 581 MHz. The new six-stage programmable counter was
implemented in a 0.8- m CMOS technology, and the active
die area is 480 100 m The measured operating frequency
is 723 MHz with 5 V power supply and dissipates 17.12 mW.
REFERENCES
Fig. 9. The measurement results of the new programmable counter operated
at 5 V power supply and 723 MHz.
of Fvco8 should be six times that of the Fout2, which is
observed in Fig. 9. The waveform of Fq4b repeats with a
period of 24 clock cycles. The performance of the counter is
listed in Table I. The counter was measured to operate at 723
MHz with 5 V power supply and dissipates 17.12 mW. The
measured power includes the power of the clock buffer but
does not include the power of the on-chip VCO. The power
dissipation per megahertz of this counter is 23.7 W/MHz.
As a comparison, the performance of other CMOS divide-bycounters was 200 W/MHz [8], 16.9 W/MHz [9], and
28.6–34.3 W/MHz [10]. This counter had been integrated in
a 1–600-MHz phase-locked loop that has a 80 ps measured
jitter [11].
IV. CONCLUSIONS
A new end-of-count detecting and reloading algorithm has
been introduced for a low-power, high-speed programmable
divide-by- frequency divider. The counter implemented was
a six-bit programmable counter, but the design methodology
can be extended to an -bit counter and can be programmed
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