Design Tip
Low power, giga speed programmable
divider in 0.18 m CMOS
By Girish N. Jadhav
T
o meet the stringent low-power consumption and high-frequency operation at
low switching noise of on-chip programmable dividers used in the design of PLL
circuits, this article will focus on the design
and simulation of a new programmable divider architecture for use in the 2.412 GHz
to 2.484 GHz frequency bands. The design is
based on 0.18 micron CMOS technology.
By comparison, the conventional programmable divider consists of a dual-modulus
prescaler (DMP), a program (P) counter
and a swallow (S) counter and is depicted
in the block diagram shown in Figure 1.
A DMP is used to get higher resolution.
A DMP allows the prescaling factor to be
changed between N and N+1. Prescaler divides 2.4 GHz down to the 75 MHz, which
is used for the following loadable counters to
minimize the silicon area and power. Here,
a program counter acts as coarse tuner and
a swallow counter as fine tuner. The counter/
divider M is given as:
M = (N+1) S + N (P – S) = NP + S
For proper functioning of the counters,
S should be smaller than P and S must also
be less than N. The numbers of N, P and S
should be chosen carefully according to the
maximum limitation of the allowable input
frequency of the counters.
The conventional design has the following issues:
 Requires two loadable down-counters.
 Reduces speed, due to delay introduced
in the counter path.
 Increases design complexity while
designing the loadable flip-flops.
 Reduces robustness of the circuit.
 Offers high power consumption at
~24 mW.
 Increases hardware and silicon area.
Proposed programmable divider
The proposed programmable divider
consists of a dual-modulus prescaler (DMP),
an up-counter, an equality detector, an analog MUX and PCFR logic. The conceptual
diagram is shown in Figure 2.
In Figure 2, Fin = sinusoidal input frequency, Fout = output frequency, CR = coarse
register, FR = fine register and PCFR logic
= prescaler, coarse, fine selector and reset
generation block. Now the formula for the
proposed programmable divider is:
M = {( N * CR ) + ( FR * 2 )}
The DMP divides sinusoidal input signal by
Program Counter
In
Prescaler
either N or N+1. That is, DMP will perform
divide-by-32; when MC = 0, and divide-by-33;
when MC = 1. Thus, the input frequency is
divided down to 75.375 MHz, 77.625 MHz
from 2.412 GHz, 2.484 GHz respectively for
MC = 0. The up-counter block operates with
this downed frequency. The up-counter is itself
a programmable frequency divider whose
function is to increment the counter output
on the rising edge of the downed frequency
(CLK) and reset the counter output asynchronously when reset = 1.
The up-counter is an asynchronous divider
constructed by combining 8-cascaded divideby-2 circuits. It starts counting from 0 to 2 L,
where L is the length of the equality detector.
(In this design L = 8).
Initially, the MUX select signal is low,
which means the equality detector compares
FR value with the output of the up-counter, if
both values match then a pulse is generated.
This pulse is used to toggle (switch) the MUX
select signal from low to high.
After toggle, the MUX select is high, which
means the equality detector compares CR
value with the output of the up-counter, if both
values match then again a pulse is generated and
this pulse is used to reset the up-counter.
EQ_DOUT
Divide
by 2
1/P
MUX select
RST-UP-CNT
MC
RST
O/P of Prescaler
1/S
Swallow Counter
D F/F
MC
RST
Figure 1. Block diagram of conventional programmable divider.
POUT
FIN
Prescaler
N / (N+1)
UP
Counter
(8 Bits)
MC=0, ÷N
Reset
MC=1, ÷(N+1)
Equality
Detector
8 Bits
PCFR.
logic
POUT B
FOUT
EQ_DOUT
Divide By 2
Analog MUX. Sel
(8 Bits)
CR
FR
(8 Bits) (8 Bits)
MUX Select
EQ_F
EQ_C
RST-UP-CNT
MC
Figure 2. Block diagram of proposed programmable divider.
62
Figure 3. Operation and waveform of PCFR logic.
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July 2006
Programming CR & FR
Calculated
Cases
Course Register C R
CR7 … CR1, CR0
Fine Register F R
FR7 … FR1, FR0
Simulated
M
Fout
(MHz)
Tout
(nsec)
Fout
(MHz)
Tout
(nsec)
189.055
I
0000 1110  CR=14
0000 0100  FR=04
456
5.28947
189.0547
5.28946
II
0001 1110  CR=30
0000 1100  FR=12
984
2.45121
407.9601
2.45121
407.96
III
0010 0100  CR=36
0000 1000  FR=08
1168
2.06506
484.2454
2.06506
484.246
Table 1. Simulated vs. calculated results.
Both coarse and fine detected pulses are
generated and merged on the same output of
the equality detector.
We can observe that both coarse and fine
generated pulses are merged on the same
output line of the equality detector. It’s important to separate coarse and fine pulses,
which is implemented in PCFR logic.
Coarse pulse is used to reset the up-counter,
set mode control (MC) and toggle the MUX
select signal. Fine pulse is used to reset the
MC and toggle the MUX select signal.
Implementation of PCFR logic
The implementation of PCFR and pulse
separation logic is as shown in Figure 3.
Simulated vs. calculated results are shown
in Table 1 for Fin = 2.412 GHz, prescaler
N = 32, Tout = 1/Fout = 1/(Fin/M) and
M = {( N * CR ) + ( FR * 2 )}
Based on the above, the current consumption was 2.84 mA at 1.3 V, with power
consumption at 3.692 mW at 1.3 V. RFD
References
1. Xi Li, “Evaluation of RF CMOS IC
Technology for Wireless LAN Applications,”
A proposal presented to the graduate school of
the University of Florida in partial fulfillment
of the requirements for the degree of Doctor
of Philosophy, February 2002.
ABOUT THE AUTHOR
Girish N. Jadhav is a senior member of
technical staff 1 at Ikanos Communications
in Fremont, Calif. where he is involved in
silicon characterization of analog transmitters and receivers. Prior to Ikanos, Jadhav
worked on analog PLL design as a design
engineer at Acer Laboratories. He holds a
BE in electronics and telecommunication
from Karnataka University in India.
COMINGINDECEMBER
2007
U.S.Radio
Frequency Allocations
Wall Chart
64
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July 2006