2015 IEEE International Symposium on Radio-Frequency Integration Technology
FR2B-1
An 80 GHz Programmable Frequency Divider for
Wideband mm-Wave Frequency Ramp Synthesis
M. van Delden∗, G. Hasenaecker∗, N. Pohl† , K. Aufinger‡ and T. Musch∗
† Fraunhofer
∗ Institute
of Electronic Circuits, Ruhr-Universität Bochum, Germany
Institute for High Frequency Physics and Radar Techniques, Wachtberg, Germany
‡ Infineon Technologies AG, Neubiberg, Germany
Abstract—A programmable frequency divider operating at
input frequencies from DC to 80 GHz for the use in fractionalN synthesizers is presented. The division factor can be set to
all integer values between 12 and 259 and is applied by an
8 bit parallel interface for fast modulation. The remarkably
high input frequency in combination with the programmability
is achieved by a dual-modulus concept and differential emittercoupled logic with a consequent merging of logic gates into flipflops. Among this, a reset function has been implemented to
synchronize multiple synthesizers. The frequency divider has been
realized in a SiGe BiCMOS technology (fT /fmax =250/360 GHz).
The divider works at a supply voltage of 3.3 V with a power
consumption of less than 390 mW.
fref
PFD
fS
LF
fV
fLO
f0
fref
÷N
PFD
LF
fS
fractional
logic
÷N
÷N
fractional
logic
const.
(a)
(b)
Fig. 1. Block diagram of the divider’s proposed applications: (a) in the
feedback loop of an offset-PLL and (b) as a reference frequency ramp
generator.
Prescaler
Prog. Dividers
A&B
Sync. Output
FF
Buffer
Delay
fin
fout
I. I NTRODUCTION
Q
S
The progress in SiGe technologies enables the realization
1
fA
A
D
4/5
of monolithic microwave integrated circuits with constantly
fps
DA R L
increasing frequencies and bandwidths at low cost. Thus
MC
B
improved frequency synthesizers offer access to high-end miDB L
crowave measurement systems, such as high precision FMCW
6
2
radar systems [1] or vector network analyzers.
Control Logic R
N 8
The key to high performance systems are highly linear frequency ramps with ultra-low phase noise and high bandwidth.
Fig. 2. Block diagram of the dual-modulus divider with synchronizing flipA common concept for microwave frequency synthesizers is
flop.
to stabilize a voltage-controlled oscillator (VCO) in a phaselocked loop (PLL). Among others, two principles are appliII. A RCHITECTURE
cable for wideband frequency ramp generation in this case.
The presented divider is based on the dual-modulus concept
Firstly, as shown in Fig. 1(a) and described in detail in [1], a
as shown in Fig. 2. This concept enables high input frequencies
constant reference frequency is used and the the division factor
for programmable dividers. On the one hand only the prescaler
of the frequency divider in the feedback loop of an offset(Fig. 3) has to handle the very high input frequencies with
PLL is switched. The second principle is applying a frequency
just a simple logic, switching the prescaling factor between
ramp to the reference input of a conventional PLL and using
4 and 5. On the other hand the complex logic is shifted into
a constant division factor in the feedback loop, as depicted in
the following fully programmable dividers A and B, which
Fig. 1(b). The reference frequency ramp is generated by a high
therefore operate maximum at a quarter of the input frequency.
frequency signal source and a second frequency divider, whose
In [4] the division factor N of the complete circuit is derived:
division factor is alternating, as described in [2].
In both cases a frequency divider with a wide division
N = 4 · NA + NB
(1)
factor range starting at a low value, a high input frequency as
well as low residual phase noise is crucial, due to the required
Due to the wideband application, division factors N selectable
ultra-low phase noise at the VCO’s output. Furthermore, the
from the entire integer range from 12 to 259 are beneficial. This
high demand for ramp linearity can be achieved by a fractionalis realized as we use a 6 bit divider A and 2 bit divider B. The
N frequency division, which requires a change of the division
division factors 256 to 259 are caused by a clock cycle delay
factor with every output cycle of the divider. Compared to
in divider A. An 8 bit parallel interface, applying the division
our earlier work presented in [3], we improved this frequency
factor, enables fast modulation in fractional-N synthesizers.
divider especially by the integration of a reset function, a
The core of divider A, shown in Fig. 4, consists of a
larger output-pulse-width and the implementation in a new
synchronous up counter built with T flip-flops. Reaching a
technology for increasing the maxmimum input frequency
value of 62 is detected by the 6-times AND. Synchronized
from 57 GHz to 80 GHz.
by the flip-flop S3 this creates the load signal L with a pulse978-1-4673-7794-2/15/$31.00 © 2015 IEEE
181
MC
& D Q
& D Q
D
fps
Q
fin
S2
S3
&
Q1
Q0
D Q
T Q
L
L
SR
SR
&
Q2
T Q
L
SR
&
Q3
T Q
L
SR
&
Q4
A0
A1
VCC
Q
Q
L
T Q
L
SR
&
A3
A2
6 bit data register
A4
VCS
Q5
T Q
L
SR
L
fin
R
Emitter
Follower
RS
C
C
output pulse generation
QD&
D-Latch 2
RC RC
L
up-counter
Q D ≥1
Emitter
Follower
RT
T
S
Fig. 3. Block diagram of the 4/5-prescaler based on a Johnson ring counter
with logic integrated into the D flip-flops for setting the prescaling factor.
fA
D-Latch 1
XOR
Set/Reset
on Load
RC RC
Rbias
REF1
REF1
Rbias REF2
REF2
Fig. 5. Schematic of the T flip-flop consisting of a D flip-flop with merged
XOR and set/reset function on load [3] as an example for merged emittercoupled logic.
A5
III. D ESIGN
During the design of each gate several aspects have to be
considered to maximize the dividers operating frequency [6].
All gates are realized in differential emitter-coupled logic using
differential bipolar transistor pairs as current switches, which
are applied to emitter followers for fast loading and unloading
the input capacitance of the following stages. To increase the
operating speed we consequently merged logic gates into flipflops, by series conjunction of current switches. For a supply
voltage of 3.3 V four stacked logic levels, provided by resistive
as well as emitter follower based level shifting, can be realized,
as shown in Fig. 5.
The divider is designed and realized in Infineon’s new
SiGe BiCMOS technology B11HFC. This technology includes
high speed hetero bipolar transistors with a transit frequency
f T = 250 GHz and a maximum oscillation frequency f max =
360 GHz, which were consequently used. As the transistor
capacitances, especially C CB , are the dominating limiting
factors for maximum operating speed without increasing the
power consumption dramatically, it is crucial to choose a small
transistor size of 0.22 µm × 1 µm. We designed the transistors
maximum peak current densities with 14.3 mA/µm2 , but allways made sure that the effective current densities are still
below the recommended design current density for maximum
f T of 11.5 mA/µm2 .
Simulations during designing of the prescaler have been
solved with the delivered HICUM model [7] due to the
very high current densities. Where this model is attesting a
maximum input frequency of 88 GHz, the Spice Gummel-Poon
model (SGPM) ends at 69 GHz. Designing the programmable
dividers was mostly supported by SGPM simulations and validated by a few HICUM simulations, because the current densities here are lower and the large amount of transistors results in
a dramatically high simulation time using the HICUM model.
All simulations have been done without parasitic extraction of
the wire capacitances.
Fig. 4. Block diagram of 6 bit divider A with up-counter and output-pulse
generation.
width of one clock cycle of divider A’s input frequency f ps .
This signal is buffered and loads the value DA in the next cycle
into the counter, resulting in a division factor NA = 64 − DA ,
due to the 2 clock cycle delay. This enables different division
factors every cycle of the whole divider, which is essential for
fractional-N synthesizers.
In the usual concept, as presented e.g. in [4], the load
signal would be the output signal of divider A as well. But
we extended the output pulse generation for two reasons.
First, the pulse-width of the output signal will usually be
one clock cycle of f ps (50 ps at f in = 80 GHz), if neither
a third programmable divider, which dramatically increases
power consumption, nor an additional divide-by-two stage at
the output, which disables the beneficial low division factors
from 12 to 23 and all odd ones, is used. This leads to high
requirements for the following phase-frequency detector in a
PLL and low energy in the output signal at larger division
factors. To overcome this disadvantage we doubled the pulsewidth by a disjunction of the 6-times AND output and the
load signal. The second reason for extending the output signal
generation is the implementation of a global reset function
by the signal R. This feature is beneficial to synchronizing
multiple PLLs, e.g. in a MIMO FMCW radar system.
Mainly divider B is a 2 bit version of divider A and
responsible for controlling the prescaling factor by the modulus
control signal MC (for a block diagram see [3]). The modulus
control logic is realized by multiple conjunctions and is
synchronized to f ps by a flip-flop. The load signal is delivered
by divider A, because only the first cycle of divider B is of
interest.
Because in frequency synthesizers a low residual phase
noise of the divider is essential, we use the flip-flop S1 to
synchronize the output of divider A to the input frequency
f in . Therefore the prescaler and programmable dividers are
no longer in the direct signal path from input to output of the
dual-modulus divider, which results in a reduction of the phase
noise as proved in [5]. To always ensure a synchronization
within one clock cycle of f in we added a delay gate consisting
of two differential amplifiers. Otherwise the synchronization
would take one cycle for f in ≤ 51 GHz and two cycles for
f in ≥ 51 GHz.
IV. E XPERIMENTAL R ESULTS
A photograph of the fabricated chip is shown in Fig. 6(a).
The divider itself occupies an area of 180 µm × 380 µm and
has a power consumption of less than 390 mW, so it is easy
to be integrated in complex MMICs such as single-chip radar
transceivers. For measurements the chip has been mounted on
a Rogers RT/duroid 5880 substrate to apply the division factor
and the power supply as well as to derive the output signal. The
single-ended input signal was fed by probes (GGB Model 40A
182
334
0
-0.2
V (fout) (V)
99.8 Prescaler
(b)
1
in
0
0
0.2
0.4 0.6
t (ns)
0.8
1
3
2
1
0
-1
0
50
0
50
(a)
t (ns)
t (ns)
100
150
100
150
(b)
Fig. 8. (a) Measured output signal with a pulse-width of 8/f in . (b) Output
signal after using the reset function is immediately tout = N/f in .
N = 12
N = 13
N = 14
N = 81
N = 255
Sim.
20
0.8
tout = 13.5ns
-0.5
f = 40 GHz, N = 32
Residual phase noise L (dBc/Hz)
Input power P (dBm)
Fig. 6. (a) Photograph of the realized frequency divider. (b) Distribution of
the power consumption and number of transistors in the different blocks.
0.4 0.6
t (ns)
0.2
-0.2
10
5
0
-5
-10
-15
-20
-25
0
0.2
fin = 6 GHz, N = 81
0
-1
0
0.4
71
(a)
fin = 40 GHz, N = 16
0.2
V (fout ) (V)
0.4
R (V)
169.6 Counter A
4
23
113
V (fout) (V)
59.3 Counter B
Number of transistors
Divider B
Prescaler
100 μm
Divider A
Output
Buffer
Delay
+
Sync.
Power consumption (mW)
20.0 Buffer
29.0 Del.+Sync.
Logic Interface
40
60
80
Input frequency fin (GHz)
Fig. 7. Measured and simulated input sensitivity of the divider for different
division N factors at a temperature of 25◦ C.
Fig. 9.
and 110H), while the complementary input was left open. Input
frequencies from DC to 40 GHz were directly delivered by a
signal source (R&S SMR40) and for frequencies above 43 GHz
a V-band frequency quadrupler (Milltech AMC-15-RFH00)
with an adjustable attenuator (Parzich WR15) was used. As
there was no proper signal source available, the gap from
40 GHz to 43 GHz has only been validated by simulations.
-125
f
= 1 GHz, N = 12
f
= 1 GHz, N = 24
out
-130
out
-135
-140
-145
-150 2
10
3
4
5
10
10
10
Offset frequency from carrier Df (Hz)
10
6
Measured phase noise of the divider.
the extremely high maximum input frequency this divider is
well suited for fractional-N synthesizers in high performance
microwave measurement systems. The reset function of the
divider gives the opportunity to easily synchronize multiple
synthesizers, e.g. in MIMO systems.
ACKNOWLEDGMENT
The authors would like to thank Infineon Technologies AG
for fabricating the chips and the Federal Ministry of Education
and Research (BMBF) for financial support in frame of the
project RAWIS (Funding number: 13N13232).
The sensitivity curve in Fig. 7 shows the required minimum
power of the sinusoidal input signal for an appropriate output
signal, measured with a spectrum analyzer (HP 8565). For
all measured division factors a maximum input frequency of
80 GHz is achieved. The difference of 8 GHz compared to
HICUM simulations is probably caused by wire parasitics. To
reduce the minimum input power at lower frequencies the 1 pF
on chip coupling capacitor can be shorted and a larger capacitor
can be applied externally.
The single-ended output signal is measured with a subsampling oscilloscope (HP 54120B) and shown in Fig 8(a). As
mentioned before, the pulse-width is 8/f in and independent
from the division factor. The reset function is illustrated in
Fig. 8(b). After the falling edge of the reset signal, the
divider immediately starts dividing with the proper division
factor. To characterize the residual phase noise we set up two
identical dividers with their output signals in quadrature. The
residual phase noise, measured with a signal source analyzer
(R&S FSUP26), is shown in Fig. 9. A low noise floor of
−149 dBc/Hz and a flicker noise corner frequency of 13.3 kHz
is reached.
[1]
[2]
[3]
[4]
[5]
V. C ONCLUSION
We presented an 8 bit programmable frequency divider operating at input frequencies up to 80 GHz. A parallel interface
enables fast programming of the divison factor in the entire integer range between 12 and 259. The realized divider consumes
a power of less than 390 mW at a 3.3 V power supply. Because
of the wide division factor range, low residual phase noise and
[6]
[7]
183
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