ATLCE - A3
01/03/2016
Politecnico di Torino - ICT School
Lesson A3: BJT Amplifiers
• Biasing
Analog and Telecommunication
Electronics
– Voltage gain
– Frequency response
A3 – BJT Amplifiers
»
»
»
»
»
– Output dynamic range
• Small signal analysis
• Amplifier design
Biasing
Output dynamic range
Small signal analysis
Voltage gain
Frequency response
– Set operating point and use of small signal model
– Lab experiment 1: small signal measurements
• References:
– D. Del Corso: Transistor circuits, sect. 1.1, 1.2
– Any texbook on Transistor Amplifiers
AY 2015-16
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Amplifiers or ….
• What matters in an amplifier
–
–
–
–
Transistor models
• Small signal
Gain
Bandwidth
Linearity (no distorsion)
Noise (low)
– MOS, MOS-FET, BJT
– Same linear model (gm or hybrid)
• Large signal: same method, different models
– BJT: exponential large signal model (rather simple)
– MOS: lin/log/quad large signal model (complex !)
• There is always some nonlinearity
– Reduce, counteract
– analytic model for BJT
– heuristic models for MOS
» Negative feedback, tuned circuits, …
– Exploit to build
– Similar effects
– Similar countermeasures
» VGA/dynamic compressor
» Mixers
» Oscillators
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Building the BJT amplifier
VAL
• Basic bias circuit
– Ic depends on current gain
– Wide changes in current gain
Rc
R1
VAL
• Final bias circuit
C1
Vi
» Versus current gain
(emitter feedback)
» Versus temperature
(Vb >> Vbe)
VAL
Rc
R1
C1
Vi
R1
Rc
R2
Re2
C1
– Stable Ic
• Collector feedback bias
– R1 to Vc
– Less dependent on current gain
Final BJT amplifier CE circuit
Vi
VAL
R1
– Gain related with bias
Rc
C1
• Emitter feedback bias
R1
Vi
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Rc
• Independent bias / gain
– Different AC / DC paths
– Same approach for CC, CB
C1
– Ic depends on temperature (Vbe)
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VAL
R2
Re1
Vi
Ce
Re2
Re
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BJT reference circuit
• Common
Emitter circuit
Amplifier features and analysis
• AC amplifier: BJT Common Emitter circuit
• Input and output AC coupling: C1, C2
– Bias (DC)
• Emitter feedback
• Add
– Gain control
with feedback
vO
ZL
RE1
– Bandwidth
(BW) control
» HF:
C feedback
and to GND
» LF:
coupling C
– DC: stabilize the bias point
– AC control the gain
(Re1 + Re2)
(Re1 only)
• Analysis or design:
–
–
–
–
–
RE2
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Select or identify the configuration
Set or evaluate the Bias point
AC passband gain (linear model)
Cutoff frequency (frequency response)
Nonlinear model analysis  next section
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Analysis of BJT circuit: step 1
• CE amplifier with bipolar transistor (BJT)
Analysis of BJT circuit: step 2
• CE amplifier with bipolar transistor (BJT)
– Find bias point:
(IC, VCE)
– Find bias point:
(IC, VCE)
– The bias point
must be in the
active region:
– The bias point
must be in the
active region:
IC
VCE > 0,2 V
VCE > 0,2 V
VCE
– Compute
small signal
parameteres for
the bias point:
IC
hie, hfe
VCE
hie, hfe, gm...
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BJT (simplified) models
• Simplified model for
bias point analysis
(to verify operation in
active area)
• Simplified model for
small signal analysis,
CE configuration.
Parameters
hfe iB or gm vBE
hie = VT * hfe/IC
gm = IC/VT
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Bias point analysis
• DC bias point
B
IB
 IB
– Small signal parameters depend on IC and (to a lesser extent)
on VCE  solve bias point first
– IC  IE is fixed by Base-Emitter mesh
– VCE is related with Collector-Emitter mesh
C
E
• Step 1: compute IC
B
gm vBE
C
– Equation on BE mesh
– First approximation: IB = 0 (hFE )
• Step 2: check VCE value;
– Equation on CE mesh
– if > 0,2 V  active area
vBE
E
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BE net
• Ic depends from
these devices
BE mesh
• BE equivalent circuit
(hFE = β)
– Ic depends
only from
Base-Emitter
mesh
– Vcc, R1, R2
are mapped to
a unique mesh,
with equivalent
Thevenin
parameters
VBB
VBB, RB
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CE net
• Vce depends from
devices in the CE
mesh
Design choices
• If hfe is large,
VB
– IB = (VBB – VB)/RB
– VB = VE + VBE ≈ β IB RE + VBE
– Vce depends
from Ic and
devices at
the Collector
node
VBE
VE
• Design variables (for a given Ic)
– VBB,
RB/VB
• Large VBB
Vce
– Good stability vs ΔVBE (mainly due to temperature)
– Reduced output dynamic range (lower VCEmax)
– Vce =
Vcc-IcRc-IeRe
• Small RB
– Good stability vs Δβ (mainly due to parameters spreading)
– High power consumption (RB = R1//R2)
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Example A3-e1: bias, small sig. param.
R1
R2
Re1
Re2
Rc
120 k
82 k
330 
12 k
10 k
Vcc
hfe
12 V
100 (50300)
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Vcc
I1
C1
Q1
Ie
R2
Re1
Ce
Vbb =
Rb =
Ie =
Vce =
C3
Rc
R1
Re2
hie =
Results (example A3-e1)
R1
R2
Re1
Re2
Rc
120 k
82 k
330 
12 k
10 k
Vcc
hfe
12 V
100
Vbb = 12 * 82 / 202 = 4,9 V
Rb = 48,7 k
C3
Rc
R1
Vcc
I1
C1
Q1
Ie
R2
Re1
Ce
Re2
Ie = 4,3 / (12,33 + 48,7/100) = 0,335 mA
Vce = 4,35 V
hie = 7,76 k
gm = 12,88 mA/V
gm =
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Lesson A3: BJT Amplifiers
• Transistor amplifiers
• Parts related with
in-band gain:
– Basic CE circuit
– Biasing
– Output dynamic range
– From slide A3-7:
C3 open,
C1, C2, Ce shorted)
• Small signal analysis
• Reminder:
– Voltage gain
– Frequency response
– In signal analysis
Vcc = 0
• Design of amplifiers
–
–
–
–
BJT circuit: small signal analysis
– R1, R2 are
connected as
parallel resistances
to Vi
Specifications
Set operating point
Use of small signal model
Lab experiment 1: small signal measurements
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Gain analysis equivalent circuit
• Gain with
linear model
• Compute the gain using the linear model
iB
vI
vI
(hfe+1)
iC
hfeiB
hie
R1//R2
Results with linear model
vO
• If hfe >> 1
ZC
ZE
– hie becomes negligible
with respect to ZE (hfe+1)
• If Ze = 0  Max gain
vO = - iC ZC;
iC = iB hfe;
vi = iB hie + iB(1+hfe) ZE
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– Av = - (Zc hfe)/hie = VT hfe/IC
– Depends on device parameters (hfe)
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Example A3-e2 : gain with linear model
hie = 8,96k
hfe = 100
gm = 12,9 mA/V
Rc
Re1
RL
Vi
Vbe
R1//R2
hie = 8,96k
hfe = 100
gm = 12,9 mA/V
gm Vbe
hie
10 k
330 
12 k
Rc
Re1
Results (example A3-e2)
Vo
RL
Rc
Re1
RL
10 k
330 
12 k
Ib
Vi
R1//R2
hfe Ib
hie
Rc
Re1
Av = - (12k//10k)*100 / (8,96k + 330*100) = -13
Av =
- Evaluate gain change for hfe 50500
- Compare with Re = 0
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RL
Total load on the Collector: Rc//RL
Total load on the Collector: Rc//RL
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Vo
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Example A3-e3: Ri and Ro
Frequency response
• Wideband AC amplifier
– Emitter/source feedback
hie = 8,96k
hfe = 100
gm = 12,9 mA/V
Rc
Re1
RL
Ib
Vi
R1//R2
» stabilize DC bias point and in-band AC gain |AV|  ZC/ZE
hfe Ib
hie
12 k
330 
10 k
Rc
• Lower band limit:
Vo
RL
Re1
– interstage series coupling capacitance
– ZE frequency behaviour
– transformer coupling (if any)
• Higher band limit
– parallel capacitors towards ground
Ri = ?
» designed capacitors
» wiring parasitic
» active device parasitic
Ro = ?
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Wideband AC amplifier
Band pass
Actual
(tolerances)
|Vu/Vi|
(dB)
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High Frequency: L and C parasitics
• Output Capacitance (load)
– insert isolation stage (Common Collector/Drain)
• PCB parasitic L and C
– Use SMD devices
– Careful PCB design
Minimum
required
(specs)
1
Low cutoff
frequency
(C1, C2, Ce)
f
(Hz)
100
10
• Active device parasitic (CBC)
– multiplied by Miller effect
– use HF devices with low CBC (GaAs, SiGe, ..)
– proper circuit configuration (Common Base, cascode)
High cutoff
frequency
(C3, Cp1, Cp2)
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Parasitic capacitances
C3
Rc
Cp1
C1
C4
Cp2
– Corrent Icond flowing in CBC:
Q1
– Icond = jωCBC (VB–VC) = jωCBC (VB+AVB) = jωCBC (A+1) VB
(multiplied by Miller effect)
Ie
Vi
R2
Miller effect
• Parasitic Base-Collector capacitance (CBC) is connected
between two nodes with inverting gain –A
Vcc
R1
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Vo
Re1
C2
– Admittance multiplied by (gain +1)
• Actual equivalent capacitance at Base node:
RL
– Cactual = CBC * (A+1)
Re2
• This capacitance limits the high frequency response
Cp1: Base-Collector parasitic (Cbc)
C3: designed to set high cutoff frequency
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• Need for Miller free circuit configurations
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Other circuit configurations: CC
• Common Collector / Common Drain
–
–
–
–
high Zi
low Zo
No Miller effect (Av ≈ 1)
Current gain
• Common Base / Common Gate
– low Zi,
– high Zo
– CBC connected to GND
 no Miller effect
Vcc
Va
Q1
• Good for
– Load separation
– Increasing Zi
– Lowering Zo
Other circuit configurations: CB
Vcc
Q2
• Voltage gain
Vi
– Av ≈ gm Rc
Re
Vo
• Combined with CE
in the cascode stage
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Cascode amplifier
Vcc
Common
Base: Ie  Vo
Voltage gain
Vi  Va
Q1: CE stage,
Low Zc  low V gain
Good current gain
- Low ΔVce
- Low Miller effect
Va  Vu
Q2: CB stage
Good voltage gain
- No Miller effect
Rc
Q2
Va
Vo
Q1
Vi
Cascode amplifier
• Common Base stage (CB)
– CBC parasitic towards ground
– no Miller effect (C multiplier)
– provides voltage gain
• Common Emitter output to low-Z load
RL
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Common
Emitter: Vi  Ic
Current gain
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– small voltage dynamic
– provides current gain
– minimum effect of CBC parasitic capacitance
• Overall result
– higher gain at high frequency
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Lesson A3: BJT Amplifiers
• Transistor amplifiers
– A real design:
» Multiple solutions
» Some specs are implicit
» Devices have poorly defined parameters
• Small signal analysis
• Simulate, build, measure
– Voltage gain
– Frequency response
– Homework: design, simulation
– In the lab: build, measure, debug
• Design of amplifiers
• Compare specs/simulation/measurements
Specifications
Set operating point
Use of small signal model
Lab experiment 1: small signal measurements
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Lab 1 and lab 2
• Design an amplifier from the provided specs
– Basic CE circuit
– Biasing
– Output dynamic range
–
–
–
–
Vo
Vi
• Current gain Ai ≈ 1
• Av ≈ 1
Only basic circuit,
no bias network
Rc
– Linear model

– Nonlinear model 
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lab 1
lab 2
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Amplifier design specs (2016)
• Single-Transistor Amplifier with:
–
–
–
–
–
• Select the circuit: CE with Ze, bias network Vb/Re
Voltage gain |Vu/Vi| = 20 (nominal)
Bandwidth -3 dB from 80 Hz to 200 kHz (minimum)
Output dynamic at least 4 Vpp on 10 kΩ load (or higher)
Supply voltage 12 V (nominal)
2N2222A Transistor (or almost equivalent)
• All features within +/-10%, at ambient temperature
• Choose a no-load dynamic (Vo), or Ve, or Rc
– Stability/power/dynamic tradeoffs
• Compute Rc, or no-load dynamic , or Ve
• Compute Ic
• Design bias network to get Ic:
– R1, R2, Re1+Re2
– Gain and output dynamic at band centre
• Compute Re1 from gain specs
• Compute C1, C2, C3, C4 from frequency gain specs.
• References:
– Text: design procedure: Cap 1, 1.P1
– Lab procedures: Cap 1, 1.L1
– web guides: lab 1
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Design sequence
• Evaluate Pdmax (always, even if not requested!)
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Checks and measurements
• Passive devices (R and C) available only in
normalized values
Theory and practice
|Vu/Vi|
(dB)
– Know what they are (E12, E24, …)
– Only E12 values available in the lab
– From computed to normalized values
Measured values
(with errors)
• Transfer function modified by normalization / tolerances
Design
specification
– Evaluate effects
• Component tolerances expand the Bode plot (a line) to
a somewhat wide band
1
– Specs must lie within the strip
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1k
Design band, taking
into account device
parameters tolerances
• Compare measurements with variations of Bode plot
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10
f
(Hz)
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Lesson A3: final questions
• Which different types of amplifiers can be found in a radio system?
• Draw three circuits which can be used to set the operating point of
a BJT, discussing respective benefits and drawbacks.
• Write an approximate expression for Av of a CE amplifier.
• Which elements limit the bandwidth of amplifiers?
• Which are the best configurations for high bandwidth amplifiers?
• List the specifications for an amplifier (what you must know to
select an amplifier from a catalogue).
• Outline the design procedure for a single transistor amplifier.
• Describe the lab procedures to measure the frequency response of
an amplifier.
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