Experiment #9 - University of Southern California

Jonathan Roderick
Hakan Durmus
Scott Kilpatrick Burgess
Experiment #9
BJT Dynamic Circuits
In the last lab, we learned the point of biasing an analog circuit correctly is so the active devices within the
circuit operate in a desirable fashion (linearly) on signals that enter the circuit. These signals are
perturbations about the bias point (or quiescent point, a.k.a. Q-point); for instance, you might bias your
input port at 2V, and then add a 100 mV peak-to-peak sine wave to this bias voltage. Ideally, you would
like amplifiers to be perfect linear devices, meaning the output signal is some multiple of the input signal,
independent of the input amplitude. Transistors are normally non-linear devices (recall their I-V
characteristics), so the output amplitude does depend upon the input amplitude. However, by suitably
restricting the amplitude of the input swing (using a “small signal”) and correctly biasing the circuit (Q
point), the resultant output will show very little curvature, meaning that the non-linear circuit acts
approximately linear for small-signal deviations about the bias point.
In this lab, dynamic circuits using BJTs will be introduced. Once a BJT is biased in such a way that it
operates in a linear region, then the “small-signal” BJT model may be used for analysis and design of
circuits that contain the transistor. This model forms the basis for understanding the dynamic performance
of several commonly encountered circuits.
Small-Signal Model for the Bipolar Transistor
The small-signal model for an NPN bipolar transistor is shown in figure 9.1. For the purposes of this lab,
the models and theory presented will focus on the NPN Bipolar Junction Transistor. The following models
also apply for the PNP transistor with the slight modification of: reversing the direction of all controlled
current sources and branch currents, and a reversal in polarity of all port and branch voltages.
β I=gmve
Figure 9.1 Small-signal model for the bipolar transistor.
Note: The small signal model is just a tool that is used to help circuit designers analyze circuits utilizing
BJTs. This tool is only valid if the transistor is operating in its linear range. Therefore it should be
understood that when using the small signal model, that significant effort has been made to ensure that the
signal being processed in the amplifier is not too large, thus validating the “small signal” model accuracy.
A large enough signal may cause the transistor to leave its linear operation if its signal change has a
magnitude large enough to offset the set Q (biasing) point, thus causing signal distortion.
The key element in the small signal model is the controlled current source, which can be shown as
depending on the internal base current i (or the internal base-emitter voltage ve). The quantity g m is defined
g m= ∂i c ∂ve
signifying how responsive the collector current is to changes in the driving voltage ve. The small signal
model accounts the various internal resistances associated with each terminal. Resistor re is the small
resistance associated with the highly doped emitter. Resistor rb is a distributed, non-linear resistance, and
thus hard to characterize with a single value, but it corresponds to the resistance between the base contact
and that region of the base material lying underneath the emitter. Likewise, resistor rc is hard to characterize
with a single value, but represents the net resistance between the collector contact and the bottom portion of
the base material. Resistor rπ, known as the emitter-base junction diffusion resistance, is not a physical
resistance (it is a mathematical model conceived from a Taylor series expansion of the base-emitter current,
IBE , about the Q-point) like the preceding three, but rather a dynamic quantity defined as
rπ = ∂i b ∂v e
It represents how resistant the input base current is to changes in the internal base-emitter voltage (i.e., the
voltage not including the voltage drop across rb , represented as “ve” in the small signal model). The
controlled source indicates how much the collector current changes for a change in base current (or
equivalently, base-emitter voltage). Like rπ , resistor ro is a dynamic resistance and it is know as the forward
Early resistance. It represents the influence of changes in collector-emitter voltage on collector current,
and thus is calculated by
ro = ∂i c ∂v ce
For high Early voltages, A E , this resistance is negligible, and thus the collector voltage has a negligible
impact on the current flowing out of the collector contact. The internal resistance does have profound
effects on overall circuit performance. Large base, collector, and emitter resistances reduce circuit gain,
diminish gain-bandwidth product, and increase electrical noise. However, rb , re, and rc are inversely
proportional to the emitter-base junction injection area and a price is paid for increasing the area to lower
resistances. Increasing the area of the device results in larger parasitic capacitances, so increasing the size
of the transistor to reduce internal resistance reduces the circuit response speed. Power consumption is also
a trade-off. All internal resistance, particularly rb , decrease monotonically with increasing the base and
collector bias currents, IB and IC respectively. In the world of wireless and mobile electronics, we want the
batteries in our cell phone to last longer, so large power consumption in wireless electronics is avoided.
Welcome to the wonderful world of circuit design, where hindering constraints are inversely proportional
to each other. Your job as a circuit designer is to find a happy median that allows you to meet all the
specifications for your design.
The small signal model also accounts for internal parasitic capacitances found with in the BJT. Cµ
represents the depletion capacitance of the base-collector junction. Cπ is composed of two parts: 1) a
diffusion capacitance given by
= τ F c = τ F gm
Cπ = ∂v
and 2) a depletion capacitance, which is usually negligible compared to the diffusion capacitance when the
base-emitter junction is forward-biased. To develop numerical values for the symbols in the small-signals
model, the defining derivatives must be evaluated symbolically, then evaluated about the Q-point. With the
bias quantities specified, numerical values may be assigned to each small-signal parameter.
The small signal model does give a circuit designer a good feel on how parasitic capacitance affects the
performance of the circuit. A matured circuit designer can by inspection see the limitations of any
topology. For instance, if bandwidth is being considered a good circuit designer would avoid exposing any
large parasitic capacitance to any large impedances (Remember the time constant, in terms of frequency, is
inversely proportional to RC).
Canonic Cells of Linear BJT Technology.
The BJT Transistor has four basic topologies that are building blocks for more complicated circuit
architecture. A single BJT transistor may be connected in a diode, common emitter, common collector, or
common base configuration. A quick and simple way to determine the difference between the common
base, collector, or emitter is: First, determine what terminals where the input and output are connected.
Then, the particular canonic cell receives its name from the terminal that is leftover. For example, if you are
looking at the ac BJT configuration in figure 9.2, you will notice that the input is at the base, while the
output is located at the collector. Hence, the leftover terminal is the emitter and this canonic cell is deemed
a “common emitter” amplifier.
Figure 9.2 An AC schematic diagram of a common
emitter amplifier.
Diode -Connected Transistor.
The simplest canonic cell for the BJT is the diode-connected transistor. The collector is tied to the base of
the transistor, so it exhibits I-V behavior of a conventional PN junction diode. Figure 9.3 depicts a
transistor connected this way and its small-signal equivalent circuit. This model assumes the transistor is
biased in the linear region and leaves out the Q-point currents.
The diode-connected transistor reduces the number of terminals of a typical BJT to two (the base and
collector are now the same terminal). This two terminal device may be modeled as a two terminal resistor
seen in figure 9.3. Using the low-frequency small-signal model of BJT (neglecting all capacitance), the
equivalent resistance of the diode-connected can be found to equal Rd .
Rd = re +
( ro + rc ) || (rb + rπ )
ro β
ro + rc + rb + rπ
If ro >>rc +rb +rπ, then equation 9.5 reduces to
Rd ≈ re +
rb + rπ
1+ β
Figure 9.3(a) Diode-Connected BJT and (b) its small-signal low frequency equivalent model.
Common Emitter Canonic Cell.
The common emitter amplifier was shown in figure 9.2. Replacing the schematic symbol of a BJT in
figure 9.2 with the small signal model, one can calculate the gain, input impedance and the output
impedance. Figure 9.4 shows a common emitter amplifier utilizing the small signal model. Assuming that
rc is negligible and ignoring the early effect (ro = ∞) the gain, input resistance (Rin ) and output resistance
(Rout ) may be calculated.
r out
r ee
Figure 9.4 A low frequency common emitter canonic cell using the small signal model.
rin = rb + rπ + ( β + 1)( re + rx )
where r x is the resistance seen by emitter.
rout ≈ ∞
Av =
− βrl
Vs rs + rb + rπ + ( β + 1)( re + rx )
assuming β is large, then the gain reduces to
Av =
Vo − rl
The common emitter canonic cell is used to achieve an inverting gain that is independent of the transistor β.
Rin depends on what the value of rx, but since it is multiplied by β it is assumed not to be too small. Rout is
very large. With a Rin that can be made fairly large and a Rout is very large, the common emitter is not a
very ideal voltage amplifier. Additional transistors can be used to enhance performance, so that the
common-emitter canonic can be used as a good voltage amplifier.
Common Collector Canonic Cell.
A common collector canonic cell is shown in figure 9.5. Notice, the input nor the output of the canonic cell
is connected to the collector of the transistor.
Figure 9.5 An ac schematic of a common-collector (a.k.a. an
emitter follower) BJT canonic cell.
Using the Small signal model it can be shown that the gain, input resistance and the output resistance are
the following
AV =
( β + 1) re
Vs rs + rb + rπ + ( β + 1)( re + rx )
In this example, choosing a small Ree the gain will reduce to
AV =
rin = rb + rπ + ( β + 1)( re + rx )
rout = re +
rb + rπ + ry
( β + 1)
Since the gain can be designed nearly equal one, rin can be made fairly large, while rout is small (due to it
being inversely proportional to β) the common collector canonic cell can be designed to be a decent voltage
buffer. Since the common collector is usually used as a voltage buffer, it is sometimes referred to as a
“emitter follower” due to the emitter following (or matching) the voltage that is connected to the base.
Common Base Canonic Cell.
The common base canonic cell is shown in figure 9.9. The input is a current source at the emitter, while
the output is taken at the collector. Hence, this is a common base configuration of a BJT.
Figure 9.9 An AC common base BJT canonic cell.
Using the small-signal model it can be shown that the current gain (A i ), rin , and rout are the following.
Ai =
=α ≈1
I s β +1
rout = ∞
rin = re +
rb + rπ + ry
( β + 1)
The common base has a current gain of about one, a large output resistance and a small input resistance.
Therefore, it is commonly used as a current buffer.
Common Emitter Amplifier Example
In the previous lab, the common-emitter amplifier was biased, but no mention was made of why it is called
an amplifier. To answer this, we analyze the circuit in the previous lab, with a few modifications. First, we
need to feed our input signal into the base, without the DC bias of the signal source and the commonemitter amplifier interfering with each other. This is accomplished by adding an AC coupling capacitor
(Cin ) to the input port, large enough so that it will act like an AC short at the frequencies at which we
operate, thus eliminating any transfer of DC offsets. Second, the amplifier needs to drive a resistive load
which we don’t want to upset our bias point, so we append another AC coupling capacitor (Cout ) to the
output port. Third, we replace the transistor symbol used in the previous lab with the small-signal model,
leading to the following circuit:
Rb1 ||R b2
re+ Ree
Figure 9.7 An AC common-emitter amplifier with resistive load for AC analysis (from experiment #5
figure 5.5)
Assuming that we are at low-enough frequencies that the parasitic capacitances of the BJT don’t affect our
results, but a high enough frequency where the coupling capacitors are acting like shorts, and further
neglecting the Early, source, and internal emitter resistances, analysis of our model leads to:
Av =
β ( Rload || Rc )
rb + rπ + (β + 1)Re
With large beta, this reduces to
Av =
Rload || Rc
a rather simple expression independent of transistor parameters. As long as Rload || Rc > Re , the
transfer function has a magnitude greater than 1, explaining why the common-emitter is called an amplifier.
For the values derived in the previous lab, this requires that Rload be at least 375Ω for gain. Notice: the
source resistance in this example was ignored, which is only valid in an ideal world. This assumption
causes the voltage division effects, which would be normally cause by the biasing transistors Rb1 and Rb2 ,
to be ignored. However, if one was to build this circuit, any source resistance would cause these two
biasing resistors to diminish the gain and thus would need to be accounted for during design.
The dynamic use of the BJT transistor was explored in this experiment. There were four fundamental
configurations covered that are known as the BJT canonical cells. Each canonic cell has different unique
beneficial characteristics as well as limitations. Experiment #10 will deal with combining canonic cells to
overcome the limitations inherent of a single cell topology. It is very crucial that the canonic cells are well
understood as they will give a circuit designer the ability to breakdown and evaluate complicated circuit
topologies virtually by inspection.
Reference reading
John Choma, Jr. EE348 lecture notes. University of Southern California. Spring 2001.
David Johns & Ken Martin. Analog integrated Circuit Design. John Wiley & Sons, Inc., New
York, 1997.
Paul R. Gray & Robert G. Meyer. Analysis and Design of Analog Integrated Circuits. John Wiley
& Sons, Inc., New York, 1993.
Pre-lab Exercises
Given the definitions of the small-signal parameters for the bipolar transistor, express rπ, g m, and ro
in terms of bias parameters (e.g., collector current, Vce, etc.). For a 1mA current and Vce of 3.2V as
well as an Early voltage of 200 and a Beta of 100, what are the values of rπ, g m and ro ?
Using figure 9.2, design an amplifier with a small signal gain magnitude of 7. Your job is to
choose the correct resistor values that determine the biasing point and correct gain magnitude.
Assume you are using a 10kHz sin wave input with a magnitude of 50mV (100mV peak-to-peak).
Be sure that your signal doesn’t drive the transistor out of the linear region. Your design must use
a ground to 5V power supply and not draw more than 5mA through any given branch. Verify your
design using Spice. Is it possible to meet the required specifications? If, not why not?
Neglecting any biasing issues , if the resistors you use in the previous problem have a tolerance of
±5%, what is the maximum error the gain can experience due exclusively to the tolerances of the
Derive the expressions given for the voltage gain, input resistance and output resistance for the
common collector circuit in figure 9.5.
Derive the expressions given for the current gain, input resistance and output resistance for the
common base circuit in figure 9.9.
Derive the expressions for the gain, input resistance, and output resistance for the low-frequency
common-emitter amplifier in figure 9.7.
Building upon the common-emitter biasing example pictured in figure 5.5 from experiment #5,
what is the maximum gain that can be achieved if the collector current is fixed at 1mA and the
base voltage is fixed at 1V? Assume Vs is a 10kHz sin wave with a magnitude 50mV (100mV
peak-to-peak) Can a gain of 50 be achieved? Why or why not? While ensuring that the transistor
never leaves linear operation, what is the maximum gain that can be obtained? What RC value
gives you the maximum gain? Use SPICE to verify your design and your suspensions about the
maximum amount of gain that you can obtain. Use the .op command to verify the bias currents
and voltages for your circuit, and an .ac or .tran analysis to observe the voltage gain.
Place a large (e.g., 0.1 uF) capacitor across resistor Ree in the previous problem. By inspection can
you theorize what happens to the gain and why? Do a SPICE simulation to confirm your response.
Express the output current of the Wilson current, figure 8.7, source in terms of the reference
current. Do not neglect base currents in your analysis, and assume each transistor has the same β.
Your final answer should be in terms of the reference current and β. (Hint: your final answer
(1 − error )
should look like out
, where the error depends inversely on β .) Do a small
signal analysis to determine a symbolic expression for the output resistance of the Wilson current
source. Assume every transistor has identical small-signal parameters. Assume you desire you an
output current of 1 mA, and your supply, Vcc, is 5V. What is the approximate size of the required
reference resistor, R?
Lab Exercise
Build the design you can up for question #2 in the prelab. Measure the gain and the current
through each branch and compare it to your spice results. Are your results within 5% of
specifications given in the prelab? Perform any necessary changes or tweaking of resistor values
to get within 5% of specs. Next, Change the input signal level by ±9-dB. Does the circuit still
behave linearly? Why or why not?
Build the design which gives you the maximum achievable gain that you determined is possible
from the common emitter amplifier in problem #7 of the prelab. Verify it operation by comparing
the magnitude of the input signal to the magnitude of the output signal.
Keep the circuit from the previous problem, but replace RC with a potentiometer. Vary the pot
until you reach the maximum achievable gain while still maintaining a base-collector reverse bias
to ensure linearity. Measure the value of the potentiometer that gives you the maximum possible
gain. Does this value agree with what you derived in question #7 of the prelab? Why or why not?
Place a large (e.g., 0.1 uF) capacitor across resistor Ree of the last problem. Using a function
generator, sweet the frequency from 1kHz to 35kHz taking a measurement of the magnitude every
1kHz. What does adding the capacitor do to the gain? Does this agree with your prediction for
question #8 in the prelab?
Design the emitter follower in figure 9.5. Choose the DC voltage of the source, Vs , and the
resistor values that bias the transistor with 1mA. Given: Vcc=5V, and Vs is a 10kHz sin wave
input with a magnitude of 50mV (100mV peak-to-peak). Measure the gain of your circuit? Now
select resistor values that maximize the output swing (ac signal magnitude). Did this affect the
gain of your circuit? If so, by how much?
Add a 300Ω and the capacitor CD to the emitter follower, as seen in figure 9.8. The capacitor, CD,
should be very large. What is the purpose of this capacitor? Estimate the gain and then measure it.
Does driving this small resistance affect the ac gain of you circuit? Why is this beneficial? Could
you drive the same small resistance with a common-emitter? Why or why not?
Figure 9.8
Design the common emitter circuit with the emitter degeneration resistor Ree. Using what you
derived in the pre-lab, what effect does Ree have on the performance of the circuit? Using a source
dc offset of 1V, use what you learned in experiment #5 to bias this circuit so that it has an emitter
current of 1mA. Choose a value for Rl , so that the output has maximum swing capability: For
linearity purposes, don’t let the collector-emitter voltage (VCE ) drop below 0.7V (It should be large
than VSAT=0.2V, but to be safe, keep it above VBE . Measure the gain of this circuit. Can you
obtain a gain of 50 given the same supply voltage and current limitations?
Add a 300Ω and the capacitor CD to the common emitter, as seen in figure 9.9. Estimate the gain
using what you derived in the pre-lab. Measure the gain. Is the gain the same as measure in part
(a)? Based on your results, what is a basic limitation of the common emitter amplifier?
Build the common-emitter amplifier of Figure 9.2. Determine an appropriate input signal level so
that the output signal is large enough to measure, but small enough so that the transistor acts
linearly. Determine the low-frequency gain at 10 kHz. Does it match reasonably well with your
hand results? Change Place a 0.1µF capacitor across Ree and re-measure the AC gain (you may
need to adjust your input signal amplitude once more to ensure linear behavior).