INTRODUCTION
Rarely does one get through a day in Canada without encountering an
electronic device. Since the discovery of the transistor in 1947 by Bardeen,
Brattain and Shockley electronics have transformed our world
http://www.pbs.org/transistor/. It especially important for scientists to
understand electronics as they play a larger role in our lives.
The field of electronics is rapidly evolving and it easy to feel it is impossible
to keep up with the “state of the art”. In fact, the study of electronics can
be split into four parts:
1. Basic physical laws of electricity
2. Circuit analysis techniques
3. Vocabulary to describe electronics
4. Application of electronics
Clearly the underlying physical laws are not changing – so studying them is
worthwhile for understanding the current and future state of the art. The
theory of circuit analysis was developed decades ago and the main new
development is the use of computers to solve more complex circuits. This
area is changing slowly and is required for quantitatively understanding the
state of the art. The vocabulary is always evolving to encompass the new
devices being developed everyday. Twenty years ago terms such as
“Photonics” and “data bus” existed only in science fiction novels. Fortunately
each new generation of terminology builds upon the previous one (e.g. gate ⇒
optical gate) so knowledge of the current terminology will be useful for many
years. Applications of electronics evolve rapidly and many of the details we
will learn in this class will be obsolete in a few years, however, the reasons
for studying the current state of the art are that it is currently useful, it
will help us understand electronics better and it is fun.
ELECTRIC FORCE AND FIELD
General Information:
• The basic unit of Charge is the Coulomb (C).
• The smallest magnitude of charge that can occur outside of a nucleon is
the charge on a single electron = 1.602 × 10 -19 C. (Millikan Oil Drop Exp.)
• Charge can be either positive or negative. Charges of the same sign repel
and charges of opposite sign attract.
r
• A charge, q, generates an electric field, E .
ELECTRIC FORCE - COULOMB’S LAW:
q1
NB: Equal and opposite force on EACH charge!
r
F12
r
r12
r
F21
q2
The direction of the electric force, F12, on q1 due to q2, is given by the signs
r
of the charges and the direction of the position vector r12 , which connects
them. The magnitude is given by Coulomb’s law:
r
kq1q 2
F12 =
2
(r12 )
where the constant k = 8.988 × 109 Nm2C-2 is a related to the permittivity of
free space, ε0, by the relationship : k =(4πε0)-1. This means that Coulomb’s
law as written above, applies only to charges in the vacuum. If the charges
are not in a vacuum then Coulomb’s law takes the form:
kq1q 2
F12 =
2
K (r12 )
where K is the (unitless) dielectric constant for the medium in which the
charges are immersed. For example:
For water
K= 80.4
For air
K=1.007 (WE WILL USE 1.0)
For wood
K=5.0
Example 1
In an evacuated experimental chamber, an α particle (positive charge, Qα = 2
× (1.602 × 10 –19 C) = 3.204 × 10 –19 C) approaches to within 10 nanometers (1
nm = 10-9 m) of an electron (negative charge, Qe = -1.602 × 10 –19 C). What is
the force the particles exert on one another? Is it an attractive or
repulsive force?
Solution The particles attract one another with a force of magnitude,
kQα Q e
F=
2
K (r )
(9.0 × 10 )(3.204 × 10 )(1.602 × 10 )
=
1.0(10 × 10 )
9
−19
−19
−9 2
= 4.619 × 10 −12 N
In vacuum so we use dielectric constant K = 1
ELECTRIC FIELDS:
The reason why a pair of charges experience equal and opposite forces at a
r
distance is that each charge individually creates an electric field, E around
itself. The interaction of a second charge with this electric field gives rise
to the electric force it experiences. For example, a point negative charge
creates straight field lines…
for +ve charge would point outward
The magnitude of the electric field around a point charge, q, is given by:
r
kq
E= 2
Kr
•
•
•
.
k and K have the same values as in Coulomb’s Law.
r is the distance from the charge to the position in question.
units are Newtons/Coulomb, N/C.
E.G. Electric field for a pair of oppositely charged point charges:
A few points about these sketches
r
• E is tangent to the field line at each point
r
• the number of lines per unit cross sectional area (⊥ to E ) is
r
proportional to E the magnitude of the electric field, which is
•
sometimes denoted E, but should not be confused with the energy.
The lines never intersect
For a charge distribution the field is calculated by writing Coulomb’s law for
each small element of charge and summing over the distribution. For a
simple charge distribution such as a pair of parallel plates with equal and
opposing charges separated by a distance, d:
top plate
+ +
+
+
+
+
E = 0
+
+
+
d
E = CONSTANT
- -
-
-
-
-
-
-
-
lower plate
Assuming the plate separation is small compared to their area the resulting
electric field takes a simple form: constant everywhere inside plates and
zero outside.. The magnitude of the field between 2 parallel plates with
voltage, V is:
E = V/d
So, Volts/meter is another unit for electric field. Actual field lines between
plates look like:
Distortion near plate edges caused by finite area of plates…
The direction of the field is that which a small positive test charge would
experience if placed at the same position (try this on diagrams above).
If a charge q1 is brought into an electric field E, then the resulting force on
that charge is,
r
r
F = qE .
The electric field at and the force on a charge point in the same direction
for positive charges and in opposite directions for negative charges.
SUPERPOSITION OF THE ELECTRIC FIELD
If electric fields from different sources are present then the total electric
field is the VECTORIAL SUM of the fields due to each source.
Example 2
A set of plates 10.0 cm apart has 200 V across them. What is the electric
field inside the plates? What is the force on an electron within them?
+
200 V
10.0 cm
0V
electron
Solution
Electric field is constant, V =Ed, for parallel plates: E = V/d = 200/(0.10) =
2000 N/C (or Volts/meter).
The field is straight down. Force on the electron, we use F = qE. Therefore,
F = (1.602 × 10-19) × 2000 = 3.204 × 10-16 N straight down.
ELECTRIC POTENTIAL
Consider a pair of charged plates separated by a distance d with a small
positive charge placed right next to the negatively charged plate.
Final position of q
+ +
+
+
+
+
+
+
+
d
- -
-
-
-
-
-
-
-
Initial position of q
The charge will experience a force with magnitude equal to qE pulling it
straight towards the negative plate (assuming the gravitiational force is
negligible). To lift it at constant velocity an upwards force with magnitude
qE must be applied. The work done against the constant electric force =
force × distance Therefore the work, W, required to move the charge all the
way to the positive plate at the top is,
W = F × d = qEd
This is the electric potential energy acquired by the charge, which clearly
depends on the magnitude of the charge between the plates. Therefore we
define the electric potential, V, which like the electric field does not
depend on the "test charge" placed in between the plates. That is,
V = W/q
The equation above can be considered a definition of the electric potential
and can be rearranged to yield an equation we have seen earlier,
Energy = W = qV.
Also one can infer, since W = qV = qEd that,
V = E d.
for constant fields
For parallel plates it is commonly assumed that the negative plate is a t
potential of zero and therefore the positive plate is at +V. For reference
the electric field near the surface of the Earth is typically E ≈ 100-200 V/m
in fair weather. During thunderstorms E ≈ 104 V/m!
Electric Force is Conservative. The work done moving from A to B depends
only on the position of the end points (not the path between the endpoints).
Corollary: the work done over any closed path is zero.
Potential around a Point Charge
kq
V=
Kr
where K is the dielectric constant. A point of reference must be chosen
where V = 0. For a point charge a distance of infinity (from the point
charge) is assigned a potential V = 0.
To calculate the potential at a point due to a combination of point charges,
simply add the potentials at that point form each charge algebraically. To
calculate the energy or work required to bring a charge, q2, from infinity to
a distance r from another charge, q1, just remember that the work required
to bring q2 to a potential V is,
W = q2V
And the potential around q1 is,
kq1
V=
Kr
Therefore
kq1q 2
W=
Kr
For example if we have several charges arranged as shown below and we
want the potential at point, P:
q1
for several charges:
q2
P
VP = kΣi (qi/ri)
Potential energy of a charge q'
placed at point P:
q3
U = q'V = q'k[Σi (qi/ri)]
Example 3
A classroom demonstration is set up as follows:
A
30.0 cm
20˚
Ball 1
r
B
C
Ball 2
Two spheres of equal mass are each given a
charge; q1 = 5.0 µC and q2 = 3.4 µC. The
30.0 cm long string holding ball 1 is
observed to make a 20 degree angle with
respect to the vertical. What angle will the
string which holds ball 2 make with respect
to the vertical? What is the magnitude of
the electric force pushing the balls apart?
What is the electric field at B, which is
10.0 cm directly below point C? What is
the electric potential at B?
Solution
The balls have equal mass and the electric force on each is equal and
opposite. Therefore, they both hang at the same angle, i.e., 20o with respect
to the vertical. We are given q1 and q2 in the problem. We need the
distance between the balls, r, to determine the force. Using trigonometry:
r = 2(30.0 cm)(sin(20˚)) = 20.5 cm = 0.205 m.
So the force is,
F=
kq1q 2
2
K (r )
(9.0 × 10 )(5.0 × 10 )(3.4 × 10 )
=
−6
9
−6
1.007(0.205)
2
= 3.62 N
To calculate the electric field at B we need the distance, R, shown in the
diagram (the same for both spheres):
r
R
B
10.0 cm
R2 = (r/2)2 + (10.0)2 = (20.5/2)2 + 100.0
⇒ R = 14.3 cm = 0.143 m
To get the electric field at point B the following diagram is useful:
0.205 m
q1
q2
y
0.100 m
θ
B
0.143 m
x
φ
E2
E1
EB
We need the value of θ:
tan(θ) = 0.100/(0.205/2)
θ = 44.3o .
The total electric field at B, EB, is the vectorial sum of the electric field at
B due to q1, E1, and the electric field at B due to q2, E2.
r
r
r
E B = E1 + E 2
The magnitudes of E1 and E2 are given by E = kQ/r2,
(
r
kq1 9.0 ×109 5.0 ×10 −6
E1 = 2 =
2
Kr
1.007(0.143)
= 2.19 ×10 N/C
5
)
.
Calculating the magnitude of E2, similarly, we find that E2 = 1.49 × 10 5 N/C.
The final answer is the vectorial sum of the two electric fields. This means
we add their x components and y components together separately. So…
EBx = E1x + E2x = (2.19cos(44.3) – 1.49cos(44.3)) × 10 5 = 0.504 × 10
5
EBy = E1y + E2y = -2.19sin(44.3) - 1.49sin(44.3) × 10 5 = -2.57 × 10
N/C
5
N/C.
Therefore the magnitude of the electric field at B is,
r
r 2 r 2 1/ 2

E B =  E Bx + E By 


= 2.62 × 105 N/C
at some angle φ below the horizontal. Using trigonometry:
and therefore,
sin(φ) = 2.57/2.62
φ = 78.8o below horizontal.
The potential at B, VB, is equal to the algebraic sum of the potential at B due
to q1, V1, and the potential at B due to q2, V2, that is,
where,
V B = V1 + V2
kq1
V1 =
Kr
and
kq2
V2 =
Kr
Therefore, since k, K and r are the same for both V1 and V2,
VB =
kq 1 kq 2 k
(q 1+ q2 )
+
=
Kr
Kr Kr
9.0 × 109
=
5.0 × 10 −6 + 3.4 × 10 −6
1.007(0.143)
(
= 0.524 × 106 V
)
.
WORK, POTENTIAL ENERGY AND
ELECTRIC POTENTIAL
1
q
r
E
2
Move charge in electric field - Work is done by electric force, qE. W = -∆U
[or -(U2-U1)]. The existence of this "electric potential" indicates that the
electric force is CONSERVATIVE.
Since,
U = qV → ∆U = q∆V
Therefore,
W = -∆U = -q∆V
EXAMPLE 4
An α particle ( charge = +2e) is moving away from a fixed charge (+Q). At
point, A, which is a distance d from the fixed charge, the potential is 900 V.
By how much does the kinetic energy of the α particle increase as it moves
from A to B - which is 2d away from the fixed charge?
2d
α particle, q = 2e moving away from Q; ∆K = ?
B
d
A
VB = ? = kQ/2d
+Q
VA = 900 V = kQ/d
We see that VA/2 = 450 V = VB
Energy Conservation:
UA + KA = UB + KB
UA - UB = KB - KA
qVA - qVB = ∆K
(2e)(900 - 450) = 900 eV
What if an electron moves from a to b? ∆K = ? ∆PE = ?
DC CURRENT
In direct current (DC) circuits the current is constant, (e.g. a battery) outlets provide AC. Only three quantities define a simple DC circuit,
Electric Potential (V), Resistance (R), and Current (I).
Electric Potential designated with symbol, VAB, is defined in terms of the
work (Energy) required to bring charge, q, from a point A to a point B, WAB.
WAB = qVAB
VAB = WAB/q
Therefore the Electric Potential is in units of Joules/Coulomb which is
defined as a Volt (V). Electric potential is often called the voltage.
Resistance is a property of the material through which the electric
potential is driving the current. Consider a voltage, VAB, across a material
with Resistance, R, as shown in the diagram below:
R
A
B
I
VAB
If R is a constant independent of VAB for a given temperature (ie. The
resistor is made of an Ohmic material) , then the above quantities may be
related using Ohm's law:
VAB = IR .
Ohm's Law
Therefore, the Resistance is given in Volt/Amperes. This unit is known as
the Ohm(Ω).
Current is the flow of charge, Q through a cross sectional area in a time, t.
I = IAV = ∆Q/∆t = dQ/dt
The SI unit for current is the Ampere (A) = (1 Coulomb of positive charge
flowing through a given area per second). In most material the electrons
carry the charge. For e.g. in a copper wire:
Copper atomic cores Collisions of e- → heat → resistance
Cross sectional Area
Direction of Conventional Current
Caused by net "drift velocity" of free electrons
Drift velocity is average of the horizontal components of the electron
velocities. Redrawing the diagram without the ion cores and only the x
component of the average electron velocities (ie. The "drift " velocity):
Cross sectional Area: A
1
v∆t
2
There are N particles in the volume A(v∆t) that will cross through surface 2
within time ∆t and register as "instantaneous" current. Each particle has a
charge q, making the total charge through surface 2 = Nq. Defining, n =
N/(Av∆t) as a number density of charges, each with charge q, per unit
volume, we get that the charge through area 2 is:
IAV = ∆Q/∆t = Nq/∆t = nAv∆tq/∆t = nqAv
For several charge carriers (eg, holes, ions electrons) the total current is a
sum over each type:
I = AΣiniqivi
Whether the circuit is treated as negative current moving in the direction
of the electrons or positive current moving in the opposite direction it
makes no difference mathematically. Therefore, since it is simpler, we will
henceforth consider only the positive flow of charge in problem solving.
EXAMPLE 5 - Calculation of Drift Speed
A copper wire with r = 0.50 × 10-3 m contains n= 8.0 × 1028 conduction e-/m3
(known from the Hall effect) while carrying a current of 2.0 A. What is the
drift velocity of the individual electrons?
I = nqvA
⇒
v = I/(nqπr2) = 2.0 × 10-4 m/s
VERY SLOW!
Conductors and Insulators - CALCULATING Resistance:
Resistance depends on the dimensions and material through which the
current is flowing. For example, consider a conductor with cross-sectional
area, A and length L;
A
L
Then, the resistance
is given by,
R = ρL/A ,
where ρ is the resistivity of the material (found in scientific data tables).
For metals ρ ≈ 10-8 → 10-6 Ωm; for insulators ρ ≈ 10+13 → 10+17 Ωm.
Resistivity depends upon the collisions of the current carriers with the ionic
cores making up the bulk of the material. The ionic core oscillations impede
the flow of electrons and increase with temperature. Therefore resistance
increases with the temperature. Some typical plots are shown below:
Ohmic
semiconductor
superconductor
insulator
ρ
ρ
ρ
conductor
T
T
T
Ohmic materials are defined as those that obey Ohm’s Law. That is (at
constant temperature) resistance is independent of voltage applied. Note
that insulators and conductors are both Ohmic – but with different slope.
ELECTRIC POWER – Joule heating
Consider an element in a circuit as shown below:
I
I
E
a
b
put an element in here through which current flows
•
In time ∆t, charge I∆t ( = ∆Q) passes through element.
•
Work done by electric field…
W
= -q∆V
(= -∆U = -(Ua – Ub))
= - (∆Q)(Vb – Va)
= ∆Q(Va – Vb)
= ∆QVab
= I∆tVab
Therefore, power = W/∆t = I∆tVab/∆t = IVab,
or,
P = IV
units: (J/C)(C/s) = J/s = Watts (W)
Cases:
1)
2)
Ohmic resistors: V = IR give P = I2R; I = V/R gives P = V2/R.
(Joule heating due to resistors)
EMF = P = ε I
SIMPLE CIRCUITS
DC CIRCUITS:
R
A simple DC circuit
I
V or EMF
Kirchoff's rules
1. Net voltage around a closed loop is zero.
2. The current going into a point is equal to
the current leaving it.
With these two rules, the currents (or other unknowns) of many simple
circuits can be calculated.
Generally useful observations:
points connected by a PERFECT conductor are at the same electric potential.
Any arrangement can be reduced to a network arranged in series and
parallel. For resistances connected in series that is,
SERIES NETWORK:
I
R1
R2
R3
A
B
V1
V2
V3
VAB
Since current coming = the current going in for each resistor, they all have
the same current: the total current, I.
The equivalent resistance, Req, for this network is:
VAB = IReq.
Each resistor has a different electric potential across it. Clearly the total
potential difference in going from A to B is:
VAB = V1+V2+V3.
Also, for each resistor;
IR1 = V1
IR2 = V2
So,
IR3 = V3
VAB = I(R1+R2+R3)
∴ Req = R1 + R2 + R3 .
Parallel Network:
R1
I1
R2
I
I
A
I2
R3
I3
V
The equivalent Resistance, Req, such that V= IReq for the three resistor
network shown above is found by applying Kirchoff's second rule at point, A,
I = I1 + I 2 + I 3
Current in
Current out
Also, since all three resistors are in parallel they have the same voltage
across them, V, therefore;
I1 = V/R1
I2 = V/R2
And we can write,
I3 = V/R3
V/Req = V/R1 + V/R2 + V/R3
Dividing by V on both sides, we find the equivalent resistance,
1
1
1
1
=
+
+ .
R R R
Req
1
2
3
This is the equivalent resistance for the network shown above. This means
if the network were part of a complex circuit, the analysis of the circuit
could be simplified by replacing the three resistors R1, R2 and R3 with a
single resistor with the equivalent resistance Req.
EXAMPLE 1: Series/Parallel Resistor Network
Calculate Req for the following combination of Resistors:
R1 = 500 Ω
R2 = 250 Ω
R3 = 1000 Ω
R4 = 600 Ω
The network can be simplified by noting that its resistance is equal to:
1/Req1 = 1/R1 + 1/R2
1/Req2 = 1/R3 + 1/R4
With a little algebra: Req1 = R1R2/(R1 + R2) and Req2 = R3R4/(R3 + R4) by using
the rule for parallel resistors. Since Req1 and Req2 are in series, we can use
the series rule to find the total Resistance of the network, Req. That is Req =
Req1 + Req2 . Therefore,
Req = R1R2/(R1 + R2) + R3R4/(R3 + R4)
Substitution of the given values for the Resistances gives:
Req = 542 Ω.
EXAMPLE 2: Series, Parallel or What? Calculate Req for the
following network. All the conductors are 1.0 Ω.
The wires are assumed to be perfect conductors. Therefore, points
connected by wires can be re-arranged to suggest a solution as long as the
same paths are possible in the new network as the old.
This is very similar to example for, except Req1 has three conductors rather
two. Using the same process to solve for Req, we find that Req = 0.83 Ω.
Symbol List of circuit elements
Battery
Connection
Multi-cell
Battery
No-connection
Resistor
Capacitor
Variable
Resistor
Variable
Capacitor
Variable
Resistor (3 – pole)
Inductor
(Air core)
Inductor
(Iron Core)
DC voltage
source
AC voltage
source
DC current
source
AC current
source
+
-
3V
1Ω
20 Ω
Example 3:
e
f
I2
c
I2
loop 1
5V
I3 = I1 - I2
I1
loop 2
1Ω
I2
I1
a
(a)
(b)
5Ω
I1 - I2
What is the current, I1, through the middle branch?
What is Vab = (Va - Vb)?
d
I1 - I2
b
GENERAL STRATEGY – MESH EQUATIONS: Use Kirchoff's rules and
Ohm's Law to solve for the two unknown loop currents, I1 and I2 then
determine Vab and I3. Take note that although there are three branches
(each with a different current) this method reduces the number of
unknowns to two by implicitly using Kirchoff’s point rule to get rid of I3 (see
below and text pg. 36-40).
(1)
Use Kirchoff's Point Rule (#2) to designate currents. For e.g. at
point c:
I3 = I1 - I2 ⇒ I1 = I2 + I3.
(2)
Use Kirchoff's Loop Rule (#1) on as many loops as required to
generate sufficient equations. Two loops are required from above.
(i)
For loop 1:
going clockwise starting at c
-IR looping in direction of I
-3V - I2 (1 Ω) - I2 (20 Ω) - I1 (1 Ω) + 5V = 0
“-” because going from + to - terminal
⇒ - I1 - 21 I2 = -2 Amps
⇒ I1 + 21 I2 = 2 A
(ii)
[1]
For loop 2: going clockwise starting at c
- 5 V + I1(1 Ω) + (I1 - I2)(5 Ω)
6 I1 - 5 I2 = 5 A
•
•
•
(3)
= 0
[2]
Loop rule works for ANY closed loop.
For e.g., big loop aefba.
Handy if there were more unknowns or as check.
Solve resulting system of equations:
Multiplying equation [1] by -6:
-6 I1 - 126 I2 = - 12 A
[3]
Add [2] and [3]…
-131 I2 = - 7 A
⇒ I2 = -7/-131 = 0.0534 A
Using this value for I2 in equation [1], we find:
I1 = 2 A- 21 I2 = 2 A -21 (7/131) A = 0.878 A.
Therefore the answer to question (a) is:
I1 = 0.878 A
For question (b), Vab = (I1 -I2) (5 Ω) = 4.12 V. This is also equal to Vcd and Vef
because these voltages are all parallel.
Example 4:
R1 = 3 Ω
What is the
current through
the 12 V battery?
R2 = 2 Ω
6V
R4 =
6Ω
12 V
R3 =
7 Ω What current flows
thru the 3Ω
resistor?
R5 = 5 Ω
Simplify diagram:
And draw
Mesh currents
8.2 Ω
6V
We want
I2
6Ω
I1
I2
12 V
5Ω
Apply Kirchoff’s loop rule
Starting in lower right corner of upper loop and moving around it in a counter
clockwise direction.
+8.2 (I1) – 6 + 6 (I1 –I2) = 0
I2 = (14.2/6)I1 - 1
Starting in lower right of lower loop and moving around it in a counter
clockwise direction.
6 (I2 – I1) + 6 + 12 + 5 (I2) = 0
Sub in I2 from above
11I2 + 18 = 6I1
11((14.2/6)I1 - 1) + 18 = 6I1
26.0I1 +7 = 6I1
⇒
I1 = -7/20 = - 0.35 A
Sub I1 into expression for I2
I2 = (14.2/6)(-0.35) – 1 = - 1.83 A
The current thru the 12 V battery = I2 = -1.83 A (Downwards in original
picture). To get the current in the 3Ω resistor we need to re – expand the
circuit…
R1 = 3 Ω
0.35 A
1.48 A
R2 = 2 Ω
6V
12 V
1.83 A
Element
R1
R2
R3
R4
R5
Resistance (Ω)
3
2
7
6
5
R3 =
7Ω
R4 =
6Ω
R5 = 5 Ω
Current (A)
V/R = -0.4/3 = -0.13
V/R = -0.4/2 = -0.2
I1 = -0.35
I1 – I2 = 1.48
I2 = -1.83
Voltage (V)
-12+9.15+2.45 = -0.4
-12+9.15+2.45 = -0.4
IR = - 2.45
IR =
8.88
IR = - 9.15
Using Microcap 7.0 the simplified circuit after Dynamic DC analysis is:
Example 5 – Above problems were warm-up
10 V
1Ω
3Ω
5V
I2
4Ω
2Ω
I3
8Ω
5Ω
7Ω
I1
6Ω
•
Choose I1, I2 and I3. There are 3 independent currents in this problem –
all others depend on those three – check using point rule.
•
To solve 3 unknowns we need 3 equations. Each labeled current loop gives
us one equation.
•
Note that some resistors have more than one current passing thru them.
E.g. 7Ω resistor has BOTH I1 going up and I3 going down.
1)
Loop 1: start in lower left and go clockwise (can start anywhere and go
any direction)
-18I1 + 5I2 + 7I3 = 0
-I1(7) + I3(7) – I1(5) + I2(5) – I1(6) = 0 ⇒
2)
Loop 2: start in lower left and go clockwise
-I2(2) + I3(2) – 5 – I2(3) – I2(4) – I2(5) + I1(5) = 0
⇒
5I1 - 14I2 + 2I3 = 5
3)
Loop 3: start in lower left and go clockwise
-I3(8) – 10 – (I3)1 + 5 - I3(2) + I2(2) - I3(7) + I1(7) = 0
⇒
7I1 - 2I2 - 16I3 = 5
Use Cramer’s Rule – See Chapter 52 of text
This system of 3 equations in 3 unknowns can be solved using linear algebra
For large (3 or more equations) systems of equations, it is much easier to use
Cramer’s rule than regular algebra. For 3 linear equations in 3 unknowns:
7I1 - 2I2 - 18I3 = 5
5I1 - 14I2 + 2I3 = 5
-18I1 + 5I2 + 7I3 = 0
1)
Evaluate determinant for the coefficients of the unknown currents.
“Expanding the determinant”
7
D =
2
5
− 14
− 18 5
− 18
−2
7
= 7
− 14 − 2
5
7
−5
2 − 18
5
7
− 18
2
− 18
− 14
2
⇒ D = 7 (-98 - 10) – 5(14 – (-90)) -18 (4 – 252)
⇒ D = 7 (-108) – 5(104) -18 (-248)
⇒ D = 3188
2)
Replace the coefficients for I1 in the determinant (1st column) with
the numbers on the right hand side of the equations. That is, replace
(7, 5 -18) with (5, 5, 0). For I2 do the same thing to the 2nd column
5
D1
=
2
5 − 14
0
5
− 18
−2
7
= 5
− 14 − 2
5
D1 = 5 (-108) - 5(104) + 0 = -1060
7
−5
2 − 18
5
7
−0
2
− 18
− 14
2
3)
I1 is then given by D1/D = -1060/3188 = - 0.33 A.
The NEGATIVE means I1 goes in opposite direction to that shown in
diagram
4)
A similar process for I2 yields:
7
D2
=
5 − 18
5 5
− 18 0
−2
7
= − 18
5 − 18
5
2
−0
7 − 18
5
2
+7
7 5
5 5
= -1730
I2 is then given by D1/D = -1730/3188 = - 0.54 A
5)
use I1 and I2 to solve for I3
Use third equation…
-18I1 + 5I2 + 7I3 = 0
-18(-0.33) + 5(-0.54) + 7I3 = 0
I3 = -0.47 A
Check answer using outer loop. Start in lower left and go clockwise:
R3
R1
-8I3– 10 – I3 – 3I2 – 4I2 - 6I1 should be = 0
-9I3– 7I2 - 6I1 – 10
= -8(-0.47) – 7(-0.54) – 6(- 0.33) – 10
R8
= -0.01
R7
R4
R6
Very near 0 ⇒ answer is within round off errors. With these mesh currents
can determine the current and voltage through each element of the circuit…
Element R (Ω) Current (A)
Voltage (V)
R1
1
I3 = - 0.47
1(-0.47) = -0.47
R2
2
I2-I3 = -0.54 – (-0.47) = - 0.07 2(-0.07) = -0.14
R3
3
I2 = - 0.54
3(-0.54) = -1.62
R4
4
I2 = - 0.54
4(-0.54) = -2.16
R5
5
I1-I2 = - 0.33 – (-0.54) = 0.21
5(0.21) = 1.05
R6
6
I1 = - 0.33
6(-0.33) = -1.98
R7
7
I1-I3 = - 0.33 – (- 0.47) = 0.14
7(0.14) = 0.98
R8
8
I3 = - 0.47
8(-0.47) = -3.76
Microcap or other software is useful here
Step 1: Construct circuit…
Step 2 – Analyze
VR1 =-6.261–(-5.794) = -0.467
VR2 = -0.944 - 0.793 = -0.151
VR3 = -5.794 – (-4.166) = -1.63
VR4 = -4.166 – (-1.995) = -2.17
VR5 = -0.944-(-1.995) = 1.05
VR6 = -1.995
VR7 = 0.944
VR8 = -3.739
Compare to table of calculated values…
CAPACITORS
Many electric devices are basically resistors (e.g. stoves, light bulbs,
toasters, etc.) or power sources (batteries, power supplies, solar cells…).
Another basic component is the capacitor, which is a device that stores
charge. It has many uses e.g.:
•
•
Frequency tuning on a radio is a variable capacitor
Photographic flash: slow charge - quick release.
A capacitor is typically constructed of two conductors separated by an
insulator. The circuit symbol for a capacitor is:
or
•
•
Normally equal and opposite charges Q and -Q on each conductor
Q depends on area (and shape) of conductors, distance and
insulator between them, and voltage.
A capacitor differs from a battery (which also stores charge) in that its
energy is stored purely in the field between the plates. There are no
electrochemical reactions in a capacitor to restore this field as it depletes.
Capacitance:
C = Q/V
where V ≡ potential difference
between conductors
NB the use of italics to avoid confusion with, Coluombs (C as opposed to C )
Units: Coulomb/Volt ≡ farad (F) (this is a huge unit most capacitors are in
the picofarad range)
Parallel Plate Capacitor
Va
Vb
+
+
+
+
+
+
+
r
E
-
-
-
-
d
-
-
-
Assuming that the area of the plates, A >> d2, where d is the distance
between the plates, we can ignore distortions in the constant electric field
and,
E = σ/ε0 = Vab/d.
By definition σ = Q/A, i.e. charge per unit area. Therefore,
E = Q/(Aε0) = Vab/d.
⇒ Q/Vab = ε0A/d
⇒ C = ε0A/d
(for two plates separated by vacuum)
Energy of a charged Capacitor:
(Work required to charge it)
(Can be shown using calculus)
U = ½CV2 = Q2/(2C) = ½QV
CAPACITORS NETWORKS
Va
a
C1
+
-
Vab = V
b
constant voltage in conductor
Q1
C2
+
-
Q2
Vb
We can treat above capacitor network as a single EQUIVALENT capacitance
(As for resistors):
a
From above:
CEQ
+
-
Vab = V
QEQ = Q1 + Q2
B
Q1 = C 1 V
Q2 = C2V
V across both capacitors
total charge provided by source is Q = Q1 + Q2. Therefore,
CEQ = Q/V = (Q1 + Q2)/V = Q1/V + Q2/V = C1 + C2 .
Or for many capacitors in parallel: C = ΣiCi . Equivalent capacitance in parallel
is determined like equivalent resistance in series.
a
Vab = V
C1
C2
+ Q1
- Q1
+ Q2
- Q2
b
NB: Net charge of this piece
of circuit must = 0.
Therefore, Q1 = Q2
CAPACITORS HAVE
SAME CHARGE = Q.
Voltages, however are now different:
V1 = Q/C1
V2 = Q/C2
(by Kirchoff's loop rule)
V = V1 + V2 = Q/C1 +Q/C2
Treating the above network as a single EQUIVALENT capacitance, we find:
a
From above:
Vab = V
+
-
CEQ = ?
QEQ = Q
QEQ/CEQ = V
Q/CEQ = V
b
Therefore we have two expressions for V = Q/CEQ = Q/C1 + Q/C2. Canceling
the value of Q on both sides we find….
1/CEQ = 1/C1 + 1/C2
i.e.) in series: (CEQ)-1 = Σi(1/Ci)
Equivalent capacitance in series is like equivalent resistance in parallel.
Example 1
C2
a
Vab = 15 V
b
C1 = 1.0 µF
C2 = 2.0 µF
C3 = 3.0 µF
C1
C3
Determine the equivalent capacitance between terminals a and b and
determine the voltage and charge on each capacitor.
a) Equivalent Capacitance: C2 and C3 are in series: Therefore they may be
replaced by a single capacitor with capacitance, C23:
Vab = 15 V
+
C1
C23
+
(1/C23) = 1/C1 + 1/C2
C23 = (1/2.0 µF + 1/3.0 µF)-1 = 1.2 µF
C1 and C23 are in parallel: Therefore their capacitances are added
together to get the total equivalent capacitance:
CEQ = C1 + C23 = 1.0 + 1.2 µF = 2.2 µF
b) Voltages and charges on each capacitor:
For C1: V1 = Vab = 15 V ⇒ Q1 = C1V1 = (1.0 × 10-6 F)(15 V) = 1.5 × 10-5 C.
For C2 and C3: V2 + V3 = Vab (Kirchoff's loop rule) Therefore using Q = CV
for each capacitor:
Vab = Q2/C2 + Q3/C3
But, as we saw in section on series capacitors, each capacitor in series has
the same charge, Q, induced on it (because of electric neutrality of each
piece of conductor). Therefore:
Vab = Q/C2 + Q/C3 = Q(1/C2 + 1/C3) = Q/C23
Q = C23Vab = (1.2 µF)(15 V) = 1.8 × 10-5 C
for C2 and C3
The voltages are found by using Q = CiVi on each capacitor:
V2 = Q/C2 = (1.8 × 10-5 C)/(2.0 × 10-6 F) = 9.0 V
-5
-6
V3 = Q/C3 = (1.8 × 10 C)/(3.0 × 10 F) = 6.0 V
V2 + V3 = 15.0 V (checks)
Now consider the same capacitor except with a jumper wire across C2 as
shown below:
c
a
C2
C1 = 1.0 µF
C2 = 2.0 µF
Vab = 15 V
C1
C3 = 3.0 µF
(as before)
B
C3
d
The jumper wire causes V2 = Vcd = 0. This takes C2 out of the circuit. The
remaining two capacitors are in parallel:
Vab = 15 V
C1
C3
CEQ = C1 + C3 = 4.0 µF
V1 = V3 = 15 V
Therefore Q1 = C1V1 = 1.5 × 10-5 C and Q3 = C3V3 = 4.5 × 10-5 C
DIELECTRICS IN CAPACITORS
Advantages:
• Materials with dielectric constant higher than air reduce electric field in
the capacitor (at same voltage) to stop arcing (dielectric breakdown). The
capacitance is increased for capacitors of the same size.
• Allows the plates a capacitor operating at a given voltage to be placed
closer together (smaller capacitors of same capacitance as "empty" ones).
e.g.:
dielectric strength of air ≈ 8 × 105 V/m
Plastics and Ceramics ≈ 1 × 107 V/m
Q
V0
r
Maximum E supported
Q
r
E0
d0
ceramic, TiO
empty
V
d
-Q
r
E
wax paper
plastic,
-Q
Same plate area, A, and distance d for each capacitor. Assume that both
capacitors have same induced charge, Q. Microscopically:
r
E 0 re-aligns dipoles
r
r
Ed + E0
r
= E
in dielectric
Since E < E0
⇒
⇒
V/d < V0/d
V < V0
electric field is
reduced
Both capacitors have a charge Q = C0V0 = CV upon them. Therefore, if V< V0,
then C > C0. We define the dielectric constant as K ≡ C/C0 > 1. Earlier we
showed that C = ε0A/d for an empty capacitor. Therefore,
C = εA/d = KC0 = Kε0A/d ⇒ ε = Kε0
where ε is the permittivity of the dielectric.
THE RC CIRCUIT
Let's consider a circuit containing both a resistor and a capacitor.
V
( int. r << R)
V
i
open switch
C
close switch at t = 0
R
-q
q
i
i
b
c
a
•
Use lower case i, v, q for time dependent quantities
•
Switch open: no current flows, no charge accumulates on the capacitor
•
When switch closed: battery does work to charge the capacitor to final
charge +Qf and -Qf on the capacitor plates. While charging, current i
flows.
•
Eventually, the capacitor will be fully charged to Qf and the current i will
drop to zero.
•
What is q(t) and i(t)?
We know that:
i = dq/dt
Also:
vac = iR
[1]
and
vcb = q/C
From Kirchoff's loop rule V = vac + vcb
⇒
V = iR + q/C
[2]
Re-arranging [2] we get: CV - q = iRC and substituting for i using [1] we get:
(dq/dt)RC = CV - q
dq/(CV - q) = dt /RC
Integrating over the interval from t = 0 to t = t (during which charge q
grows from zero to q on both sides of the equation;
∫
q
0
t dt
dq
=
CV − q ∫0 RC
− ln(CV − q ) 0
q
t
=
RC
t
0
− ln(CV − q ) − (− ln(CV )) =
t
RC
solving for q, w get;
t
 CV − q 
− ln
=
 CV  RC
 CV − q 
− t/RC

=e
 CV 
q = CV - CVe − t/RC = CV (1 − e − t/RC )
[3]
At t = 0, the capacitor is uncharged, q = 0, i = I0 ≡ initial current. Therefore
vcb(0) = 0 and,
I0R = V
[4]
At t = ∞, i → 0, q → Qf. Therefore, vac → 0 and
vbc = Qf/C = V
[5]
Using expression [5] in [3] we get the final expression for q(t):
q = Q f (1 − e − t/RC ) .
Checking the limits of the above expression we see that:
1. At t=0 q(0) = Qf (1-1) = 0
2. As t → ∞, q → Qf(1 - 0)= Qf
As expected
Plot q vs. t
q
Qf
Qf/e
RC
t
At t = RC , q = Qf(1 - 1/e) ≈ Qf(1 - 0.368)
RC = time constant (τ) = relaxation time.
For expression describing the current simply use:
i = dq/dt = d/dt[Qf(1 -e-t/RC)]
Therefore;
Q f − t/RC
d
− t/RC
i = (Q f − Q f e
)=0+
e
dt
RC
using [5] and [3] we get
V − t/RC
i= e
= I 0 e − t/RC
R
Plot i vs. t
i
I0
I0/e
t
RC
At t = 0, i = I0
As expected
As t → ∞, i→ 0
At t = RC
i = I0/e
Include a plot of I vs. v to show capacitor is linear
Include a plot of v vs. t to show type of output Microcap will generate
ADVANCED CIRCUIT ANALYSIS
Real vs. ideal sources
We often treat batteries simply as constant voltage differences with no
resistance. Real batteries have (non constant) internal resistance and have a
voltage difference that varies over time:
a
From Kirchoff’s loop rule
ε
b
ε - Ir – IRL = 0
a
t
t
e
r
y
RL
r
b
I
(1)
∴ ε I – I 2r – I 2R L = 0
ε I = I 2r + I 2R L
emf
power
useful work = PL
In actual fact any “real” electronic component also has a small amount of
inductance and capacitance. A real battery might also be depicted as…
However in most real cases the
Inductance and capacitance
Are small enough to neglect
Sometimes even the resistance is
Neglected though it is always present
For a “real” battery with only a voltage an internal resistance….
The voltage at the terminals, or terminal voltage (i.e. Vcd = Vc- Vd)
Vcd =
ε - Ir < ε
As batteries age, ε decreases slightly and r increases a lot
(electrochemical by-products gunk up electrodes)
Therefore by equation (1) above I decreases [from (1) I = ε/(r + RL)].
This means the power in load RL = I2RL goes down as well. The battery is said
to have “less juice”. What happens to batteries in the cold?
Power Matching:
a
From Above
ε
b
ε = I(r + RL) ⇒ I = ε /(r + RL)
PL = I2RL = [ε /(r + RL)]2RL
a
t
t
e
Maximum useful power occurs when:
r
r
dPL/dRL =

RL
d 2
 =0
ε  2
2 
dRL  RL + 2RL r + r 
y
b
I
⇒
ε2
d
dRL


RL
 2

 R + 2R r + r 2  = 0
L
 L

 1 (R 2 + 2R r + r 2 ) - R (2R + 2r ) 
L
L
L
L
 =0
Using Quotient rule we find that : ε 2 
2
2 2


(RL + 2RL r + r )



ε 2
(
r 2 - RL2
 R 2 + 2R r + r 2
L
 L
)
2

 = 0 ⇒ r2 – RL2 = 0 ⇒ RL = r for maximum power output


At the maximum (RL = r), the power output is:
MAX PL = I2RL = [ε /(r + RL)]2RL
= [ε /(2r)]2r = ε2/4r
Therefore for an EMF of 100 V with an internal resistance of 50 Ω, we
would expect the maximum power output to occur at RL = 50 Ω and we would
expect the peak power to be: (100)2/4(50) = 10000/200 = 50 Watts. Below
is a graph of PL vs. RL using the above quantities where it is clear that the
maximum does occur at RL = 50 Ω and that the maximum power output is 50
W.
P
(W)
RL (Ω)
Advanced Circuit Analysis Techniques
Superposition – The current in any branch of a linear circuit is equal to the
sum of the currents produced separately by each source remainder of the
circuit, with all other sources set to zero.
Reciprocity – The partial current in branch x of a linear, dc circuit produced
by a voltage source in branch y is equal to that which would be produced in
branch y by the same source if it were placed in branch x.
Linear Circuit – Circuits involving only elements with voltage-current
relationships that are linear (e.g. resistors, capacitors, inductors).
Thevenin’s Theorem:
any complex network of linear circuit
elements (sources, resistors and impedances) having two terminals can be
replaced by a single equivalent voltage source connected in series with a
single resistor (impedance).
Procedure for using Thevenin’s Theorem:
1. If the circuit to be replaced by the Thevenin equivalent circuit already
has two open terminals, label these terminals VTh. If there is a circuit
element at the point where the circuit is to be studied, remove the
element from the circuit, replace it by an open circuit and label the
terminals VTh.
2. Compute VTh, the voltage at the open terminals
3. Replace all voltage sources in the circuit with short circuits and all
current sources with open circuits. (Conceptually - NOT in the Lab!)
4. Compute RTh, the resistance of the circuit looking back into the output
terminals after making these changes.
5. The network can then be replaced by the Thevenin equivalent circuit:
RTh
VTh
Example 1 – Using Thevenin’s Theorem - or save for Ass. #4?
Given the circuit:
Vin
R1
R2
C1
Where R1 = 6000 (6k) Ω, R2 = 3000 (3k) Ω and C1 = 4.0 × 10-8 F. What is the time
constant for this circuit?
This circuit can be simplified using Thevenin’s Method.
First replace the entire circuit except the capacitor with the Thevenin equivalent circuit so
that a simple RC circuit results for which the time constant can easily be evaluated:
RTh
VTh
C1
This is done in two steps
Step 1 –Compute the Thevenin Equivalent Voltage VTh of the original the circuit
without the capacitor:
R1
i = Vin/(R1+R2)
VTh = iR2 = VinR2/(R1+R2)
R2
Vin
VTh
VTh = Vin(3k)/(6k+3k) = Vin/3
Step 2 –Compute the Thevenin Equivalent Resistance RTh of the original the circuit
without the capacitor by replacing the voltage source in the above circuit with a closed
circuit:
R1
1/RTh = 1/R1 1/R2
1/RTh = 1/6000 1/3000
R2
RTh = 2000 Ω
VTh
The original circuit
R1
Vin
R2
C1
can now be replaced with its Thevenin Equivalent circuit:
RTh
VTh
C1
Where VTh = Vin/3 and RTh = 2000 Ω
The resulting time constant is (RTh)(C1) = (2×103)(4.0×10-8) = 8.0×10-5 s
Using Microcap we find:
When Vin (V1 in diagram above) is set to be a square wave with the following
properties:
V0 = 0
Von = 18V
Time delay to leading edge = 100 µs
Time delay to trailing edge = 600 µs
Total time per pulse =
1 ms = 1000 µs
Then transient analysis of the circuit yields the following v(t) curves.
Note that the time constant in the above curves can be shown to match the
calculated value and that v(2) corresponds to the voltage across the
capacitor.
Norton’s Theorem: any complex network of linear circuit elements (sources,
resistors and impedances) can be replaced by a single equivalent current
source connected in parallel with a single resistor (impedance).
Procedure for using Norton’s Theorem
1. If the circuit has two terminals, connect these by a short circuit. If the
current through some element is to be studied, replace it by a short
circuit.
2. Calculate INor, the current through this short circuit
3. Replace all the voltage sources by short circuits and all the current
sources by open circuits
4. Compute the shunt resistance RNor looking back into the circuit after
making all of these changes. NB RNor = RTh.
5. Finally replace the network by the Norton Equivalent current source.
Norton’s method is not used as often as Thevenin’s method – for an
example see text pages 47 and 50.
If time permits: Do a questions 6-1 to 6-5 in text.
MAGNETIC FIELDS
Magnetic fields,
r
B , are produced by moving charges.
I
Electron orbiting
in atom
nucleus
r
B
r
B
Classical trajectory
Of e- as suggested
r
By e- orbital L .
The angular momentum of electrons in the atom creates magnetic fields.
When aligned, the momenta create permanent magnets:.
North
South
Bar magnet
S
N
However, any current will create a magnetic field. (Magnetic forces in
circuits are therefore a concern). For example:
Inductor with constant current flowing thru it – The strength of the field is
proportional to the magnitude of the current B ≅ µ0NI/x.
I
x
S
N
turns
Notes re: Magnetic fields
•
r
B points from North to South (OUTSIDE OF THE MAGNET)
•
Every magnetic N has a S
•
Unlike poles attract, like poles repel.
The N pole of a magnet points to the Earth's magnetic North. Therefore
r
the geographic North pole is actually a South Magnetic pole. B of Earth ∼
10-4 T: For comparison a strong bar magnet ∼ 0.2 T
•
r
The field lines, tangent to B at each point in space, point in direction of
force on a magnetic North pole
•
r
Number of lines/(unit Area) ∝ B ∝ strength of field
•
r
SI unit for B is Tesla (T)= NA-1m-1. Another unit is Gauss (G): 1 T = 104 G.
ELECTROMAGNETIC INDUCTION
It has been observed
that a magnet moving
towards a loop of wire
induces a current in the
wire.
r
v
•
•
•
•
•
•
Move magnet downwards and current flows
around loop
Move magnet upwards and current flows in
opposite direction
When magnet is stationary with respect to the loop - no current flows.
THERE IS AN INDUCED CURRENT DUE TO AN INDUCED EMF.
The induced EMF, ε, depends on how B changes with time in the loop.
Depends on number of B field lines that intersect the cross sectional
area of the loop. (Defined as MAGNETIC FLUX, ΦB)
FARADAY's LAW OF INDUCTION
The induced emf in a closed loop equals the negative of the time rate of
change of magnetic flux through the loop.
ε = - dΦB/dt .
The direction of the induced current is given by
LENZ's LAW:
Direction of magnetic induction opposes the cause.
B increasing
B
I
B induced
ε
The actual amount of I that flows (and therefore the magnitude of induced
B) depends on the resistance in the wire, that is:
I = ε /R
INDUCTORS
A changing magnetic field will induce a voltage in many electronic
components. However, significant inductance is usually produced by coils of
wire specifically designed for the purpose. Such coils are called inductors.
As discussed above, the induced voltage is proportional to the change in
magnetic flux. For a loop of constant area, the change in flux is proportional
to the change in the magnetic field. The magnetic field is proportional to
the current. Therefore (for fixed geometry) the induced voltage, v(t) is
proportional to the change in current (di(t)/dt). The proportionality
constant linking the two is called, L, the inductance:
v(t) = L di(t)/dt
[1]
This can be re-arranged to give i(t) in terms of v(t):
1
i(t) = ∫ v (t )dt
L
[2]
The unit for inductance is called the Henry (H). Let’s compare inductance
to capacitance:
Q= CV
dQ/dt = I = V dC/dt + C dV/dt
assume constant geometry ⇒ C is constant
⇒ dC/dt = 0
i(t) = C dv(t)/dt
Compare to expression [1]. Integrating the above expressions yields:
1
v(t) = ∫ i(t )dt
C
Note the symmetry between inductance and capacitance. Also notice that
under steady state (DC) conditions, the voltage and current do not change –
hence inductance and capacitance are not studied in courses restricted to
DC circuits.
The RL Circuit
Let's consider a circuit containing both a resistor and a inductor.
V
i
V
A
open switch
B
close switch at t = 0
L
R
i
i
•
Switch open: no current flows, no induced voltage on the inductor
•
Switch closed: Current i flows but induced counter voltage stops current
from instantly reaching steady state value, I = V/R.
•
Eventually, current reaches I, and the counter voltage will drop to zero.
•
What is v(t) and i(t)?
Applying Kirchoff's loop rule: V – iR – Ldi/dt = 0
⇒
V – iR = Ldi/dt
⇒
(V – iR)dt = L di
⇒
dt = L di/(V-iR)
Integrating over the interval from t’ = 0 to t’ = t (during which time current
i’ grows from 0 to i on both sides of the equation;
t
i
dt ′
di′
=
∫0 L ∫0 V − i′R
i
t
1
t′
− ln(V − i′R ) =
R
L0
0
ln(V − iR ) − (ln(V )) = −
tR
L
solving for i, w get;
tR
 V − iR 
ln
 =−
L
 V 
 iR 
− tR/L
1 −  = e
V

i=
V
(1 − e − tR/L )
R
We see that at t = 0, the current i = 0. As t → ∞, i → V/R, which is the
steady state value of the circuit without the inductor. Therefore inductors
behave as short circuits in Dc circuits (and capacitors behave as breaks in
the circuit). To get the voltage across the inductor we note that v =
L(di/dt)…
v=L
v=
di
d V

= L  (1 − e − tR/L ) 
dt
dt  R

VL d
VL d − tR/L
1 − e − tR/L = −
e
= −Ve − tR/L
R dt
R dt
(
)
(
)
Therefore at = 0 the voltage across the inductor is –V and it decays
exponentially to zero as time passes.
Plot i vs. t
i
if = V/R
if/e
t
R/L
At t = R/L , i = V/R(1 - 1/e) ≈ V/R(1 - 0.368)
R/L = time constant (τ) = relaxation time – just like with capacitor.
v Plot v vs. t
t
-V/e
R/L
-V
Plot of v vs. i
V – v – iR = 0 from Kirchoff’s loop rule, where v = L(di/dt)
v(i)
v = -V + iR
As with capacitors
the plot is linear indicating
that inductors are linear
circuit elements.
v = 0 (t = ∞)
i
v = -V (t = 0)
How do these plots
if switch is thrown to B
after a long time?
Complex numbers
It is possible to display AC voltages and other quantities in a concise
notation involving complex numbers….
Consider first the real numbers: 0, -3, π, (18.4)½, etc. are all examples of
REAL NUMBERS shown on the line below…
0
-3
π
(18.4)½
Real numbers include all rational numbers, all algebraic irrationals and all
transcendental real numbers (such as e, and π).
When solving an equation such as x2 + 1 = 0, numbers such as − 1 appear as
solutions, the equation has no REAL solution. However, a great deal of REAL
mathematics could not be proven true without the assumption that a solution
exists. In order to deal with this, the concept of imaginary numbers has
been developed by mathematicians.
−1 = j
− 2 = 2 −1 = 2 j
− 4 = 4 − 1 = 2j
and so on …
Just as for the REALS, we can plot the imaginary numbers on a line.
0
πj (18.4)½j
-3j
Once we allow that imaginary numbers exist a wide doorway has opened. We
have discussed pure imaginary and pure real numbers. What about “mixed”
numbers? All solutions to a quadratic equation ax2 + bx + c = 0 are given by :
x=
− b ± b 2 − 4ac
2a
We may have been told that if b2 – 4ac < 0 there was no solution but now we
see that a “mixed” solution with both a real part and an imaginary part is the
actual result. Such numbers are called COMPLEX NUMBERS.
From our imaginary and real axes we see that the only number that is both
real number and an imaginary number is zero. That is, 0 is the one point in
the intersection between the set of REALS and the set of imaginary
numbers. This suggests that the REAL and IMAGINARY axes can be drawn
perpendicular to one another with an intersection at zero. This gives us a
graphical interpretation of the complex numbers.
2j
j
-4
-3
-2
-1
1
2
3
jy
4
5
x
-j
-2j
The standard or “Cartesian” form for such numbers is z = x + jy. Complex
numbers are clearly two dimensional vectors…
Polar Representation of Complex Numbers: From the diagram above we can
see that the complex numbers may also be represented in polar form:
x = rcosθ
r = z = x2 + y2
y = rsinθ
2j
z = x + jy = r(cosθ + jsinθ)
(modulus or magnitude)
r
j
θ = tan-1(y/x)
(argument or phase)
θ
-4
-3
-2
-1
1
-j
2
3
4
5
Using Euler’s Theorem:
e j(θ ) = cos(θ) + jsin(θ)
It is possible to write complex numbers in exponential form:
rejθ = r(cos(θ) + jsin(θ))
Operations on complex numbers
Complex conjugate: If z = x + jy, then its complex conjugate, z* is:
z* = x – jy
in cartesian form
-jθ
= re
in exponential form
= r(cosθ - jsinθ) in trigonometric form
The magnitude z = (zz*)½ = (x2 + y2)½
Plot zz*.
z
2j
j
-4
-3
-2
-1
1
2
3
4
5
z + z*
-j
-2j
z*
Addition:
z1 + z2 = (x1 + x2) + j (y1 + y2)
Complex numbers add (and subtract) like vectors. Easiest in Cartesian form.
Multiplication:
z1z2 = (x1 + jy1)(x2 + jy2) = (x1x2 – y1y2) + j(x1y2 + y1x2)
Easiest in exponential form: z1z2 = (r1ejθ)( r2ejϕ) = r1r2 ej(θ+ϕ)
Division
z1/z2 = (r1ejθ)/( r2ejϕ) = (r1/r2)ej(θ-ϕ)
V-I in an AC circuit for linear elements
What is voltage when an AC current, i = Imsin (ωt), is driven through a
Resistor:
Capacitor:
v(t) = iR = RImsin(ωt)
1
i(t )dt
C∫
1
= ∫ Imsin(ωt )dt
C
v(t) =
= - (Im/ωC)cos(ωt)
or an Inductor:
v(t) = L di(t)/dt
= L d(Imsin(ωt))/dt
= ωLImcos(ωt)
What is current when an AC voltage, v = Vmsin (ωt), is driven through a
Resistor:
Capacitor:
i(t) = v/R = (Vm/R)sin(ωt)
i(t) = C(dv/dt)
= C[d(Vmsin(ωt))/dt]
= CωVmcos(ωt)
NB sin(θ + π/2) = cos(θ)
+90o out of phase with i(t)
or an Inductor:
1
i(t) = ∫ v(t )dt
L
1
= ∫ Vmsin(ωt )dt
L
Vm
= - ω L cos(ωt )
-90o out of phase with i(t)
See Table 8-1 and 8-2 if you do not want to use calculus every time…
Equations for sinusoidal AC voltage (See pg.56 of text)
V = Vmsin(ωt)
Periodic functions
V = Vmsin(ωt ± φ)
Phase angle
φ = “phase angle” is proportional to shift of function along time axis
“+” or “-” according to direction of lag.
φ/2π = the fraction of a period the function is shifted (if φ is in radians)
If “+” the second voltage is said to “lead” the first by φ.
If “-” the second voltage is said to “lag” behind the first by φ.
Period
The period over which the wave repeats itself is defined as T the period. It
can be calculated from the angular frequency ω = 2πf = 2π/T.
Graphing
If we look at V = V0sin(2πt/T) we can graph it easily.
V
3T/4
+V0
-V0
2T
t
T/4
T/2
T
If we look at V = V0sin(2πt/T + φ) we now can graph it easily.
V
+V0
t
-V0
The entire wave is shifted LEFT by T(φ/(2π)) seconds
AC – ALTERNATING CURRENT
We have now been introduced to circuits with time varying voltage. A
common type of time varying voltage is household power provided by
alternating current – in which voltage and current vary sinusoidally with time.
In North America power is provided in a 60 Hz sinusoidal cycle with root
mean square voltage of 120 V.
Period τ = (1/60) s
+ Vm
v
v = Vmsin(2πt/τ)
t
average value of v = 0
-Vm
Lower case v is used for varying voltage. Although the average v = 0, the
average v2 ≠ 0.
Period τ = (1/60) s
v2 = Vm2sin2(2πt/τ)
Vm2
v2
v2 = Vm2sin2(ωt)
where ω = 2π/τ
(angular frequency)
t
average v
2
=
1
τ
v (t )dt
τ∫
average value over one period
2
0
=
1
τ
τ
2
2
∫ Vm sin (ωt )dt =
0
2
Therefore the average v =
Vm2
τ
Vm2/2.
τ
2
∫ sin (ωt )dt =
0
Vm2
1
[1 − cos(2ωt )]dt = Vm
∫
τ 02
2
τ
2
The square of the maximum voltage/2
A useful quantity to define is the root – mean – square voltage, Vrms or the
square root of the average v2 ,
Vrms = v 2 =
Vm
2
= 120 V in North America.
This means that in the outlets in our homes, the maximum voltage per cycle
is Vm = 2 (120 V) = 170 V.
Phasor (Complex) representation of voltages and currents
A real sinusoidal voltage, v(t) = Vmcos(ωt) can be represented as a
complex number that varies in time:
z = v(t) = Vmejωt = Vm[cos(ωt) + jsin(ωt)]
conjugate = z* = Vm[cos(ωt) - jsin(ωt)]
(zz*) = Vm2[cos2(ωt) - jcos(ωt)sin(ωt) +jcos(ωt)sin(ωt) –j2sin2(ωt)]
= Vm2[cos2(ωt) + sin2(ωt)] = Vm2
Modulus = (zz*)½ = (Vm2)½ = Vm
Argument = ωt
The real part Vmcos(ωt) is the actual observable voltage. The imaginary part
represents the energy transferred to i(t). In the complex plane, at time t,
this looks like:
As the phasor
(complex#)
describing v(t)
sweeps thru
complex plane
-3
-2
2j
Vm
j
Vm
ωt
-1
Real part of v(t)
Varies sinusoidally
v(t + ∆t)
v(t)
1
-j
-2j
2
The modulus Vm is
constant.
ω(t + ∆t)
3
4
The same is true for an AC current: i(t) = Imejωt
2j
Im
j
-3
-2
-1
ω(t + ∆t)
Im
ωt
-j
Real part of i(t)
Varies sinusoidally
i(t + ∆t)
i(t)
1
2
3
4
-2j
Re[i(t)] = Re[Imejωt] = Imcos(ωt) = Imsin(ωt + π/2)
Kirchoff’s Laws and Alternating Current and Voltage
Kirchoff’s laws are also valid for alternating current circuits. The only
constraint is that they are only valid at each instant in time. However,
quantities from different times cannot be considered. Due to the finite
velocity at which electrical signals are physically transferred (they cannot
propagate faster than c), in some circuits “the same instant” is difficult to
define. This concern won’t be addressed even though it is a consideration in
the continent wide power grids. So Kirchoff’s laws are then…
1. At any instant in time, the sum of the voltages around a closed loop = 0
2. At any instant in time, the (current entering a point) = (current leaving)
Take note that the quantities can be handled as complex numbers e.g. i(t):
i2(t)
2j
j
-3
-2
-1
i3(t)
1
i1
i1(t)
2
i2
3
4
i1+i2 = i3
AC POWER CALCULATION:
Instantaneous power consumption: P(t) = i(t) v(t)
FOR RESISTORS:
Assume v= Vmsin(ωt) ⇒ current i = (Vm/R)sin(ωt) = Imsin(ωt).
P = iv = [Imsin (ωt)] [Vmsin (ωt)] = ImVmsin2(ωt)
Average power is determined using similar methods as for the rms voltage…
average P
=
I V
I V sin (ωt )dt =
∫
τ
2
1
τ
m m
2
m m
0
Therefore,
Pavg = IrmsVrms
Also
Vrms = IrmsR
So that
P = (Irms)2R = (Vrms)2/R
 I  V 
=  m  m  = IrmsVrms
 2  2 
AVERAGE POWER DISSIPATED IN CAPACITORS
AND INDUCTORS:
Assume v= Vmsin(ωt) ⇒ current i = CωVmcos(ωt)
P = iv = [CωVmcos(ωt)] [Vmsin (ωt)]
ωCVm2
= τ ∫0 cos(ωt )sin(ωt )dt
τ
average P
Solve by substitution:
Let x = sin(ωt)
then dx/dt = ωcos(ωt)
dx/ω = cos(ωt)dt
And the integral becomes:
ωCV
ωCV  x2

xdx =
∫
average P = τ x1
τ 2

2 x2
m
2
m
x2


x1 

2 τ 

ωCV (sin(ωt ))


average P = τ 
2
=0
0

2
m
A similar proof for inductors yields a zero as well – and it does not depend
on whether the voltage is calculated from the current or the other way
around. No matter how the quantities are calculated the integrand will
always be [sin(ωt) cos(ωt)] . Therefore, capacitors and Inductors do not
DISSIPATE power in a circuit. This is because the energy from the
voltage and current are not dissipated but stored 90o out of phase in the
electric or magnetic field generated by the device.
EXAMPLE 1: A toaster has a 700 W average power consumption. Vrms
= 120. Irms = ?
Pavg = IrmsVrms
Vrms = Irms R
R=?
Therefore, Irms = 700/120 = 5.83 A
Therefore, R = Vrms/Irms = 120/5.83 = 20.6 Ω
Impedance (See pg. 64-65 of text)
If we use complex numbers to describe AC voltages and currents we can
define a quantity called IMPEDANCE, Z = v/i
NB: only true for: i(t) = Imejωt
Resistor:
and
v(t) = Vmejωt
i(t) = v/R = (Vm/R) ejωt
ZR = v/i = [Vmejωt]/[(Vm/R) ejωt] = R
ZR = R
The impedance of a resistor = R, its resistance
i(t) = C(dv/dt)
= C[d(Vmejωt)/dt]
= Cjω Vmejωt = jωCv
Capacitor:
or an Inductor:
ZC
ZC
ZC
= v/i = v/(jωCv)
= 1/(jωC) = j/(ωC)
= -j/(ωC)
i(t)
=
=
ZL
ZL
1
v(t )dt
L∫
Z depends on ω for capacitor
V
1
Vm e jωt dt = m e jωt
∫
L
Ljω
= v/(jωL)
= v/i = v/[v/(jωL)]
= jωL
Impedances are manipulated like complex resistances. Purely resistive loads
are unchanged. Capacitors and inductors become frequency dependent phase
shifting resistors.
Equivalent Impedance ZEQ for Impedances in series
Equals…
Z1
ZEQ
Im
ZEQ
Z2
Z1
ZEQ = Z1 + Z2
Equivalent Impedance ZEQ for Impedances in parallel
Z1
Z2
=
Z2
ZEQ
1/ZEQ = 1/Z1 + 1/Z2
Re
AC Analysis using complex numbers
AC version of OHM’s LAW:
i = Vin/ZEQ
In polar exponential form:
i=
j(ωt + θ )
Ve
ZEQ
=
Ve j(ωt + θ )
ZEQ e jφ
=
Vin
ZEQ e jφ
V
e j(ωt + θ-φ )
=
ZEQ
or also
Vin
i= Z
EQ
=
Vin e j(-φ )
ZEQ
Where :
|ZEQ| = [(Re{ZEQ})2 + (Im{ZEQ})2 ]½ = magnitude of ZEQ in complex plane
and
φ = tan-1(Im{ZEQ}/ Re{ZEQ}) = argument of ZEQ in complex plane
This exactly like OHM’s law for DC resistors except we use the magnitude
of ZEQ rather than R to divide the voltage and the current is shifted -φ out
of phase with the voltage.
So all we have to remember with AC analysis is that the “resistance” is now a
complex number and we need to know both its magnitude and phase to
determine how the complex voltage relates to the complex current.
We will first revisit the RC and RL circuits except that we will now drive
these circuits with a sinusoidal AC voltage rather than with a DC voltage.
The RC circuit with Alternating Current
Let's consider a circuit containing both a resistor and a capacitor.
Vin = Vejωt
i
Vout
R
C
Vout = iR
⇒
need expression for i
From Kirchoff's loop rule:
Starting in upper left and going clockwise:
Vin – iZR – iZC = 0
⇒
i = Vin/(ZR + ZC)
⇒
i = Vin/[ R - j/(ωC)]
⇒
Vout = iR = (Vin) R/[ R - j/(ωC)]
Another way of looking at this is i = Vin/ZEQ
ZEQ = R - j/(ωC)
⇒
phase shift ⇒
and therefore
| ZEQ| = [(R - j/(ωC))( R + j/(ωC))]½ = [R2 + (ωC)-2]½
φ = tan-1[(1/(ωC))/R] = tan-1[(1/(ωCR)]
i = Vin/ZEQ =
V
R2 +
1
ω C2
ej(ωt - φ) = Imaxej(ωt - φ)
2
i(t) is just the input voltage Vin(t) with a magnitude divided by a factor of
|ZEQ| and phase shifted by φ. The frequency ω is unchanged.
This looks like
T = period = 2π/ω
V
T
t
-IMAX
IMAX =
V
φ = tan-1[(1/(ωCR)]
1
R2 + 2 2
ωC
Later we will do an example showing similar concepts in the complex plane…
While such relationship between current and voltage are useful, it turns out
that for many AC circuits (including this one), it is most interesting to study
the GAIN.
GAIN = Ratio of the output voltage over the input voltage = Vout/Vin
For this circuit…




 R 
1  Vin 


G = Vout/Vin = iR/Vin = V 
j 
j  R= 
in R −
R−



ωC 

ωC 

First rationalizing the denominator we find… (see expr. 9-5)
G=
j 



 R  R +
ωC 


 R − j  R + j 



ωC 
ωC 

=


 R 2 + jR 

ωC 
2 

 R 2 +  1  


 ωC  

=
(1 + j/(RωC ))
 1 
1+

 R ωC 
2
In an AC circuit the gain is also a complex number and it is useful to study it
in polar form…
|G| =



R

2
 2  1 
R
+



 ωC 








and φ = tan-1(1/(RωC))
The magnitude of the gain can be further simplified…
-2 -½
|G| = (1 + (RωC) )
1
=
 1 
1+

 R ωC 
2
As ω goes to infinity in the above circuit, the gain goes to 1. As ω goes to
zero the gain goes to zero. Therefore the above circuit is called a high pass
filter because it only passes high frequencies.
If such a circuit is AC analyzed using Microcap, the following Gain and phase
shift as a function of frequency plots are found….
THE LOW PASS FILTER
If, in the following circuit, the voltage across the capacitor is studied, we
find it has a very different behaviour from the high pass filter above.
Similar to high pass above
Except now we consider
The voltage across
capacitor
Rather than analyze the entire circuit again, we will simply plot v2 vs. time
(the output voltage across the capacitor). Transient analysis on Microcap
yields…
For this circuit, ZEQ = same as above for high pass filter and …
G = Vout/Vin = iZC/Vin =




- j/(ωC )
 Vin 
j 
Vin 
R−

ωC 

Simplifying the above we find… |G| = ((RωC)2 + 1)-½


 j/(ωC ) 

= - 
j 
R−

ωC 

For the R and C values listed above at 60 Hz this should yield a ratio of the
amplitude of the output voltage over the input voltage of 1/(17)½ which is
what we find in the above transient analysis graph. Calculation of the phase
shift yields…
AC analysis on Microcap gives the following graphs, which show that the
circuit is a low pass filter, suppressing high frequencies and passing low
ones…
|G|
φ
Bode plots for the above circuit
If you plot:
Gain in dB = 10log10(G)
vs Frequency on
on a logarithmic
scale you get a
BODE PLOT
The RL circuit with Alternating Current
Let's consider a circuit containing both a resistors and inductors.
Vin = Vejωt
i
R1
R2
Vout
L2
L1
Let’s determine i = Vin/ZEQ
ZEQ = REQ + jωL1 +
jωL2
Where 1/REQ = 1/R1 + 1/R2
ZEQ =
⇒ REQ =
R1R2
+ jω(L1 + L2)
R1 + R2
R1R2
R1 + R2
2
⇒
| ZEQ| =
 R1R2 

 + ω 2 (L1 + L2 )2
 R1 + R2 
phase shift ⇒ φ = tan-1[(ω(L1 + L2)/REQ] = tan-1[(ω(L1 + L2)(R1 + R2)/(R1R2)]
and
i = Vin/ZEQ = (V/|ZEQ|)ej(ωt - φ)
Vout = iREQ
Is the above circuit a low pass or a high pass circuit? – analyze on Microcap
to check….
Result should look like…
The RLC circuit
Applying Kirchoff’s loop rule starting
In the lower left of the circuit and
going clockwise.
R
L
Vin = Ve
Vin(t) – i(t)ZR – i(t)ZL – i(t)ZC = 0
jωt
C
Vin(t) = i(t)(ZR + ZL + ZC) = [ i(t)]ZEQ
Vout
Using expressions for ZR, ZL and ZC
Vin (t )
R + jωL − (j/ωC )
= i(t)
This is more difficult to interpret than in DC case since the relationship
between current and voltage now changes each time the frequency of the
input voltage ω is changed – FOR THE SAME COMPONENTS.
i(t) is clearly a complex number
In polar form… i(t) = Vin(t)/ZEQ = Ve
jωt
ZEQ e jθ
=
V
e j(ωt-θ )
ZEQ
Where |ZEQ| = the modulus of ZEQ = (R2 + (ωL – 1/ωC)2)½
 ωL − 1/ωC 
And θ = argument of ZEQ = tan-1 

R


Vin(t):
Modulus = V
Argument = ωt
Im
Modulus i(t) = V/|ZEQ|
i(t) argument i(t) =ωt + θ
ZEQ
Study limits of ω
V
Vin(t)
ωt
Re
|ZEQ| and θ are constant for fixed components and fixed values of ω.
Therefore as the phasor corresponding to Vin(t) sweeps through the complex
plane, the phasor corresponding to i(t) will be reduced w.r.t. Vin(t) by a
constant factor = |ZEQ|-1 and will lead Vin(t) by a constant phase shift =θ.
These concepts can be applied to any pure AC, RLC circuit (that is a circuit
containing any combination of R, L and C and driven by a purely sinusiodal
input voltage or current) after suitable simplifications have been made using
parallel and series impedance formulae and, if necessary, Thevenin’s method.


Vin (t )

From above: Vout = iZC = ZC 

(
)
R
+
j
L
−
j/
C
ω
ω




− (j/ωC )


Vin (t )


 (-j/ωC)/[Vin(t)] = 

 R + jωL − (j/ωC ) 
(
)
R
+
j
ω
L
−
j/
ω
C




Gain = Vout/Vin =
This is a complex number best plotted in polar form:
1

 2

(j/ωC )
− (j/ωC )
Modulus of the Gain = |G| = 





 R + j[ωL − (1/ωC )]  R - j[ωL − (1/ωC )] 
|G| =
1
(
ωC R 2 + [ωL − (1/ωC )] 2
= 1/(ωC|ZEQ|)
)
1
2
The phase shift,φ, of the gain can be calculated also and is left as an
exercise. The result is:
 1/(ωC ) − ωL 

R


φ (ω) = tan −1 
The output voltage Vout = GVin. Therefore if Vin is a sinusoidal driving voltage
then Vout will be sinusoidal with an amplitude Vin/|G| and a phase shift, θ.
What is interesting about these circuits is that at a certain frequency, the
circuit resonates and, if the resistance is low enough, the output voltage can
exceed the input voltage.
|G| =
1
(
ωC R 2 + [ωL − (1/ωC )] 2
)
1
2
The circuit resonates at the resonant frequency, ω0, which occurs when:
ω0L – 1/ω0C = 0
⇒
ω0L = 1/ω0C ⇒
1
LC
ω0 =
At resonance:
(ω0)2 = 1/LC
RESONANT FREQUENCY
ZEQ= R
|G| = 1/(ω0CR)
i(t) = Vin(t)/ZEQ = Vin(t)/R – current is in phase with voltage
Vout = i(t)ZC = -jVin(t)/(ω0CR)
Under such conditions:
• if R is zero the voltage gain would go to infinity. C cannot go to zero
because then the circuit does not resonate.
• The power coming out of the circuit does not go to infinity, it is balanced
by the current in the output part of the circuit.
|G| vs. ω plot using Excel
Values of
6
R = 0.2 Ω
C = 1 mF
L = 1 mH
Gain = Vout/Vin
ω = 2πf
NB
4
Gain
Were used
To make this
graph .
5
lim ω → 0
|G| = 1
3
2
1
0
0
500
1000
1500
2000
omega
2500
3000
3500
4000
Transfer Function
In AC circuits we often have an input voltage with a known amplitude, V,
angular frequency, ω and phase φ. This can be expressed in the form:
v = V(ω, φ)
The output voltage of the circuit, vout, has an amplitude, Vout, frequency, ωout,
and phase, φout, that ultimately depends on the input voltage (and therefore
V, φ and ω) and the circuit in question. The circuit will always have an
impedance that will depend in some way upon the frequency. Therefore the
output voltage can always be simplified to some function of the input voltage,
magnitude and phase:
vout = F(V, ω, φ) = V G(ω, φ)
The gain is a ratio of vout/vin, therefore G does not depend explicitly on V –
in linear circuits V will appear in the top and bottom and therefore cancel.
By working out the magnitude and phase of the gain, the phase dependence
and frequency dependence are separated and therefore |G| can be
expressed as the product of two functions: 1) H(ω),that depends only upon
the frequency and 2) ejφ:
G = Vout/Vin = H(ω)ejφout:
For example for a simple RLC circuit
H(ω) = |G| =
1
(
ωC R 2 + [ωL − (1/ωC )] 2
)
1
2
 1/(ωC ) − ωL 

R


φ (ω) = tan −1 
The function H(ω,φ) = H(ω)ejφ = G is sometimes also called the TRANSFER
FUNCTION. It contains all the information regarding how the input voltage
is transformed into the output voltage.
Simplifying parallel AC circuits using frequency dependence
Because of their frequency dependence, in some cases it is possible to
further simplify circuits FOR PARTICULAR LIMITING VALUES OF THE
FREQUENCY.
For example, given the circuit:
Vin
ZR = R
ZC = -j/(ωC)
We see immediately that the equivalent impedance for this circuit is:
ZEQ = ZRC = (ZRZC/(ZR + ZC)) = (R(-j/(ωC))/(R - j/(ωC)))
ZEQ = -jR/[RωC - j] = R/(jRωC + 1)
In general the circuit can only be simplified further using advanced methods
such as Thevenin equivalency, however in the limits:
ω → 0, ⇒ ZEQ → R = ZR
ZEQ acts like resistor at low ω
ω → ∞, ⇒ jRωC >> 1
⇒ (jRωC + 1) → jRωC
⇒ R/(jRωC + 1) → R/(jRωC) = 1/(jωC)
⇒ ZEQ → 1/(jωC) = -j/(ωC) = ZC
ZEQ acts like capacitor at high ω
General AC analysis
We now have the necessary techniques for solving multiloop AC and DC
circuits containing resistors, capacitors, inductors and AC and DC voltage
and current sources. We have also seen a few cases that are neither AC nor
Dc like step functions.
Let’s try to solve a more difficult AC circuit…
L
jωt
Ve
C
A
+
+
-
R1
i1
Iej(ωt+φ)
i2
B
R2
Let’s use KVL going around the left loop in a clockwise manner starting in the
lower left:
Vejωt – i1ZL – i1R1 + i2R1 - i1R2 = 0
Vejωt - i2R1 = i1 (ZL + R1 + R2)
(Vejωt - i2R1)/(ZL + R1 + R2) = i1
[1]
Let’s use KVL going around the right loop in a clockwise manner starting in
the lower left:
– i2R1 + i1R1 - i2ZC – VAB = 0
VAB = i2 (R1 + ZC)- i1R1
[2]
Where VAB is the unknown Voltage
across the constant current source
By inspection we have 2 equations and 3 unknowns, but we can see from the
diagram that i2 = Iej(ωt+φ), so we are back to two unknowns. Later we can use
the outer loop to check.
From [1], ZL = jωL and i2 = Iej(ωt+φ) we see that:
i1 = (Vejωt - Iej(ωt+φ)R1)/(jωL + R1 + R2)
[3]
and we have solved for i1.
Using [3] to sub into [2] we can solve for VAB:
VAB = Iej(ωt+φ) (R1 –j/(ωC))- R1(Vejωt - Iej(ωt+φ) R1)/(jωL + R1 + R2)
The circuit is then solved. It could be checked symbolically using the outer
loop, but this would be time consuming. It would be easier to check it
numerically once values are assigned.
In this case, due to the inclusion of a constant current source, the equations
became much easier to solve. However, for a voltage source in the place of
the current source a system of 2 equ.’s in 2 unknowns results. This is solved
using algebra or Cramer’s method. See page 76 of the text for an example.
Example: Thevenin’s Method in AC
Given the circuit:
Vin = Ve
L
jωt
R
C
Solve for the current
thru the capacitor
First replace the entire circuit except the capacitor with the Thevenin
equivalent circuit:
ZTh
VTh
C
Step 1 –Compute the Thevenin Equivalent Voltage VTh of the original circuit
without the capacitor:
L
i = Vin/(ZL+R) = Vin/(jωL + R)
VTh = iR = VinR/(jωL + R)
Vin
R
Step 2 –Compute the Thevenin Equivalent impedance ZTh of the original
circuit without the capacitor by replacing the voltage source in the above
circuit with a closed circuit:
1/ZTh = 1/ZL + 1/R
L
1/ZTh = 1/(jωL) + 1/R
R
VTh
ZTh = jωLR/(jωL + R)
Step 3: The original circuit
L
Vin
R
C
can now be replaced with its Thevenin Equivalent circuit:
ZTh
VTh
C
The current,i, in the capacitor in the above circuit is easily determined:
VTh – iZTh – iZC = 0
⇒
VTh = i(ZTh + ZC)
⇒
VTh/(ZTh + ZC) = i
Substituting our expressions for ZTh and VTh we obtain:
i=
Vin R/ (jωL + R )
jωL/(jωL + R ) − j/(ωC )
VinR
= jωL − j(jωL + R )/(ωC )
which is the current thru the capacitor.
The voltage thru the capacitor is iZC = 1/(ωC)
Vin R
(jωL + R )/(ωC ) - ωL
This function can be checked by determining that it has the correct
behaviour for low and high frequency limit and also by conventional AC
analysis. Thevenin’s method was not “required” for this circuit.
Transformers
A transformer is a commonly appearing linear circuit element. Transformer
consist of two (or more) inductors placed near enough to each other to
induce a current in each other. That is, a strong magnetic field form one coil
passes through the other.
The symbol for a transformer is:
(Air core)
P1
TRANSFORMERS
(Iron Core)
P2
The induction relations between the coils result in a change in current in coil
1 inducing a change in current in coil 2. The general relationship for any type
of time varying current is:
di1/dt = (N2/N1)di2/dt
[A]
where Ni is the number of turns in coil i. Clearly a transformer will not do
anything in a DC circuit where di/dt = 0.
Because energy is conserved the power on the input side must be equal to
the power on the output side of the transformer:
P1 = P2
We know that P = IV and for a time varying voltage we can write…
or
i 1 v 1 = i 2v 2
i1/i2 = v2/v1
Taking the derivative of the top and bottom on both sides we find:
(di1/dt)/(di2/dt) = N2/N1 = (dv2/dt)/(dv1/dt)
Where equation [A] has been used to simplify the LHS.
For AC VOLTAGES, the derivative of v1 = (constant)v1 therefore we may
write:
N2/N1 = v2/v1
THEREFORE
(N2/N1) v1 = v2
Uses of the transformer:
1) Step up or step down power transformers. High voltage AC power
transmitted from generator to where it will be used (to reduce P = I2R
power loss in transmission line).
2) Step up or step down transformers in devices to match power source with
device
3) Impedance matching: Input sees Z1 = v1/i1. Output sees Z2 = v2/i2.
Therefore:
N 
v2  1 
N
Z1 =  2  = (v2/i2)(N1/N2)2 = Z2(N1/N2)2
N 
i2  2 
 N1 
Viewed from the input the output impedance, instead of being Z2 is
transformed to Z2 times the square of the turns ratio. This means
transformers can be inserted into a circuit to achieve the maximum power
transfer matching impedance. We saw earlier for resistances that this was
achieved when the impedance of the source matches that of the output.
Transducers
An electronic transducer is a device that transforms energy from one form
into another where one of the forms of energy is electric energy.
Output transducers: are those that have electronic input and output
another form of energy. Examples include: speakers, motors, stove burners,
light bulbs and microwave ovens. All output transducers convert electrical
energy into useful WORK.
Input transducers: are those that have electronic output and another form
of energy as input. Examples include: microphones, generators, thermostats
, photovoltaic cells and microwave receivers. All input transducers convert
WORK into electrical energy.
There are two further distinctions that can be made with regards to
transducers:
Passive Transducers operate without the need for an external power source
(that is: additionally to the power being converted.)
Active transducers must draw power from an external power source in order
to work.
Transducers are of fundamental importance. Any application that is not
purely electronic in nature (i.e. EVERY application) must rely on a transducer
at some point. Most common transducers are important enough to be fields
unto themselves (e.g.: generators and motors, em transmitters and
receivers, photovoltaic cells).
Input transducers are the only way for an electronic device to acquire data
about its surroundings.
In general, transducers can rely on any electronic effect to transform the
electricity. Piezoelectric effects (piezoelectric strain gauges),
semiconductor electronics (e.g. L.E.D’s), or digital electronics.
Transducers based on Inductors: the VOLTMETER
The most basic transducer and one you have encountered frequently in the
lab is the voltmeter. Although many voltmeters are digital and work using
different physics, the analog voltmeter functions as follows:
readout
Magnet
coil
Magnet
Spring
Vin
A coil wrapped around an indicator needle sits in a permanent magnetic field.
A measured voltage, Vin, is induced a current in the coil, which in turn
creates a magnetic field. The magnetic field caused by the coil interacts
with that caused by the permanent magnets to produce a force on the
spring. The magnetic field produced by the coils is proportional to the
current and hence to the input voltage. The deflection of the indicator
needle, attached to a carefully wound linear spring, on the readout is
proportional to the force between the coil and the magnet and hence
proportional to the input voltage. By carefully calibrating the position of the
marks on the readout an accurate measurement of the voltage is possible.
When being used a voltmeter the coil has a large resistor in series with it so
that it does not draw any current and change the voltage to be measured.
The Ammeter:
The ammeter functions the same way as the voltmeter. The user must
ensure that when measuring current the coil is in series with the current to
be measured to ensure that the currents are the same. Now the resistance
is as small as possible to ensure that the ammeter uses as little power as
possible and has the smallest effect possible on the circuit.
Transducers based on Resistors:
Any 3-pole variable resistor can be utilized as position sensitive transducer:
wiper
Variable
Resistor (3 – pole)
As the position of the wiper is changed, the resistances RA and RB change. In
conjunction with a spring (and a voltmeter to produce a readout) such a
simple device could function as a scale.
Spring
Force
Vout
RA
RB
Vin
RA
Vin
RB
Because
RA = ρLA/A
And
RB = ρLB/A
and LA = F/k
Vout
Vout = RB/(RA + RB) ∝ F
A resistor may also be used to set up as a strain gauge
Input
WHEATSTONE BRIDGE
The resistance of the resistor in the middle of the following arrangement
RW = ρL/A. RW is chosen so that the
voltage across it at equilbrium (Force =
0) is zero. In this arrangement the
Force
circuit will be very sesnitive to small
changes in Rw. The length will change
slightly as a strain is applied. This will
change the resistance RW. The area of
the resistor will change only very very
slightly under small changes in the
length, L. (NB Strain = ∆L/L)
Output voltage
voltage
The resistivity will change somewhat as a function of temperature as will the
Young’s Modulus (related to the elasticity) of the material. The Wheatstone
bridge arrangement is used because the errors introduced will cancel out in
the other resistors. Therefore this strain gauge will be very accurate over a
range of conditions.
Capacitive Transducers
In general reproducible results are obtained when the transducer is far
away from the “plastic” limit. The best way to ensure this is to have a
transducer that does not change in shape very much. Because capacitance is
sensitive to the geometry, Capacitors make excellent stress and strain
gauges
Remember
Force
,parallel plate
d
Vout
capacitance is:
Vin
C = εA/d
where ε is the dielectric constant of the material inside, A is the plate area
and d is the distance between the plates.
Introduction to Digital Logic
In analog devices, such as an output transducer (discussed in the last
section), the output voltage is proportional to some desired information.
The voltage may take on any real value, hence, the information contained in
each reading from the device is limited only by the precision of the
instrument. It may contain a great number of significant figures.
In digital devices, the entire voltage range is split into two logical domains,
true and false. The exact values corresponding to true or false varies with
the device, but the information contained in the all the significant figures is
reduced to one of two options: low or high.
The simplification enabled by digital logic has led to its application in many
electronic devices – despite the information loss. Most devices rely upon a
combination of both approaches - neither process is superior in all cases.
Digital Logic
•
•
•
•
Binary - i.e. 2 options: true and false, high and low, or 0 and 1.
Each such state is called a bit.
Logical variable = string of bits
logical operations change individual bits and therefore the variable.
The wide variety of digital devices attests that any complicated function can
be broken down in a series of logical operations. The most basic of these
operations are AND, OR and NOT. They convert a varying number of inputs
into a single output.
Truth Tables
Tabulating all possible outcomes for every input state of a device
will characterize it in a truth table. Since each input can only be in one of
two states: true or false, there are only 2N possible input states for the
device (compared with ∞ for an analog device). Therefore, for an operation
with M outputs, the truth table will have 2N rows and (N + M) columns – each
row indicates a possible input state of the device arranged in N columns.
The last M columns contain the output states for each possibility.
Logical gates:
The electronic circuits that carry out basic logical operations are called
logical gates. The schematic symbols and truth table for a few important
ones are shown below.
LOGICAL AND
The quantity (A AND B) is true if and only if (iff) both A and B are true.
The truth table is:
Symbol
A
B
A AND B
T
T
F
F
T
F
T
F
T
F
F
F
LOGICAL OR
The quantity (A OR B) is true if either A or B are true. The truth table is:
Symbol
A
B
A OR B
T
T
F
F
T
F
T
F
T
T
T
F
LOGICAL NOT
The operation NOT(A) is the opposite of A. e.g. if A is true, NOT(A) =F.
Symbol
A
NOT(A)
T
F
F
T
Other logical operations
It turns out any other logical operation can be constructed from a
combination of those above (see DeMorgan’s Law below). A few logical
operations are so common that they have been given names and symbols:
NAND = NOT (A AND B)
The truth table has output that is the opposite of AND i.e. NOT AND
Symbol:
NOR = NOT (A OR B)
The truth table has output that is the opposite of OR i.e. NOT OR
Symbol:
XOR = Exclusive OR. – Can be constructed out of NOT, AND and OR
gates – see problem #2 assignment 6 or text 19-1.
Symbol
A
B
A XOR B
T
T
F
F
T
F
T
F
F
T
T
F
Note the 1st row of table makes XOR “exclusive”, that is A XOR B only is
True only if one input is True.
XNOR = NOT XOR.
Symbol
A
B
A XNOR B
T
T
F
F
T
F
T
F
T
F
F
T
Boolean algebra
•
•
•
•
•
Named after George Boole
Limited to 0 and 1 as possible values for variables
Basic operations, addition (OR), multiplication (AND) and negation (NOT)
Notation allows proofs to be expressed concisely
Truth tables below
A
Addition (OR)
B
A+B
1
1
0
0
1
0
1
0
1
1
1
0
Multiplication (AND)
A
B
A∗B
1
1
0
0
1
0
1
0
1
0
0
0
Negation (NOT)
A
A
1
0
0
1
Logical Theorems
Circuit simplification and proofs for any logical theorem is possible using
Boolean Algebra. Both can also be checked by testing all the possible
combinations in a truth table.
Because all possible outputs (0 or 1) = all possible inputs (0 or 1) and because
addition and multiplication are commutative (e.g. A + B = B + A) and
associative (e.g. A ∗ (B∗C) = (A∗B)∗C), this logical system forms an Abelian
Group. Abelian groups are studied extensively in linear algebra.
The following theorems can be proven using commutativity and additivity and
any of the theorems higher in the list or by testing all possible combinations
by using a truth table.
(a)
A+A=A
(b)
A∗A=A
(c)
A+1=1
(d)
A∗1=A
(e)
A+0=A
(f)
A∗0=0
(g)
A+ A =1
(h)
A∗ A =0
(i)
NOT(NOT(A)) = A
(j)
A ∗ (A + B) = A
(k)
A + (A ∗ B) = A
(l)
A ∗ ( A + B) = A ∗ B
(m) A + ( A ∗ B) = A + B
(n)
A + (A ∗ B) = A + B
(o)
A + (A ∗ B ) = A + B
(p)
A *B = A + B
A + B = A *B
(q)
Theorems (a) through (h) are easily shown using a truth table. E.g. theorem
(h): A ∗ A = 0
A
A∗ A
A
1
0
0
0
1
0
proofs of (a) to (g) left as exercise
Theorem (j) proven with Boolean algebra.
LHS (j)
= A ∗ (A + B)
=A∗A+A∗B
=A+A∗B
= A ∗ (1 + B)
=A∗1
=A
= RHS (j)
by distribution
by theorem (b)
by distribution
by theorem (c)
by theorem (d)
by inspection
Theorem (k) proven with Boolean algebra.
LHS (k)
= A + (A ∗ B)
=A∗A+A∗B
= A ∗(A + B)
=A
= RHS (k)
by theorem (b)
by distribution
by theorem (j)
by inspection
For proofs of Theorem (l) using Boolean Algebra and (p) using truth tables
see text (Faissler) page 153.
Proof of theorem (m) left as exercise.
Theorem (n) is just theorem (m) with A and NOT(A) switched. Theorem (o)
is just theorem (n) with NOT(B) substituted everywhere for B.
Theorem (q) A + B = A * B proven using truth table.
A
B
A+B
A+B
A
B
A *B
1
1
0
0
1
0
1
0
1
1
1
0
0
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
The columns marked by the arrows are the same, therefore, they represent
the same logical values and therefore: A + B = A * B and theorem (q) is true.
Theorems (p) and (q) show that any logical operation can be constructed out
of a combination of NOT and OR gates or by a combination of NOT and
AND. All three types of gate NOT, OR and AND are not required. This is
handy if there is a difficulty obtaining a particular type of gate. The laws
are known as DeMorgan’s Laws.
e.g.: construct A AND B using NOT and OR.
from theorem (p) A * B = A + B ⇒NOT( A * B ) = A∗B = NOT( A + B )
With AND, OR and NOT any logical operation may be performed.
Practical Considerations for Logical gates
Logical gates are imprinted by a variety of techniques on silicon wafers to
form complete circuits called integrated circuits or chips.
Millions of logical gates may be placed on a single cm2 of silicon wafer – good
for computers – bad in lab
Much easier in lab to work with chip with small number of well spaced gates.
The most common package is called a Dual in line (DIP) package:
Quadruple 2 input NAND integrated circuit DIP.
VCC
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GROUND
2 rows of leads.
Propagation delay
•
•
•
•
•
•
new output not generated at instant either input changes
time delay = gate propagation delay
depends on mainly on gate type
other factors influence: e.g. type of transition, capacitance of leads
typical delays 1-100 nanoseconds
important element limiting computational speed
Design of Logical Circuits
There are two basic methods in circuit design:
1) Design a circuit with a truth table that performs a certain function.
2) Determine changes in the truth table when a circuit is modified.
The 2nd method is reverse design. The method consists of propagating all
possible inputs through the circuit and determining the outputs.
Example 1 – Reverse Design
A
X
B
OUTPUT
B
B
C
Work out truth table for X
Y
A
B
B
X
T
T
F
F
T
F
T
F
F
T
F
T
F
T
F
F
and for Y
B
C
T
T
F
F
T
F
T
F
B
Y
F
F
T
T
T
F
T
T
and then determine OUTPUT truth table. The final table will have 23 = 8
rows because there are 3 inputs.
OUTPUT TRUTH TABLE
A B C X Y OUTPUT
T
T
T
T
F
F
F
F
NB Y and OUTPUT turned out
T T F T
T F F F
F T T T
F F T T
T T F T
T F F F
F T F T
F F F T
to be the same
T
F
T
T
T
F
T
T
Sum of Products Method
Sometimes we want to design a circuit having a truth table designed for a
specific purpose (forward design). This is done in several steps:
1) Designation of logical variables describing the system
2) Determination of the desired truth table for the system
3) Design of circuit having the desired truth table
4) Simplification to the smallest circuit performing the desired function
Sum of Products (SOP) Method: Description
Steps 1 and 2 require no special methods to perform. The Sum of Products
Method is a way of performing step 3. Simplification can be done with
Boolean Algebra or using Karnaugh Maps (discussed later).
The Sum of the product method is based on the fact that only 1 line in an
AND (or product) gate is true. Therefore, each TRUE appearing in the final
output can be expressed as a PRODUCT of the inputs that produced it. Any
other input in the product will not add another TRUE result to the final
output. The SUM (OR) of all such PRODUCTS will generate the correct final
OUTPUT. Each product of inputs producing a TRUE final output is called a
miniterm. Miniterm inputs that are false appear as NOT(input) in product.
Example 2 – Sum of Products Design – text pg. 162
Design a digital network that will allow two switches to control a single light
bulb.
Function: Toggling any switch in any position changes the state of the light.
Step 1)
Designate the variables describing the system. We will
designate the switches A and B. We will call the “up” state for each switch
TRUE and the “down” state FALSE. The “on” state for the light bulb will be
called TRUE and the “off” state FALSE.
Step 2)
Construct a truth table
Switch A
Switch B
Light
T
T
F
F
T
F
T
F
T
F
F
T
Verification that the above truth table is correct:
There is no combination of positions for switch A and switch B where
changing the state of one of the switches does not change the state of the
light bulb. Therefore, toggling the state of ANY switch changes the state
of the light bulb. This is the desired function. Therefore the above truth
table is the correct one.
Step 3)
Design a circuit that will replicate the above truth table.
Using the SOP method we notice that two lines have true outputs in the
truth table (1st and 4th). The two miniterms (products) corresponding to
these two TRUE output states are A∗B and A ∗ B . Therefore the desired
output is the sum (OR) of these two products:
OUTPUT = A ∗ B + A ∗ B
The circuit that performs the above logical operations is:
A∗B
A
B
OUT
A∗B
This circuit can be simplified using theorem (q)
A + B = A *B .
FINAL CIRCUIT:
Example 3 – A More Complex Example
Design a circuit that
A
T
T
T
T
T
T
T
T
F
F
F
F
F
F
F
F
has the following truth table as output:
B
C
D
OUTPUT
T
T
T
F
T
T
F
T
T
F
T
F
T
F
F
F
F
T
T
F
F
T
F
F
F
F
T
T
F
F
F
F
T
T
T
F
T
T
F
F
T
F
T
F
T
F
F
T
F
T
T
F
F
T
F
F
F
F
T
F
F
F
F
F
The truth table contains just three outputs that are true. These generate
three miniterms which are summed together to form the solution:
Output = A ∗ B ∗ C ∗ D + A ∗ B ∗ C ∗ D +
A ∗B∗ C ∗D
Simplification using Boolean Algebra (circuit to come later…)
Output
= (B ∗ D ) ∗ (A ∗ C
= (B ∗ D ) ∗ (A ∗ C
+
+
A ∗ C) + A∗ B∗ C ∗D
A+C) + A ∗ B ∗ C ∗ D
Example 4 - Karnaugh Maps
Another way to find a simple circuit to perform a logical operation is a
Karnaugh map. This method works well for up to systems with up to four
input variables. Consider the following truth table (text page 169):
The SOP method would
yield 4 miniterms →
A
B
C
Output
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
1
1
0
0
0
1
0
Output = A∗B∗C + A∗B∗ C + A∗ B ∗C + A ∗ B ∗C
= A∗B∗(C + C ) + (A + A )∗ B ∗C
= A∗B
+ B ∗C
This can be simplified to: Output
If the use of Boolean Algebra seems difficult. An alternative method of
obtaining a simplified circuit is a Karnaugh Map.
AB
C
00
01
11
10
0
1
0
1
0
0
1
1
0
1
NB only 1 variable changes between adjacent cells. Now the connected areas
containing all 1’s (TRUE) must be identified along with their corresponding
logical expressions.
AB
C
00
01
11
10
0
0
0
1
0
1
1
0
1
1
The red ellipse corresponds to A∗B∗(C + C ) = A∗B
The blue ellipse corresponds to A∗(B + B )∗C = A∗C
The green ellipse corresponds to (A + A )B ∗C = B ∗C
read from Map
Note well that the table should be read as though it were wrapped around a
cylinder (notice the green ellipse). The solution is the sum of the three
expressions:
output = A∗B + A∗C + B ∗C
However we can see from the diagram that the space spanned by the blue
ellipse (A∗C) is covered by the other two ellipses, hence it is not required in
the solution:
output = A∗B + B ∗C
This is the final solution from the Karnaugh mapping method. Note it is the
same as the simplified solution from the SOP method, however, no use of
algebra was required to obtain it.
Example 5 – Simplifying e.g 3 using Karnaugh Maps
Karnaugh Map for truth table from Example 3:
AB
CD
00
01
11
10
00
01
11
10
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
The algebraic expressions that correspond to the above are:
OUTPUT = A ∗B∗ C ∗D + A∗B ∗ C ∗D + A∗B∗C∗D
This is the same expression as the result of the SOP method. If there were
major simplifications possible, there would have been connected zones.
The fact that there are no major simplifications means we might as well use
the circuit resulting from the expression above…
Circuit for example 3 and 5.
A
B
C
A
A
B
B
C
C
D
D
D
A
B
C
D
A
B
C
D
OUT
A
B
C
D
The connection between the left half and right half are not drawn in for
clarity. It is obvious which leads connect.
Sequential Digital Logic
So far, we have been discussing Combinatorial Logic. In this type of logic,
only the current combination of input levels matter. Previous input levels are
irrelevant. A given set of input levels always produces the same output.
Most digital applications also employ Sequential Logic. In sequential logic,
the history of the circuit matters (i.e. previous input levels). A given set of
input levels may produce different output depending upon the history.
Therefore when using sequential logic, some circuit needs to remember the
history of the circuit. This memory is supplied by a combination of gates
called a flip-flop.
Because sequential logic remembers previous input levels, the concept of a
pulse train becomes relevant. A pulse train is a series of changes in the
logic level, plotted as a function of time.
Positive going pulse train
Leading edge
trailing edge
1
0
Positive edge
negative edge
RS FLIP - FLOPS
The most basic flip-flop is the RS flip flop. It consists of two NANDS in
parallel.
S
R
Q
•
•
•
Label R stands for Reset
Label S on the stands for Set
State of output Q defines state of flip flop.
Function of RS flip-flop.
Because there are two outputs, there are in principle 4 output states: both
high, both low and 2 mixed states. Similarly there are 4 input states. We
will start by considering that the S and R inputs are both high. What are
the possible output states? Let’s check the possibilities one at the time.
A)
S and R inputs are both high
1)
Both outputs high: If both outputs are high then both NAND gates
have two high inputs. The truth table for NAND shows that this
corresponds to a low output. Therefore this state is impossible. It
contradicts itself.
2)
Both outputs low: If both outputs are low then each NAND gate
would have one high and one low input. Each NAND output in this case
(see truth table) is high. This state also contradicts itself. It’s
impossible.
3)
Top output high, bottom output low: In this case the top NAND has
one high input and one low input. The NAND output in this case is high
– matching our assumption. The bottom NAND has two high inputs
resulting in a low output – again matching our assumption. This state
persists as long as S and R remain high.
4)
Top output low, bottom output high: In this case the top NAND has
two high inputs. The NAND output in this case is low – matching our
assumption. The bottom NAND has one high input and one low input
resulting in a high output – again matching our assumption. . This state
persists as long as S and R remain high.
Therefore when S and R inputs are both high there are only two
possible output states. The outputs must be the opposite of each other
and hence the outputs are labeled Q and Q . As long as R and S
remain high, the output state is stable and remains unchanged.
Whether Q is high or low will depend on the HISTORY of the circuit. This
is how Flip-flops serve as memory. The way this happens is discussed below.
1. What happens when S input changes from high to low? R remains
high.
1)
If Q was high: then Q is low and the top NAND has two low inputs.
This requires that the upper gate have a high output, therefore the
top output STAYS HIGH. The bottom NAND has two high inputs and
therefore has a low output – the bottom output STAYS LOW.
2)
If Q was low: then Q is high and the top NAND now has one low and
one high input. The NAND operation on the upper gate then
CHANGES ITS OUTPUT TO HIGH.
For any output state, Q will be high after S goes negative.
2. What happens when S input changes back from low to high? R
remains high.
From the above discussion Q can only be high now – the other output
must be low. Input S switching back to high “locks” or latches the
flip-flop in the high state. Further negative pulses on S do not change
anything. This corresponds to case A3 above. Except now we see that
it will persist as long as nothing occurs on the R input.
3. What happens when R input changes from high to low? S remains
high.
We have shown that, at this time that Q is high, and Q is low. The
bottom NAND has a High and a Low input - its output MUST change
to high. Once this change occurs, the top NAND now has two high
inputs. Its output will change to low. The bottom NAND now has two
low inputs, however this does not cause any further change.
4. What happens when R input changes from low back to high.
Q is low. R switching back to high does not affect Q and therefore
does not effect Q. Further negative pulses on R also have no effect
For any output state, Q will be low after R goes negative.
5. What happens if R and S go low simultaneously?
Because each NAND now is guaranteed to have at least one low input,
both outputs are guaranteed to end up high regardless of their preexisting state.
6. What happens when the R and S simultaneously return to high.
The flip-flop’s state is now given by the last line to return to positive.
If S goes positive LAST, then Q is High and vice versa. However, it is
completely RANDOM which gate is slower. Therefore the output
resulting from this situation is undetermined.
Therefore the RS flip-flop is has two stable states as long as R and S are
both high. The circuit remembers the last negative pulse. If the last
negative pulse is on the S line, Q is high. If the last negative pulse was on
the R line, Q is low. If the negative pulses overlap, the last gate to return
to positive dictates the state of the flip-flop. If they return to positive
together, then the output is RANDOM and therefore labeled indeterminate.
For R and S starting LOW, we would find that the output on both NANDS
always goes to high and stays there. The circuit responds usefully only to
negative logic. Therefore the circuit is more correctly called a
flip-flop.
Symbol
FF
Q
The NOT bars over inputs signify
negative logic
GENERALIZATIONS
R2
R1
Q
We do not need to restrict
ourselves to flip flops with
single R and S lines.
FF
Q
S
A similar analysis would show that a negative pulse on ANY R input resets
the flip-flop. In effect the multiple inputs behave as if they are OR’ed
together. This is a consequence of DeMorgan’s Laws.
If the negative logic presents difficulties, NOT gates can be added to the
inputs to cause the input to respond to positive pulses.
S
Q
FF
Q
R
A similar analysis would show that a positive pulse on the R input resets the
flip-flop (Q low) and a positive input on the S input set Q high.
It is also possible to construct a flip-flop from NOR’s. (See text page 179).
This flip flop will respond to positive logic. There are a great variety of flipflops in use and therefore it is imperative to read the data sheet when using
them in the lab.
RS and RS Flip-Flop – what’s the difference?
Technically the Flip-flop discussed above is a RS flip-flop. There is some
confusion at times with the nomenclature because it is often called an RS
FF. To clear things up, the internal structure and truth table for an actual
RS flip flop is provided.
S
R
0
0
1
1
0
1
0
1
Q
no change
0
1
1
0
undefined
Notice the RS flip-flop behave the same as the R’S’ flip-flop except that it
responds to positive logic rather than negative.
CLOCKED FLIP - FLOPS
A regular RS type flip flop is always “ON”. That is it is always sensitive to
what is happening at the inputs. In many circuits, it is useful to have a flipflop whose input sensitivity can be turned on and off. The signal responsible
for doing this is called the clock signal because usually it is timed to occur at
regular intervals so an entire synchronous circuit can operate using that one
signal and all the relevant flip-flops or only activated as the clock signal
pulses through the circuit.
The symbol for
a Clocked RS flip-flop is:
S
C
On the inside they look like…
gate
Q
FF
S
C
R
R
Because of the NAND’s in the gate part of the circuit, a clocked RS FF
responds to positive logic pulses.
While the clock pulse is high, a high input at either R or S will produce a low
output at corresponding gate NAND and the final output from the FF behind
the gate will change. The FF will continue to respond in the normal way to
any pulses on the R and S inputs while the clock is high.
While the clock pulse is low then both gate NAND’s have at least one low
input, therefore the outputs to the gate NAND’s are both high and the
output state of the RS flip flop behind the gate will be fixed.
Q
This behavior can be summarized in a characteristic table.
Input State
State after Pulse
S
R
C
Q
X
L
H
L
H
X
L
L
H
H
L
H
H
H
H
Unchanged
Unchanged
H
L
Indeterminate
Unchanged
Unchanged
L
H
Indeterminate
Many other behaviours are possible with just a few gates for clocked FF’s.
see appendix A of the book for references.
DATA LATCHES
The D flip-flop (transparent latch) avoids the undefined states in the RSFF
truth table by reducing the number of input options
D
C
X
0
1
0
P
P
Q
No change
0
1
1
0
D
C
RS
FF
Q
Where X means “any input” and P stands for a clock pulse. Some DFF’s have
additional inputs on the second set of NAND’s to allow the circuit to be set
independent of the Clock, C. See problem 21-3 from the text. When these
inputs are used the circuit behaves just like a regular RS FF.
JK Flip-Flop
Another variation of the RS FF that avoids the undesirable undefined state
is called the JK FF. It replaces the undefined state with a useful state
called “toggle”. The toggle state is useful in counting circuits.
The JKFF simplifies the RSFF truth table but keeps two inputs. If the C
pulse is too long this state is undefined and hence the JKFF can only be used
with rigidly defined short clock pulses.
Consider the following cases:
1)
J=K=0: Both AND gates outputs must be at zero because the both
have at least one zero input. Therefore S = R = 0 and the state of the
RS FF behind the gates is UNCHANGED.
2)
J = 0, K = 1: Then S = 0, as the top AND gate has a zero input. The
only possibilities are for the RS FF to be in the RESET state or to
remain UNCHANGED. If the RS FF was in the SET state (Q = 1),
then R = 1 momentarily when the CLOCK pulse (C) arrives. Therefore
at that time R = 1, S = 0 which RESETS the RS FF. Now the ANDS in
front of the RS FF both have at least 1 zero input – therefor after
RESETTING, the JK FF returns to the UNCHANGED or stable state.
If the RS FF was in the RESET state – then RESETTING it again
won’t change its state.
3)
J = 1, K = 0: Then R = 0, as the bottom AND gate has a zero input.
The only possibilities are for the RS FF to be in the SET state or to
remain UNCHANGED. If the RS FF was in the RESET state (Q’ = 1),
then S = 1 momentarily when the CLOCK pulse (C) arrives. Therefore
at that time S = 1, R = 0 which SETS the RS FF. Now the ANDS in
front of the RS FF both have at least 1 zero input – therefor after
RESETTING, the JK FF returns to the UNCHANGED or stable state.
If the RS FF was in the SET state – then SETTING it again won’t
change its state.
4)
J = 1, K = 1: Assume Q = 1 to start. Then the bottom AND gate has
its output = 1 momentarily when the CLOCK pulse arrives. At the same
time, the top AND gate has a zero input and output because Q’ = 0.
Thus, S = 0 and R = 1 and the circuit changes to the RESET state.
Now assume Q = 0 to start. Then the top output has its output = 1
momentarily when the clock pulse arrives. at the same time the
bottom AND gate has a zero output because Q’ = 0. Thus S = 1 and R
= 0 and the circuit changes to the SET state. Therefore each clock
pulse changes the output state of the JK FF to the opposite of the
previous state as long as J = K = 1. For this reason this state is called
the TOGGLE state.
An interesting use of the toggle state is as a frequency divider. Each CLOCK
pulse raises the logic level to 1 and then drop it back to zero. Each CLOCK
pulse drives the output put level from low to high or vice versa. It requires
two clock pulses to complete the cycle at each output high ie) drive the level
to high and back to low.
Preset and Clear
Many FF’s have additional inputs to intialize the state of the FF independent
of the CLOCK pulse.
PRESET
S
Q
C
CLEAR
R
JK Master-Slave Flip-Flop
We can simulate a dynamic clock input by putting two flip-flops in tandem,
one driving the other in a master/slave arrangement as shown below. The
slave is clocked in a complementary fashion to the master.
This arrangement is still pulse triggered. The data inputs are written onto
the master flip-flop while the clock is true and transferred to the slave
when the clock becomes false. The arrangement guarantees that the
outputs of the slave can never be connected to the slave's own RS inputs.
The design overcomes signal racing (ie. the input signals never catch up with
the signals already in the flip-flop). There are however a few special states
when a transition can occur in the master and be transferred to the slave
when the clock is high. These are known as ones catching and are common in
master/slave designs.
Edge Triggering
Edge triggering is when the flip-flop state is changed as the rising or falling
edge of a clock signal passes through a threshold voltage (figure 7.24). This
true dynamic clock input is insensitive to the slope or time spent in the high
or low state.
Both types of dynamic triggering are represented on a schematic diagram by
a special symbol near the clock input (figure 7.25). In addition to the clock
and data inputs most IC flip-flop packages will also include set and reset (or
mark and erase) inputs. The additional inputs allow the flip-flop to be preset
to an initial state without using the clocked logic inputs.
More Practical considerations for digital logic
•
In digital circuits all inputs must be connected.
•
Logic circuits are grouped into families, each with their own set of
detailed operating rules. Some common logic families are:
1.
2.
3.
4.
5.
6.
RTL: resistor-transistor logic,
DTL: diode-transistor logic,
TTL: transistor-transistor logic,
NMOS: N-channel metal-oxide silicon,
CMOS: complementary metal-oxide silicon and
ECL: emitter-coupled logic
Normally signals flip from one logic state to another. The time it takes the
signal to move between states is the transition time tt, where the time is
measured between 10% and 90% of the signal levels. Delays within the logic
elements result in a propagation (pulse) delay tpd, where the time is
measured between 50% of the input signal and 50% of the output response.
Definitions of the transition time and propagation delay are shown below
The one-shot (also called a monostable multivibrator) is essentially an
unstable flip-flop. When a one-shot is set by an input clock or trigger pulse,
it will return to the reset state on its own accord after a fixed time delay.
Hence a one-shot is able to generate a pulse of a particular width following
an input pulse. One-shots are often used in pairs with the output of the first
used to trigger the second. Unfortunately the time relationship between the
signals becomes excessively interdependent and it is better to generate
signal transitions synchronized with the circuit clock.
Registers, Counters, Adders and Displays
The Basic Buffer Register
The most basic storage register uses edge-triggered DFF’s and simply
transfers the values on its input lines to its output lines every time a clock
pulse arrives.
X0
Y0
D
X1
Y1 X 2
D
Q
Q
Y2
D
Q
X3
Y3
D
Q
CLK
X values may change at will until a clock pulse arrives at that time the values
on the X lines are transferred to the output lines, marked Y. Those values
will then be stored on the output lines, no matter what changes occur on the
X lines until the next clock pulse.
Parallel Data Transfer
X0
X1
D
X3
X2
Q
Load X
Y0
Y1
Y2
Y3
Transfer X to Y
Shift Register
A shift Register may be constructed out of JK M/S FF’s. Each FF’s has its
output connected to the next FF in the line.
Serial
input
J
Parallel output
X3
X2
X3
X2
M/S
K
CLK
Each clock pulse the data in the JK FF’s shift to the right by on FF. The
first FF has a NOT gate on its K input to reduce the input line to a one bit
and to ensure that the inputs to the register are always the complement of
one another. Though they transfer data more slowly, shift registers are
useful for the manipulation of data. For example to queue a stack of
instructions and have them leave the register one bit at the time at each
clock pulse.
The shift register above is configured for serial input (SI) parallel output
(PO). Therefore it is called a SIPO shift register. It is possible to
construct parallel input (PI) and serial output (SO) buffers as well. Modern
registers can switch between all the above modes (Faissler 213).
Binary Counters
Circuits are required that are capable of incrementing or decrementing their
output each time that a signal arrives. This will keep a count of total number
of such signals received. We will study a few types of counter circuits
constructed from JK M/S FF’s.
Four Bit Counter
A
Clear
High
J
CLK
Q
B
C
D
High
High
High
High
High
High
M/S
High
K
20
21
22
23
All JK inputs are held at high, which puts the JK M/S FF in the toggle state.
Each time the clock triggers for a given FF its Q output complements. The
binary weighting is shown under each FF. The initial Q states of all the FF’s
are all set to 0 (an e.g. showing why a CLEAR input is useful. The 1st pulse to
arrive at CLKA toggles the state of the first FF so that it changes from 0 to
1. However because JK FF’s are negative edge triggered (as shown by
symbols) nothing happens to QB until the next signal at the CLKA line of the
1st FF. This changes the QA state back to zero producing a negative edge at
the CLK input to the second FF. This changes the QB state of the CLKB on
the 2nd FF to high. That toggles the state of the QA output back to low.
The negative edge on the QA line then toggles QB from 0 to 1. The function
can be summarized in a table. This counter resets to 0000 after 1111.
…. And so on up to 15
A
B
C
D
# of CLK pulses
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
2
3
4
5
6
7
8
…
Ripple Counters
If instead of edge triggered FF’s were used, regular JK FF’s were used then
as soon as the first CLK pulse arrived at CLKA – the output QA would change
from low to high exactly one gate delay later and trigger the second FF at
CLKB. One more gate propagation delay later QB would change and so on.
The changes ripple though the device like a domino effect and hence such
counters are called ripple counters. These will count at a predetermined
rate set by the gate delays and keep counting as long as CLK is high.
However because the counter may read the wrong values while the circuit is
waiting for the signal to propagate through to the output often a more
sophisticated circuit called a synchronous counter is employed.
Synchronous UP Counter
X3
X2
X1
X0
Clear
J
Q
M/S
K
CLK
COUNT
Let COUNT = 1. Clear = 1 sets [X] = 0000. The next CLK pulse sets [X] =
0001. All the Q1, Q2, Q3 were zero to begin with so instead of rippling the
CLK pulse is blocked by the AND gates. The nest CLK pulse sets X [0010]
and the rightmost AND gate allows J1,K1 = 1. FF2 and FF3 still have J = K= 0
and so remain unchanged.
This action is referred to as UP counting the circuit could be configured for
DOWN counting.
BCD Counter
It is also possible to count in the BCD system. This is merely a modification
of the binary count with 0000 following 1001. 1010 through 1111 are not
allowed. One approach to the design of a BCD counter is to detect when
1001 occurs and to disallow bit 1 from changing on the next CLK while forcing
bit 3 to change. Bit 0 changes to 0 as it normally would. Bits 1 and 2 would
normally remain at zero at this time. In this way 0000 will follow 1001.
The nine [1001] detector must sense when bit zero and bit three are 1.
Numbers above nine also share this trait but if the device is functioning
properly, such nmbers will never be reached. A single 2-input AND gate with
bits 1 and 3 as inputs will always have 0 output except when 1001 occurs
(assuming 1010 to 1111 have been disallowed). The implementation looks like:
X3
X2
X1
X0
Clear
J
Q
M/S
K
CLK
COUNT
It is also possible to construct circuits that add numbers together. The
implementation and analysis are not too difficult but due to time constraints
this material will not be covered in class or on the final. Interested readers
are directed toward pg. 221 of the text.
7 segment display
One common display for electronic devices is the 7 segment Led display. It
has 7 segments arranged as follows for displaying numbers (and sometimes
letters):
t
y
u
x
v
z
w
Only 4 binary digits are required to store the numbers from 0-9 that can be
displayed on a 7 segment display. It must have 7 outputs to properly
illuminate the correct segment at the correct time. For digital output
becomes a BCD to 7 segment decoder. For example the number 3 in binary
form is 0011. To display a “3” we must have t,u,v,w and z on and x and y off.
That is 0011 ⇒ tuvwx’y’z. In this manner a truth table can be constructed
and using the design techniques we have previously learned (SOP method,
Karnaugh Maps) a logical expression (and hence a circuit) performing this
function can be implemented.
Operational Amplifiers
Amplifier Basics:
Amplifiers are basic circuit building blocks that transfer an input into an
output via the GAIN. In the simplest sense, this can be depicted
schematically as follows:
input
Amplifier
output
GAIN = output/input
In general, the input can be a voltage or current of any type (DC, AC or
other). If there is no difference in power between the input side and the
output side of the circuit, the circuit is said to be passive and many such
examples with a wide variety of different responses were studied in the
first half of the course. However, because often the power drawn on each
side of the circuit may be different, a more general form of amplifier is the
active amplifier which is more correctly drawn as:
power
input
Amplifier
output
ground
Often the power supply is omitted in schematics but nonetheless op-amps
and other active amplifiers require a power source to function.
Amplifiers can perform a large variety of functions. They may have linear or
non-linear responses to the input – they may have strongly varying frequency
response or may only respond to DC input. Often it is not necessary to
understand exactly what is happening inside the amplifier. The amplifier
may be treated as a black box with only a few quantities characterizing the
function of the amplifier
Basic quantities and concepts:
Voltage Gain:
The voltage gain of the amplifier is the ratio of the
output over the input voltage:
G = vout/vin
Gain normally expressed in decibels. G = 10log(Vout/Vin).
Current and power gain are defined in a similar manner.
For ideal amplifiers, the input and output voltages are
assumed to not to have any bias or offset due to
operational requirements of the amplifier (such as nonzero internal resistance between the leads or non-zero
output for zero input current).
Input impedance: This is the impedance the input signal reacts to when the
amplifier is placed in the circuit. The signal will feel a
load = I2Zin where Zin is the input impedance and I is the
current flowing through the amplifier. If Zin is very high,
then the current is very low and the amplifier does not
draw any current from (and hence change the behaviour
of) the source. Therefore ideal amplifiers have very high
input impedance.
Output impedance: This is the impedance the output signal feels as it
attempts to draw current from the source. It is the
Thevenin equivalent output impedance of the circuitry
within the amplifier. Ideal amplifiers, have very low
output impedance, Zout, allowing the output side of the
circuit to draw power as needed without being affected
by the amplifier.
Frequency
Response:
The performance of an amplifier often changes as a
function of the input frequency. The way in which it
changes is called the frequency response. Amplifier
circuits with a strong frequency response are often
called ACTIVE FILTERS.
Attenuators:
Many amplifiers actually have gains of less than one. The
reduce the magnitude of the input signal. This is called
attenuation and the circuit that do this are called
attenuators.
Differential
Amplifiers:
Responds to difference between input leads. That is the
input leads are 180o out of phase with each other. Also
said to have double – ended input. Some amplifiers have
double – ended output. If one lead (input or output) is
connected to ground, that side of the circuit (input or
output) is said to be single - ended.
FEEDBACK
Many uses of amplifiers involve feeding the output through a network of
resistors, capacitors and sometimes even other amplifiers and back into the
input. This is called feedback.
input
Feedback
Network
Amplifier
output
Feedback can change the output in one of two ways:
Negative feedback:
reduces the output compared to what it would have
been without the feedback.
Positive feedback:
increases the output compared to what it would
have been without the feedback.
Ground:
reference point from which voltages are measured.
Common or earth are synonymous terms. When
two or more ground symbols appear in a circuit,
make sure the intention is that the two points are
indeed at the same electric potential.
Operational Amplifiers
Amplifiers are used for many industrial (usually increasing the power of a
circuit) and scientific (amplifying a weak signal from a scientific instrument)
purposes.
Most amplifiers in use today are built from integrated operational
amplifiers. Operational Amplifiers are high – gain differential input
amplifiers. They are so named because they can be wired to perform
mathematical operations. They were used to construct huge expensive and
buggy analog (as opposed to digital) computers during WWII. Today, solid
state op-amps are small, fast, reliable cheap and widely available in DIP
format at retail electronics outlets.
Symbol for amplifier
Differential input
single-ended output
+
-
Non - Inverting input
Inverting input
output
voltages measured wrt ground
Pinning for 741 – a very common op-amp
Voutput
7
8
6
Offset
null
+15
V
Offset
null
1
5
- +
Most of the newest
electronics are no longer
available in DIP packages.
DIPS are too large, bulky and
capacitive
-15
V
2
3
V-
V+
4
www.vanderbilt.edu/~sloan/els/els.html
The inverting input inverts the input by 180o. For DC inputs this amounts to
inverting the polarity. The non-inverting input leaves the input unchanged.
Gain:
(V+ - V-)A = Voutput
The output is linear with the difference between the two input leads.
The factor between the difference and the output when nothing else is
attached to the amplifier is called the open loop gain and is denoted by the
symbol, A.
From the above equation we see that if
and
(V+ - V-) > 0, then Voutput > 0
(V+ - V-) < 0, then Voutput < 0
Unlike with digital electronics all the significant figures in the input affect
the value of the output. For example, if Voutput > 0 and V- increases, then
the output becomes slightly less positive (or more negative).
The output will be in phase with the input applied at the non-inverting input
and it will be 180o out of phase with the input applied at the inverting input.
Ideal vs. real op-amps
An ideal op-amp would have a very high gain, A → ∞. The 741 has an open
loop gain of 103 dB. Because stability is difficult to maintain for very high
gains, values typically range between 60-120 dB for standard op-amps. Many
op-amps today do not have huge gains because it is very difficult to achieve
stability and it is up to the designer to access the data sheet in order to:
a)
use the recommended values of resistance for achieving fixed gains
b)
use the formula the data sheet gives for achieving a specific gain
c)
go from scratch (e.g. at frequencies > ~10 MHz)
Input impedance is infinite for an ideal op-amp. For a 741 the value is 2 MΩ.
Some op-amps range up to 106 MΩ. This value is affected by all the circuitry
on the input side of the circuit – therefore it can be changed where it is not
suitable. Output impedance = 0 for an ideal op-amp.
Input bias current is the current that flows into input lines during normal
operation of the op-amp. This current will be the net current flow through
the input side. Ideally this value will be zero. For the 741 the currently
typically ranges around 0.1 µA and some op-amps have values down to 10-14 A.
Output impedance will be zero in an ideal op-amp. Practically it depends on
the application for which the op-amp is intended. Low power op-amps tend
to have higher output impedances – about a few kΩ. High power op-amps will
be much lower – less than 1 Ω. The 741 has an output impedance of 75 Ω.
Input offset voltage is the voltage that must be applied at the inputs to
produce a zero output. Ideally this will be zero. For the 741 the input
offset voltage is 2 mV. This value is too large to ignore – therefore the 741
(and many other op-amps) have inputs through which adjustments may be
made to “null” the op-amp. Once the op-amp has been “zeroed” for a
particular set-up, then it the input offset voltage will effectively be zero as
long as external conditions (such as temperature) do not change. Because in
real operation, external conditions are often changing – the stability of the
null setting becomes important.
The slew rate is the maximum rate at which the output may change. Ideally
this value would be infinite. For the 741 the slew rate is 0.5 V/µs. Op-amps
with slew rates of over 100 V/µs exist.
The Basic Inverting Amplifier Circuit
The most basic way to configure an op-amp is shown below:
Rf
R
i2
Vin
i1
V-
i3
+
i2
Vout
The non-inverting input is connected to ground (0 V), the signal is fed
through the inverting input via a resistor, R and the output feeds back to
the inverting input through a resistor Rf. We shall show that the feedback
has the effect of reducing the output and hence is negative feedback. The
voltage at the inverting input (relative to ground) is V-.
Analysis:
Kirchoff’s current law applied at the junction just after the input resistor
(often called the summing point for this reason), R yields:
i1 = i 2 + i 3
Applying Ohm’s law to resistor R:
i1 = (Vin – V-)/R
And to
i2 = (V- - Vout)/Rf
Rf:
The open loop gain is A ≡ -Vout/V-. The minus sign appears because V- is
applied at the inverting input. From this we get:
V- = -Vout/A
Subbing in for i1 and i2 using the expressions above we can write:
(Vin – V-)/R = (V- - Vout)/Rf + i3
Replacing V- with -Vout/A, we can further write:
(Vin + Vout/A)/R = -(Vout/A + Vout)/Rf + i3
Vin/R = i3 -Vout[1/(AR) + 1/(ARf) + 1/Rf]
Solving for Vout for the final answer:
Vout =
i3
Vin /R
−
1/Rf + 1/(AR) + 1/ARf 1/Rf + 1/(AR) + 1/ARf
This is the general answer involving no assumptions about the ideality of the
op-amp. If we assume that the op-amp is ideal, then
1)
i3 = 0 (the input bias current =0 in ideal op-amps) and so from
Kirchoff’s current law i1 = i2. The first term above → 0.
2)
The open loop gain, A → ∞. All terms with A in denominator go away.
The resulting expression gives:
Vout =
i3
Vin /R
−
1/Rf + 1/(AR) + 1/ARf 1/Rf + 1/(AR) + 1/ARf
0
0
0
⇒ Vout = -Vin(Rf/R)
The CLOSED LOOP GAIN = G = Vout/Vin = -Rf/R, is INDEPENDENT of the
open loop gain of the amplifier. A 100 dB gain corresponds to:
100 dB = 10log(Vout/Vin)
1010 = Vout/Vin
This is a very large number, hence the ideal amplifier approximation is good.
The result of the feedback is that Vout is reduced in magnitude by a factor
(Rf/R) when Rf < R. That is the feed back in this case is negative.
Note that the infinite gain approximation is the same thing as saying Vout/V= infinity or V- = 0. That is the inverting input is AT GROUND. Therefore
this approximation is often called the VIRTUAL GROUND approximation.
In the future when we analyze op-amp circuits we will skip the “real” analysis
and proceed directly to the “ideal” analysis. As an example we will redo the
above analysis assuming immediately that i3 = 0 and V- = 0.
Immediately we get:
i1 = i2 ⇒
Vin/R = -Vout/Rf
and the results from above follow immediately.
When does the ideal amplifier approximation break down?
1)
When the rate at which the input changes requires that the output
must change faster than the slew rate for the op-amp.
2)
Saturation - When the output voltage exceeds the voltage limits for
the op-amp.
Analysis in these two cases is difficult. Usually it is not required however
since circuit designers take care to avoid operating past these limits.
Frequency Response of op-amps
A data sheet for an op-amp such as the 741 will include a Bode Plot indicating
the open loop gain and the phase shift as a function of frequency. These will
be for the op-amp on its own.
Open Loop phase shift ϕ
in degrees
These look like (pg. 494 Faissler):
100
Voltage gain (dB)
80
60
40
20
0
90
45
0
-45
-90
-20
1
10
6
5
7
102 103 104 10 10 10
Frequency (Hz)
1
10
6
5
7
102 103 104 10 10 10
Frequency (Hz)
The flat area in the Bode plot for the gain indicates the region over which
the ideal assumptions for amplifiers are valid. After about 10 Hz the gain
falls of at about 6 dB per octave.
If a negative feed back network is used the op-amps performs ideally over a
much larger frequency range. For example, if the op-amp is configured as
an inverting amplifier as shown above with Rf and R chosen suitably. Now the
gain will look like:
100
Voltage gain (dB)
80
Loop
gain
60
Open loop gain
Closed loop gain
40
20
0
-20
1
10
6
5
7
102 103 104 10 10 10
Frequency (Hz)
The frequency response of the closed loop amplifier is much flatter (i.e.
better) than that of the amplifier by itself. At low frequency the ideal
assumption will hold. In the region where the red curve drops ideal
assumptions are not valid.
Examples of feedback mechanisms: cruise control, thermostats, that loud
squeal that is heard when the microphone is too near the speaker in a sound
system. Which are examples of positive feedback? Which are negative?
Would positive feedback ever be desireble?
(do it yourself comparator – certainly an op-amp oscillator? ASK Christian
about these examples.
Basic Operational Amplifier Circuits
Operational amplifiers are so named for their use in the computation of
mathematical operations. We will now study a variety of methods on
configuring op-amps to perform a number of different functions.
The Basic Inverting Amplifier Circuit
R
+
Vin
Rf
Vout
Analysis: We analyzed this circuit previously. We found that: Vout = Vin
(Rf/R). That is the closed loop voltage gain = (Rf/R).
Limitations: The input impedance = Rin = R. The only limitations are that R
must not be so large that the input current is not smaller than the input bias
current (i.e. the minimum current required for the operation of the op-amp)
usually on the order of 10-6 A. Rf cannot be so small that the output power
(current * voltage) exceeds the maximum power output of the op-amp.
A Better Inverting Amplifier Circuit
R
+
Vin
Rg
Rf
Vout
This circuit also functions as an
inverting amplifier with
Vout = Vin(Rf/R). If the new
resistor, Rg = RfR/(Rf + R), the
effects of the input bias
current are almost eliminated.
Non-Inverting Amplifier Circuit – Voltage divider
+
-
Vin
Vout
i2
R2
Therefore:
VB
if
R1
Gain: For ideal op-amps: Vin = V- and if = 0. By
inspection we see that V- = VB. Therefore Vin
= VB. Using Kirchoff’s current law and if = 0,
we get i1 = i2 = i.
and
Vin = VB = iR1 ⇒ i = Vin/R1
Vout = iR2 + VB
= i(R1 + R2)
= (Vin/R1)(R1 + R2)
i1
Vout = Vin(1 + R2/R1)
Input impedance: Zin = Vin/iin
Voltage across input leads = e = (V+ - V-) = (iin)(ri).
Open loop gain = A ⇒ Vout = Ae ⇒ Vout/A = e
Vin
+
Vout
ri
iin
-
R2
From above Vout = Vin(1 + R2/R1)
⇒ e = (Vin/A)(1 + R2/R1)
⇒ e/ri = iin = (Vin/(riA))(1 + R2/R1)
R1
⇒ Zin = Vin/iin = Vin/[(Vin/(riA))(1 + R2/R1)]
=riR1A/(R1 + R2) → ∞ in ideal limit
Output impedance:
e
+
-
io
ro
R2
R1
Output impedance, Zout, found by grounding input and
applying voltage V to output.
i = i2 – i0
V
i2 = V/(R1 + R2)
i2
i0 = (Ae – V)/r0
e = -i2R1 = -VR1/(R1 + R2)
i0 = (1/r0)AVR1/(R1 + R2) – V/r0
i
i = i2 – i0 = V/(R1 + R2) + (1/r0)AVR1/(R1 + R2) + V/r0
i=
Vr0 + AVR1 + V (R1 + R2 )
r0 (R1 + R2 )
Zout = V/i =
r0 (R1 + R2 )
r0 + AR1 + (R1 + R2 )
in ideal limit
Voltage Follower Circuit
Vin
+
Gain: Vout = Vin.
ri
-
r0
Vout
Input impedance:
Take (R1 and R2→ 0) limit of input impedance
Zin = Ari
Output impedance:
Take (R1 and R2→ 0) limit of output impedance
Zout = r0/A
Function: This circuit acts as a buffer and impedance transformer. Though
the voltage gain = 1, power can be at amplified to power limit of the op-amp.
The Summing Amplifier Circuit
i1
if
V1
i2
V2
i3
V3
R1
R2
+
Rf
Vout
The conjunction where the
three input currents meet
is called the summing point.
For ideal op-amps, we can
the voltage at the summing
point = 0 (same as the
ground – ie virtual ground).
R3
Calculation of the gain (ideal – input bias current assumed to be zero):
i1 + i2 + i3 = if
Using virtual ground approx. at summing point, if = -Vout/Rf, i1 = V1/R1, and
etc.. Sub. in 1st equation:
Vout = (Rf/R1)V1 + (Rf/R2)V2 + (Rf/R3)V3 a weighted sum.
Function: If all resistors are equal: Vout = V1 + V2 + V3
SUM
The Difference Amplifier Circuit
V1
R1
+
V2
R1
R2
Vout
Note that the two
resistors at the input
leads must have the
same value for this
circuit to function
properly.
R2
Calculation of the gain (ideal – input bias current assumed to be zero):
The (current through R1) = (current through R2) so the voltage at the noninverting is:
Current through R1 = V2/(R1 + R2) = V+/R2 = current through R2
Re-arranging to solve for V+ = V2R2/(R1 + R2).
At the inverting input:
[A]
(V1 – V-)/R1 = (V- - Vout)/R2
However, for ideal op-amps V+ ≅ V- so:
(V1 – V+)/R1 = (V+ - Vout)/R2
Subbing in for V+ using expression [A]:
(V1 – V2R2/(R1 + R2))/R1 = (V2R2/(R1 + R2) - Vout)/R2
V1/R1 – V2(R2/ R1)/(R1 + R2) = V2R2/(R1 + R2) - Vout/R2
Vout/R2= V2(1 + R2/ R1)/(R1 + R2) - V1/R1
Vout/R2= V2/ R1 - V1/R1
Vout = (R2/R1)(V2- V1)
Function: When R2 = R1 this is clearly a difference operation.
Calculation of the gain (ideal):
The Current to Voltage Converter
If
+
Iin
Rf
Ohm’s law:
(V- - Vout)/Rf = If
Ideal op-amp:
V- = 0, If = Iin
Result:
Vout = IinRf
Vout
Function: The input is explicitly a current and the output is a voltage. Many
of the above circuits could function as a current converter. It depends on
the point of view.
The Constant Current Source
+
Vin
VB
i2
Load
R2
Vout
Calculation of the gain (ideal):
i1
Ideal op-amp:
Vin = VB, i1 = i2
Ohm’s law:
i1 = i2 = VB/ R2 = Vin/R2
Result:
i1 = Vin/R2
Function: The current through the load, i1, is
independent of the load. Therefore, the circuit
represents a constant current source. Note
the power Vin/R2 requirements of the load cannot
exceed the capabilities of the op-amp or the
above analysis is not valid.
The Integrator
i2
R
vin
+
i1
Cf
vout
Calculation of the gain (ideal):
Ideal op-amp:
Ohm’s law:
⇒
i1 = i2, V- = 0
vin/R = i1 = i2 = -Cf[d(vout)/dt]
⇐ I-V relation for Capacitor
Assume that vout = 0 at t = 0
Result:
vout = −
t
1
vin dt
RCf ∫0
Function: The output voltage is the time integral of the input voltage. Note that for
PURE AC input, the capacitor can be treated as a simple impedance.
vout = -vin(Zf/Z) = -vin(-j/(ωC))/R = jvin/(ωCR)
Gain = vout/vin = j/(ωCR)
and the circuit behaves as a simple inverting amplifier OR in the frequency domain as an
active low pass filter. Note that this is because the integral of a sinusoidal function is
a still a sinusoidal function. A difficulty encountered in application is that the small
effects of the input bias current also get integrated throwing this circuit farther out
of true as time progresses. Ultra stable op-amps or some low frequency (these effects
l l ) filt i
t f thi
The Differentiator
i2
C
vin
Rf
+
i1
vout
Calculation of the gain (ideal):
Ideal op-amp:
i1 = i2, V- = 0
I-V relation for Capacitor: ⇒
i1 = -C [d(vin)/dt] = vout/Rf = i2 ⇐ Ohm’s law
Result:
vout = -Rf C[d(vin)/dt]
Function: The output voltage is the time derivative of the input voltage. Note that for
PURE AC input, the capacitor can be treated as a simple impedance.
vout = -vin(Zf/Z) = -vinRf/(-j/(ωC)) = jvinRfωC
Gain = vout/vin = jRfωC
and the circuit behaves as a simple inverting amplifier OR in the frequency domain as an
active high pass filter. Note again that this is because the integral of a sinusoidal
function is a still a sinusoidal function.
Nonlinear amplifiers
We complete the catalog of basic mathematical operations with a brief
description of non-linear amplifiers. We will learn more about the diodes
used in such circuits later (see Chapter 41 of text). For now we will except
that the V-I relationship for a diode is exponential.
i2
R
vin
Rf
+
i1
vout
Calculation of the gain (ideal):
Ideal op-amp:
i1 = i2, V- = 0
Ohm’s law ⇒ i1 = vin/R = Bexp(vout/α) = i2 =
Result:
⇐ I-V relation for diode:
vout = -αln(vin/(RB))
Function: The output voltage is related to the logarithm of the input voltage. If the
diode were on the input lead, then the output of the circuit would be proportional to the
exponential (or antilogarithm) of the circuit. See the similar inverse relationship
between the differentiator and integrator above. Together the log and antilog circuits
can be used to construct a circuit for multiplying two numbers:
VA
log
Sum
VB
log
Exp
VA*VB
Many other simple
mathematical operations
(division, reciprocals etc.)
are possible with similar
circuits but are beyond the
scope of this course.
Introduction to Semiconductors and diodes
SEMICONDUCTORS
In the past we have discussed insulators and conductors. We have seen how
to calculate their resistance and have seen that though a perfect conductor
does have some resistance, the value is so low that it is zero to a good
approximation. Similarly for insulators their resistance is very high and
easily calculated.
A brief review is helpful:
•
A conductor has many free electrons (~8.0 × 1028 conduction e-/m3). The
valence electrons are loosely bound. (ρ ~ 10-8 Ωm)
•
An insulator has very few free electrons. The valence electrons are
tightly bound. (ρ ~ 1011 Ωm)
•
In semiconductors, valence electrons are bound with intermediate
strength. Therefore, the number of free electrons can be varied by
changing external conditions (e.g. temp. or applied V). (ρ ~ 10-6 – 10-4Ωm)
A semiconductor is a material whose resistance depends strongly on the
applied voltage and temperature.
Temperature dependance
Ohmic
semiconductor
superconductor
insulator
ρ
ρ
ρ
conductor
T
T
Semiconductors are not Ohmic materials.
The are two types of semiconductors: Intrinsic and Extrinsic
T
INTRINSIC SEMICONDUCTORS
Common semiconductors such as germanium and silicon lie in the 4th column
of the periodic table (like carbon). Semiconductors form crystals. Each
atom in the crystal has four valence electrons that it may share with four
neighbours to form a filled (↑↓ paired electrons) bonding orbital. A two
dimensional representation of there 3-dimensional (tetrahedral) structure
might look like.
Atomic core
Bonding ↑↓
electron pair
The bonding orbitals do not move around because the crystal structure (and
hence the position of the atomic cores) is fixed. However, individual
electrons may switch from orbital to orbital depending on how tightly bound
the electrons are to the atomic cores. For germanium and silicon atoms, the
valence electrons are bound with energy approximately equal to their
average kinetic energy at room temperature. This means that at room
temperature some small fraction of the bonding electrons will have shaken
free of their parent atoms. Even just 1 in a billion will add up to a very large
number for the large number of atoms present (~NA).
Free electron
Hole
Even though the above configuration has slightly potential higher energy
than the “perfect” crystal – the system prefers this configuration to the
perfect crystal because it is less ordered and the kinetic energies of the
electrons is sufficient at temperature to achieve this configuration.
Note that the number of holes, nh = ne, the number of free electrons
because in a pure semiconductor the every free electron created leaves
behind a hole.
If an electron and a hole ever meet, the electron will occupy the hole and
the charges will cancel out. This process is happening at all times in the
semiconductor. However it is balanced by the fact that new holes are being
created at all times by thermal excitations. The rate at which the holes
recombine (which in the steady state = the creation rate of holes) turns out
to be proportional to the product nenh (because a two body collision is
required). Therefore:
nenh = creation rate of holes
Statistical mechanics (adv. physics) tells us that the creation rate of holes
is related to the amount of energy required to create them = ∆ui (= a
constant for a given material) and the temperature as follows:
Rate of hole production ∝ exp(-∆ui/kT)
where k = Boltzmann’s constant
Therefore the product nenh is equal to the above expression multiplied by a
constant, C:
nenh =C exp(-∆ui/kT)
Therefore we see at T = 0, there will be no charge carriers. As T goes up
the number of charge carriers increases exponentially.
Once created, the free electron is free to move around in the crystal. So is
the hole. The atomic cores do not move, just the electrons. If the atom
with the hole borrows an electron from the atom next door, the position of
the hole moves. Therefore both holes and free electrons may carry current.
Under the influence of an electric field the electrons and holes will continue
to bounce about at random but tend to move in opposite directions due to a
net drift velocity. This is where the force on the charge caused by the field
is balanced by the “drag” caused by collisions with the atomic cores.
Though considerably simplifies (no Quantum Mechanics) these arguments can
be used to explain why germanium and silicon are semiconductors and
diamond is not. To some extent they also can help one to understand
insulators and conductors.
Semiconductors that behave as described above are called INTRINSIC
SEMICONDUCTORS, because their conductivity depends on the inherent
properties of the material. Their behaviour at room temperature is far
more interesting than that of conductors and insulators, however, there are
too few charge carriers in a pure semiconductor for their properties to be
useful on their own. If a small amount of impurity is added, the properties
can change dramatically. Intrinsic conductors with impurities are called
EXTRINSIC SEMICONDUCTORS.
EXTRINSIC SEMICONDUCTORS, n-type and p-type
n-type:
If a small (1 part per million or less) amount of impurity (As, Pb,
Sb) having five valence electrons is added to a common semiconductor such
as silicon, the following situation initially results.
Extra electron
impurity
Bonding ↑↓
electron pair
impurity
-ve charge
Free e-
The extra electron is not very tightly bound to the impurity so it will move
around and leave behind a positively ionized core. Typically this ionic core
does not have a strong ability to bind electrons and remains fixed in place.
The end result is that a mobile electron has been created without creating a
hole. These extra charge carriers increase the conductivity by a factor of
about 1000 at room temperature. Since there are more electrons than holes
ne ≠ nh and the majority carrier (electrons) is negative. Therefore this type
of extrinsic semiconductor is called an n-type semiconductor.
p-type:
If a small (1 part per million or less) amount of impurity (Al)
having three valence electrons is added to silicon, the following situation
initially results.
hole
impurity
The hole moves around and leaves behind a negatively ionized core which
remains fixed in place. There are more holes than free electrons again ne ≠
nh and the extra charge carriers increase the conductivity by a factor of
about 1000 at room temperature. Since the majority carrier is positive this
type of extrinsic semiconductor is called an p-type semiconductor.
For both n-type and p-type semiconductors a quantum mechanical treatment
of the problem shows that the concentration of charge carriers follows the
same behaviour as intrinsic semiconductors:
nenh =C exp(-∆ui/kT)
Therefore in a p-type semiconductor with many holes, the number of
electrons must drop to near zero for the product to remain constant. If a
number of minority carriers, (in this case electrons) are injected into the
semiconductor, they will quickly recombine with the holes and disappear.
pn junctions
Consider a block of n-type semiconductor bonded to a p-type semiconductor
so that there is no irregularity in the underlying perfect crystal structure
across the interface
When the junction is formed, free charge carriers can drift the across the
junction into the other type of semiconductor. In particular holes from the
p-type semiconductor drift into the n-type, recombine with the majority
carriers on that side (electrons) and vanish. Similarly across the junction
electrons from the n –type drift into the p-type, recombine with holes and
vanish. While this diffusion occurs there is a net conventional current
across the interface from the p-type into the n-type.
Each hole that crosses the interface leaves behind a negative ion fixed in
place that cannot move. Similarly each electron that diffuses leaves behind
a positive ion. As time passes a growing amount of charge accumulates on
each side of the junction. This charge establishes an electric field. This
electric field increasingly opposes the continuation of the diffusion process
until finally the process stops at some equilibrium value that depends on the
intrinsic material but not the doping material.
On average the charges nearest to the interface are the first to cross.
Therefore this charge accumulates near the junction and is called the dipole
layer.
Formation of a pn-junction
p-type
p-type
n-type
Charge density
Bonding
n-type
x
Diffusion
And
Recombination
-
+
-
+
-
+
Electric field
Potential
difference
V
x
The final value of the voltage that results depend on the material the
semiconductors are made from but not on the doping material. At room
temperature this potential difference ∆v is roughly:
∆v = 0.3 V for germanium
∆v = 0.7 V for silicon.
The establishment of this electric field across the junction sweeps charge
carriers away, creating a depletion zone. The depletion zone is a few
microns thick and represents a barrier to the flow of charge with voltage
dependant properties. A pn-junction is also called a diode. The symbol is:
p-type
n-type
The behaviour of a diode in an electrical circuit
Consider the following arrangement:
FORWARD BIAS
Before the battery is even hooked up we saw earlier that negative charge
had accumulated in the p-type semiconductor on the left side of the diode.
The positive pole of the battery causes positive charge to flow and
accumulate on the left side of the junction. Similarly negative charge flows
from the negative pole of the batter and accumulates on the right side.
These charges counteract the charges in the depletion zone. Eventually (a
few nanoseconds or less), enough charge accumulates to counteract all the
charge present in the depletion zone and the potential difference across the
junction is reduced to zero. The time this takes is called the switching time.
Current then flows across the pn-junction in the diode up to the current
limit of the diode. This arrangement is called FORWARD BIAS.
Consider the following arrangement:
REVERSE BIAS
Before the battery is even hooked up we saw earlier that negative charge
accumulates in the p-type semiconductor on the left side of the diode. The
positive pole of the battery causes positive charge to flow and accumulate on
the right side of the junction. Similarly negative charge flows from the
negative pole of the batter and accumulates on the left side. These charges
add to the charges already in the depletion zone. Eventually (a few
nanoseconds or less), enough charge accumulates to counteract the
electromotive force of the battery and charge stops flowing (sort of like a
capacitor). Current then stops flowing at all and at no time in the process
has any current flowed across the pn-junction in the diode. This is called
REVERSE BIAS.
A FORWARD BIASED DIODE HAS P hooked up to POSITVE
Therefore the ideal I-V behaviour for a diode is:
Infinite impedance
I
zero impedance
V
Reverse bias
Forward bias
Real Diodes
There is no such thing as a perfect conductor. Therefore a real diode will
not have an infinite current when biased in the forward direction. There is a
limit to the number of available charge carriers at any given temperature
and this will dictate the current at that temperature. Furthermore the flow
of current dissipates energy in the diode and at some maximum current this
amount of energy will exceed the capabilities of the diode. This is called
burnout.
Similarly there is no such thing as a perfect resistor. Under reverse bias
the presence of small amount of the wrong type of impurities causes a small
amount of current to flow when ideally none should flow. This is called
reverse saturation current, Is. It can be reduced by using ultrapure
semiconductors. Another source of reverse saturation current is the
thermal creation of electron-hole pairs in the depletion region. Nothing can
be done about that except running at low temperatures. Furthermore as the
reverse bias voltage is increased, at some point the voltage will be sufficient
to rip the fixed ions in the depleted region loose. This will destroy the pnjunction and hence is called the breakdown voltage.
Therefore the ideal I-V behaviour for a diode can be contrasted with
ACTUAL behaviour:
burnout
I

 qV  
I = IS exp
 − 1
kT
 


Breakdown
voltage
Reverse
saturation
current
V
Turn on
voltage ~ 0.3 V
for Ge diode
at room
temperature
Turn on for
same diode
at higher T
Diode types
Switching diode: low power – combined with resistors to form logic gates –
engineered for fast switching time small.
Rectifiers: high power- engineered for DC to AC conversion – see chapter
38 of Faissler for details. Can be quite large. Engineered to dissipate power
and not breakdown, burnout or overheat.
Light emitting diode: LED’s are made of exotic material that emit light
while conducting. Ubiquitously used as indicator lights in all kinds of
electronic devices. Medium power (1.6 V and 10 mA). There are lasing
versions of this now used to make very compact media scanners (eg CD
players).
Photodiode: Complement of LED - turns light into current. Reversed bias –
charge carriers that conduct electricity are created in depletion zone
whenever light hits the depletion zone. Used in light sensors, and now arrays
of them used in the CCD’s of digital cameras and scientific equipment.
Zener diode: Diode with a well defined reverse bias breakdown voltage.
Instead of overheating and destroying itself, a Zener diode will simply let all
current through if the maximum reverse bias is exceeded. Useful as a
voltage reference and regulator and to avoid burnout in many applications.
I-V curve for Zener diode.
I
V