Distributed On-Chip Power
Regulators and Decoupling
Capacitors
Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester
Department of Electrical Engineering
Technion – Institute of Technology
Voltage
Delivering Power On-Chip
Off-chip
converter
Unregulated
high
Regulated
voltage
voltage at
required
level
Board
Package
Unregulated
high
Regulated
voltage
voltage at
required
level
Voltage on-chip
Chip
Package
Board
Off-chip
converter
Voltage
Delivering High Quality Power On-Chip
Off-chip
converter
Unregulated
high
Regulated
voltage
voltage at
required
level
Board
Package
Unregulated
high
Regulated
voltage
voltage at
required
level
Voltage on-chip
Chip
Package
Board
Off-chip
converter
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management

Future research

Summary
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

From power plant to integrated circuit

Power delivery architectures

Heterogeneous power delivery management

Future research

Summary
Electricity – From Power Plant to House
120 V alternating
current (AC)
Power plant
Step-up
transformer
120 V
155 kV – 765 kV direct
current (DC) or AC
Transmission lines
120 V
Step-down
transformer
<10 kV
Local distribution lines
120 V
Electricity – From House to Computer Board
On-board
On-board
power
power supplies
supplies
Intel Skulltrail motherboard – D5400XS - 2009
Electricity – From Board to Integrated Circuit
Toshiba HD decoding chip – 2011
25 power domains
Toshiba – HD decoding chip – 2011
Electricity – From Board to Integrated Circuit
Samsung Exynos 4 Quad Core – 2012

Quad core application processor

32 nm




High-k metal gate
Over 1.4 GHz per core
Separate power management IC

Nine buck converters

28 LDOs
Dynamic voltage and frequency
scaling (DVFS)

6.25 mV step size
Samsung Exynos 4 Quad Core – April 26, 2012
Power Management – Adaptive Power Supply

Suffers from low power
efficiency
 41% to 93%
 Switched capacitor
regulator

Centralized power management controller

Hybrid power supply
 Buck converter and switched capacitor regulators
*G. Patounakis et al., “A Fully Integrated On-Chip DC-DC Conversion and Power Management System,”
IEEE Journal of Solid-State Circuits, March 2004.
Columbia University
Dynamic Voltage Scaling (DVS)

On-chip power
management area


0.36 mm2
Centralized control

Far from the load

Slow transient
response
Realtek Semiconductor

Power management with low power PWM and high
efficiency pre-regulator

Off-chip inductor (4.7 µH) for the pre-regulator
Y. H. Lee et al., “A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System,”
IEEE Journal of Solid-State Circuits, November 2010.
Software Controlled Power Management –
Intel SpeedStep Technology

Software controlled power management

Centralized hardware

Voltage ramp rates are controlled

Dynamically change frequency of PLLs by changing input voltage
N. A. Kurd et. al., "Westmere: A family of 32nm IA processors,"
IEEE International Solid-State Circuits Conference, February 2010.
Intel
Full On-Chip Power Management –
65 nm CMOS Cellular Handset Chip

Buck converter with ten LDOs

~ 0.9 mm2

85% power efficiency

Centralized power management
and power supplies

Far from load circuits

Higher power noise
ST Electronics
A. J. D`Souza et al., “A Fully Integrated Power-Management Solution for a 65nm CMOS Cellular Handset Chip,”
IEEE International Solid-State Circuits Conference, February 2011.
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

From power plant to integrated circuit

Power delivery architectures

Background and issues

Separation of power conversion and regulation

Heterogeneous power delivery management

Future research

Summary
Active Power Supplies – Circuit Examples
Power supply
Power converter/
regulator
(stable and low)
(noisy and high)
Linear
LDO
Power supply
Switched
Capacitor (SC)
Series-parallel
Switching
(SMPS)
Buck
Switching vs. Linear Power Supplies
E. Salman and E. G. Friedman, High Performance Integrated Circuit Design, McGraw-Hill Publishers, 2012.
Off-Chip Power Delivery – Past
Vdd1
 Off-chip power
converters

Vdd3
Vdd2
Vdd4
Off-chip power converters

Parasitic effects



Resistive IR drop
Inductive L di/dt noise
High number of I/O pins
On-Chip Power Delivery – Present
Vdd1
 Off-chip power
converters

Vdd3
Vdd2
Vdd4
On-chip power converters


Parasitic effects eliminated
Smaller converters required
Active vs. Passive Power Supplies

Exploit distinctive properties of decoupling capacitors and power supplies
V. Kursun and E. G. Friedman, Multi-Voltage CMOS Design, Wiley, 2006.
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

From power plant to integrated circuit

Power delivery architectures

Background and issues

Separation of power conversion and regulation

Heterogeneous power delivery management

Future research

Summary
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management


Design complexity
Design solutions

Future research

Summary
Hierarchy of Power Delivery System
On‐board (off‐chip) Power supplies
power supplies
in package (PSiP)
On‐chip power supplies
+
–
Board
Package

On-chip power delivery is not one-dimensional

Highly complicated power delivery system


Off-chip/in-package power converters

On-chip power regulators and decoupling capacitors
Power noise analysis

Computationally complex

Significant memory requirement
R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Köse, and E. G. Friedman,
Power Distribution Networks with On-Chip Decoupling Capacitors, Second Edition, Springer 2011.
Interactions of Power Supplies and Power Grid
Architectural interactions within
off-chip and on-chip power supplies
Off-chip
Physical interactions within on-chip
power supplies and power grid
LDO
On-chip
Decap
Load
Off-chip power
converters
I/O
interface
Distributed
on-chip LDOs
Voltage
islands
Physical Design Complexity
Distribution of Regulators and Decaps with On-Chip Loads

Several power distribution networks

Hundreds of on-chip linear regulators

Thousands of decoupling capacitors

Billions of load circuits
Load
Decap
Power
regulator
Architectural Clustering of Power Supplies
Off-chip
Off-chip power
converters
On-chip
I/O
interface
Distributed
on-chip LDOs

Tens of off-chip
switching converters

Hundreds of on-chip
linear regulators

Multiple power grids

Billions of load circuits
Voltage
islands
I. Vaisband and E. Friedman, "Methodology for Energy Efficient Distribution of On-Chip Power Supplies,"
IEEE Transactions on Power Electronics (in press).
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management


Design complexity
Design solutions

Future research

Summary
Design Solutions for Heterogeneous Power Delivery System
Delivering power to complex ICs is a fundamental bottleneck
Models
Algorithms
Closed-form expressions for
effective power grid resistance
Fast algorithms for power
grid analysis
Co-design methodology
Circuits
Ultra-small
point-of-load
voltage regulator
Off-chip
converters
On-chip
regulators
Decoupling
capacitors
considering
Power
High
3-D
efficiency
regulation (low noise)
integration
Architecture
Topologies for on-chip
and off-chip co-design
of power supplies
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management


Design complexity
Design solutions




Circuits
Models
Algorithms
Architecture

Future research

Summary
Active Filter Based Converter

Rochester, Eastman Kodak, and TSMC

110 nm CMOS technology

Voltage reference is replaced with active filter



Simple design

Low quiescent current
Ultra-small voltage regulator

0.015 mm2 on-chip area

Suitable for on-chip distribution
–
Fast response time
Op-amp
Active filter
+
Active Filter Based Converter - Feedback
Feedback
C2
Vdd1 R1
R2
Op-amp
R3
PWM
C1
C3
Vdd2
Load Circuits
Test Circuits
Output test pad
PWM
Op amp
Passive
Components

Opamp
Output
stage
Five different test circuits have been fabricated

Three circuits with internal PWM module to provide input signal

Two circuits with input signals supplied from off-chip signal generator
Performance Summary

Proposed regulator provides smallest area, fast
response time, and low quiescent current
S. Köse, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, “An Area Efficient On-Chip Hybrid Voltage Regulator,”
Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED), March 2012.
S. Köse, S. Tam, S. Pinzon, B. McDermott, and E. G. Friedman, “Active Filter Based Hybrid On-Chip DC-DC Converters
for Point-of-Load Voltage Regulation," IEEE Transactions on Very Large Scale Integration (VLSI) Systems (in press).
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management


Design complexity
Design solutions




Circuits
Models
Algorithms
Architecture

Future research

Summary
Effective Resistance Model
k*r
r

Infinite semi-uniform
two layer mesh

Models power or ground
network

Effective resistance
between arbitrary points
within power grid
A
(x1 ,y1 )
B
(x2 ,y2 )

IR drop analysis
Exact solution* 
Asymptotic solution* 
* S. Köse and E. G. Friedman, "Effective Resistance of a Two Layer Mesh,"
IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 58, No. 11, pp. 739 – 743, November 2011
Simplified Model of Power Grid Interactions
Il  idl  ipl
 Physical separation affects
current supplied from
– Power supplies
– Decoupling capacitors
35
d 2Vc (t )
dVc (t ) 
dVc (t )

ipl  Rpl  Lpl
 CLvd
  CRvd
dt 
dt
dt 2

idl 
dVc (t )
Rvd  Rdl  Lvd  Rdl 
dt
M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman, “Effective Radii of On-Chip Decoupling Capacitors,”
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, pp. 894-907, July 2008
Flow of Presentation

Power delivery yesterday, today and tomorrow

Heterogeneous power delivery management


Design complexity
Design solutions




Circuits
Models
Algorithms
Architecture

Future research

Summary
Fast Algorithms for Power Grid Synthesis

Efficient algorithms to
estimate IR voltage drops

Significantly faster than
existing techniques

IRnode1 
Non-iterative
1 m
1 n


I
I
R
R
R




.  Rsn (1)  Rsl ( i )  Rnl ( i )  



sn (1)
sl ( i )
nl  
i 1  load ( i )
i  2  supply( i )
2
2
S. Köse and E. G. Friedman, “Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality,”
Proceedings of the IEEE/ACM Design Automation Conference, June 2011.
S. Köse and E. G. Friedman, “Efficient Algorithms for Fast IR Drop Analysis Exploiting Locality,”
Integration, the VLSI Journal, Vol. 45, No. 2, pp. 149-161, March 2012.
Power Supply and Decoupling Capacitor Co-Placement

 ISPD benchmark circuit
 Superblue18
 483,452 individual blocks
 Power grid
 ~ 400 horizontal lines
 ~ 380 vertical lines

Where should power supplies and
decoupling capacitors be placed?
Characteristics of decoupling
capacitors and power supplies
►
►
Spatial location
Output impedance
►
►

Maximum current
Characteristics of load circuits
►
►

Response time
Spatial location
Current demand
Characteristics of power network
►
Parasitic impedances
N. Viswanathan et al., "The ISPD-2011 Routability-Driven Placement Contest and Benchmark Suite,"
Proceedings of ACM International Symposium on Physical Design, March 2011.
Benchmark Circuits – SuperBlue5
# of blocks
Power grid size
# of nodes in the power grid
95,041
774 X 713
551,862

# of PS
# of Decaps
Case 1
1
2
Case 2
1
10
Case 3
3
10
Case 4
3
20
Case 5
20
32
Map of voltage drops for superblue5
 Smaller voltage drop with distributed power delivery system
Benchmark Circuits – SuperBlue10
# of blocks
Power grid size
# of nodes in the power grid
214,223
638 X 968
617,584

# of PS
# of Decaps
Case 1
1
2
Case 2
1
10
Case 3
3
10
Case 4
3
20
32
Map of voltage drops for superblue10 Case 5 20
 Smaller voltage drop with distributed power delivery system
Benchmark Circuits – SuperBlue12
# of blocks
Power grid size
# of nodes in the power grid
15,349
444 X 518
229,992

# of PS
# of Decaps
Case 1
1
2
Case 2
1
10
Case 3
3
10
Case 4
3
20
32
Map of voltage drops for superblue12 Case 5 20
 Smaller voltage drop with distributed power delivery system
Benchmark Circuits – Superblue18
# of blocks
Power grid size
# of nodes in the power grid
41,047
381 X 404
153,924

# of PS
# of Decaps
Case 1
1
2
Case 2
1
10
Case 3
3
10
Case 4
3
20
32
Map of voltage drops for superblue18 Case 5 20
 Smaller voltage drop with distributed power delivery system
Distributed Power Delivery
One power supply
Two decaps
One power supply
Ten decaps
Three power supplies
Ten decaps
Three power supplies
20 decaps
20 power supplies
32 decaps
Maximum
voltage
drop
Average
voltage
drop
Maximum
voltage
drop
Average
voltage
drop
Maximum
voltage
drop
Average
voltage
drop
Maximum
voltage
drop
Average
voltage
drop
Maximum
voltage
drop
Average
voltage
drop
Superblue5
163 mV
130 mV
134 mV
115 mV
122 mV
73 mV
100 mV
69 mV
25 mV
9 mV
Superblue10
241 mV
173 mV
166 mV
133 mV
106 mV
81 mV
98 mV
72 mV
22 mV
11 mv
Superblue12
39 mV
28 mV
30 mV
24 mV
22 mV
12 mV
20 mV
13 mV
9 mV
3mV
Superblue18
47 mV
39 mV
38 mV
27 mV
27 mV
13 mV
20 mV
15 mV
10 mV
3 mV
Maximum voltage drop decreases significantly
with distributed power delivery
S. Köse and E. G. Friedman, ''Distributed On-Chip Power Delivery,''
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (in press).
Flow of Presentation

Power delivery yesterday, today and tomorrow

Heterogeneous power delivery management


Design complexity
Design solutions




Circuits
Models
Algorithms
Architecture

Future research

Summary
Architectural Clustering of Power Supplies

Objective



Design criteria
Maximize power
efficiency of system

Number of off-chip SMPS

Number of POL LDOs
Satisfy on-chip
area constraints

Clusters of LDOs within SMPS

Choice of output voltage levels for SMPS converters
+
–
…
…
1
+
–
…
…
…
VIN
+
–
…
…
NS
On-chip linear
power regulators
Voltage
islands
+
–
Off-chip switching
power converters
I/O
I. Vaisband and E. Friedman, "Methodology for Energy Efficient Distribution of On-Chip Power Supplies,"
IEEE Transactions on Power Electronics (in press).
Off-Chip Factors in Heterogeneous Power System
Power Efficiency vs. Number of SMPS converters
1.8 V
On-chip
power loss

3.0 V
1.8 V
(+VT)
Three off-chip SMPS
 93% efficiency
1.8 V (+VT) 1.8 V
1.1 V
3.0 V
1.0 V
1.1 V (+VT) 1.1 V
Off-chip
SMPS

POL
LDOs
Voltage
islands
Single off-chip SMPS
 68% efficiency
1.0 V (+VT) 1.0 V
Off-chip
SMPS
POL
LDOs
Voltage
islands
On-chip
power loss
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management

Future research

Summary
Summary
Delivering power to complex ICs is a fundamental bottleneck
Models
Algorithms
Closed-form expressions for
effective power grid resistance
Fast algorithms for power
grid analysis
Co-design methodology

Circuits
Ultra-small
point-of-load
voltage regulator

Power delivery on-chip
 Circuits
 Models
 Architecture
Power supply distribution on-chip
 Circuits
 Models
 Algorithms
Architecture
Topologies for on-chip
and off-chip co-design
of power supplies
Power Management – Cross-Field Research
Optimization
Optimization techniques
techniques


Power
management
Models
Computational
Computational geometry
geometry
Operations
Operations research
research
Algorithms
Circuits
Architecture
Interconnect
Interconnect evolution
evolution



Interconnect
Interconnect complexity
complexity
Bus
Bus signaling
signaling
Network-on-chip
Network-on-chip paradigm
paradigm
Flow of Presentation

Power delivery: yesterday, today, and tomorrow

Heterogeneous power delivery management

Future research

Summary
Summary
Delivering power to complex ICs is a fundamental bottleneck
Models
Algorithms
Closed-form expressions for
effective power grid resistance
Fast algorithms for power
grid analysis
Co-design methodology
Circuits
Ultra-small
point-of-load
voltage regulator
Off-chip
converters
On-chip
regulators
Decoupling
capacitors
considering
Power
High
3-D
efficiency
regulation (low noise)
integration
Architecture
Topologies for on-chip
and off-chip co-design
of power supplies
Distributed On-Chip Power
Regulators and Decoupling
Capacitors
Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester
Department of Electrical Engineering
Technion – Institute of Technology