Comparative analysis of Ni-Cr/Pt thin film resistors on silicon and

Indian Journal of Engineering & Materials Sciences
Vol. 19, October 2012, pp. 304-306
Comparative analysis of Ni-Cr/Pt thin film resistors on silicon and GaAs
substrates for IPD technology
Cong Wang & Nam-Young Kim*
RFIC Laboratory, Electronic Engineering Department, Kwangwoon University,
447-1 Wolgye-dong, Nowon-ku, Seoul 139-701, Korea
Received 18 May 2011; accepted 7 August 2012
The Ni-Cr/Pt thin film resistors (TFRs) deposited on silicon and GaAs substrates using the RF cluster sputtering system
are comparatively analyzed in electrical and physical properties for integrated passive device (IPD) technology. In order to
find the suitability of these substrates, the electrical and morphology characterizations for pure and thermally annealed
samples have been demonstrated. The pure and the annealed samples on GaAs substrate have shown very less variation of
resistivity from room temperature to 200ºC. But the variation of resistivity on silicon substrate has changed much for
different annealed temperatures. This is due to the mobility variation and the inter-diffusion of silicon with the other metals.
This study presents that the resistive Ni-Cr/Pt layers on the GaAs substrate shows more stability, less inter-diffusion and less
formation of voids compared to the resistive layers on silicon substrate.
Keywords: Integrated passive device, Thin film resistor, RF cluster sputtering system
An IPD technology on semi-insulating GaAs substrate
has been developed to meet the ever increasing needs
of size and cost reduction in wireless applications1-5.
IPD technology is the integration of passive
components, such as resistor, inductor, and capacitor
into thin film multi-layer system. For the fabrication
of resistor, a material providing a precision sheet
resistance and low temperature coefficient is needed6.
The nickel and chromium alloys that form Ni-Cr are
the most successful resistor materials for fabricating
TFRs in IPD process7-9. The precision of Ni-Cr TFRs
and their within-wafer and wafer-to-wafer uniformity
have always been very problematic for all of the
IPD processes, representing some of the biggest
manufacturing challenges. A single Pt layer is another
successful material for TFRs with a low temperature
coefficient10. Very few studies concerning the
combination of Ni-Cr and Pt with an appropriate
thickness are available. Therefore, a study has been
made with appropriate Au/Cu/Ni-Cr/Pt multi-layers
thicknesses in order to know their detailed behavior.
Finally, the Ni-Cr/Pt TFRs deposited on the different
substrates such as silicon and GaAs were
comparatively analyzed in electrical and morphology
*Corresponding author (Email: ,
Ni-Cr/Pt Thin Film Resistor
A multi-layer combination of a 100 Å thick Pt
layer and a 800 Å thick Ni-Cr layer are selected as the
barrier layers between the substrate and the contact
metal (Cu/Au) for this present study. The multi-layers
along with the Cu/Au metallization can be deposited
by either electron-beam (e-beam) evaporation or the
sputtering method. It is well known that sputtering
during the growth of these films causes an
improvement in the quality of the thin films.
Au/Cu/Pt/Ni-Cr multi-layers on silicon and GaAs
substrates have been deposited using the RF cluster
sputtering process.
The substrates were subjected to various cleaning
processes in order to remove the organics, the
inorganics and other elements. Cleaning processes
can use lift-off machine in acetone at nozzle pressure
of 5 Mega for 180 s, rinsed briefly with isopropyl
alcohol (IPA) and distilled water, and O2/H2 plasma
treatment is done by a microwave asher operating at
gas mixing rate (20:1), working pressure (2 Torr),
chuck temperature (80ºC), and RF power (550 W) for
60 s. After cleaning process, the Ni-Cr/Pt layer is
deposited from a target consisting of 90% Ni and
10% Cr in order to get the optimal performance.
The deposition lasted for 410 s, during that the
substrate was maintained at around 60ºC. Such low
temperatures are possible due to the higher deposition
speed of the cluster sputtering method. The deposition
conditions are a vacuum of lower than 4 × 10-7 Torr,
an RF power of 1 kW and a voltage of 200 V.
The Au/Cu/Ni-Cr/Pt samples possessed thicknesses
on the order of 200 Å /300 Å /800 Å /100 Å for a
target sheet resistance of 25 Ohm/sq. The samples on
the silicon and GaAs substrates were annealed at
400ºC and 600ºC, respectively, supplanted by rapid
thermal anneal (RTA) for 30 min in a nitrogen
atmosphere. X-ray diffraction measurements were
carried out using the X-ray diffraction (XRD). Cu-kα
radiation from the X-ray tube was used with normal
focusing. The surface topography and the grain size,
along with their variations, of the annealed samples
were analyzed using Hitachi S-4800 scanning electron
microscope (SEM) and PSIA XE100 atomic force
microscope (AFM). The elemental analysis was
carried out using energy-dispersive X-ray spectroscopy
(EDAX), which is attached to the SEM. An analysis
of the electrical sheet resistivity was also carried
out using a four-probe method from room temperature
to 200ºC.
Measurement Results
The annealed sample on silicon substrate at 400ºC
showed a slight variation with no change in phase. At
600ºC the grain size tended to increase due to the fact
that the annealing temperature was able to slightly
activate some thermal diffusion. Surface morphology,
grain size, and their variations can be analyzed by
using SEM and AFM, which clearly indicated the
inter-diffusion as shown in Figs 1 and 2, respectively.
The surface roughness achieved with annealing
process is worse than the pure sample due to the
fact that multi-layers on silicon substrate became soft
with annealing as well as a peeling off for the higher
loads. The EDAX can be used to identify the
presented materials and the metallization on the
device. The metallization can be completely destroyed
by reactions induced by thermally activated processes
in the case of the silicon substrate. But in the case of
the GaAs substrate, there was no inter-diffusion and
no voids. However, as the annealing temperature
increases, silicon from the substrate diffuses into the
multi-layers through the grain boundary paths in order
to satisfy solubility and the number of voids and the
inter-diffusion increase. Resistivity measurements
from room temperature to 200ºC were carried out
using the four-probe method, which is an accurate
method for the determination of resistivity. The
results of the measurements are presented on the
Arrhenius plot for the different substrates, which are
shown in Fig. 3. The GaAs substrate sample showed a
low resistivity value with less variation over a range
of temperatures.
The annealed samples on the GaAs substrate did
not show much variation. However, the silicon
substrate sample showed a large variation with a high
Fig. 1—SEM pictures of: a) pure; b) annealed at 400 °C; and c) annealed at 600 °C samples on the silicon substrate
Fig. 2—AFM pictures of: a) pure; b) annealed at 400 ºC; and c) annealed at 600 ºC samples on the silicon substrate
value of resistivity over the different annealing
temperatures. The Arrhenius plot for the pure and
annealed samples on the silicon and GaAs substrates
are shown in Figs 4 and 5, respectively. The increase
in the resistivity value for the annealed samples on
silicon substrate was due to an increased dislocation,
vacancies, and grain boundary diffusion as well as the
presence of a Pt-Si layer. The behavior of the residual
resistivity in the pure and the annealed samples
confirms the inter-diffusion of the layers and a
mobility variation due to the inter-diffusion of the
metal layers diffusion of impurities.
Fig. 3—The variation of the Arrhenius plot of the multi-layers
on the silicon and GaAs substrates without annealing process
The SEM and AFM results showed the interdiffusion and the formation of voids in the case of the
multi-layers on the silicon substrate. The resistive
layers Ni-Cr/Pt on the GaAs substrate presented more
stability, less inter-diffusion, and less formation of
voids compared to the resistive layers on silicon
substate. This confirms that the GaAs substrate with
the selected multi-layer thickness is more suitable for
the creation of IPDs with good performances.
This research was supported by the National
Research Foundation of Korea (NRF) grant funded
by the Korean government (MEST) under No. 20120009224 and No. 2012R1A1A2004366. This work
was also supported by the Research Grant of
Kwangwoon University in 2012.
Fig. 4—The variation of the Arrhenius plot of the pure and
annealed samples on the silicon substrate
Fig. 5—The variation of the Arrhenius plot of the pure and
annealed samples on the GaAs substrate
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