NTE74HC74
Integrated Circuit
TTL − High Speed CMOS,
Dual D−Type Positive−Edge Triggered Flip−Flop
with Set and Reset
Description:
The NTE74HC74 is a dual D−type flip−flop in a 14−Lead DIP type package that utilizes silicon gate CMOS
technology to achieve operating speeds similar to LS−TTL gates with the low power consumption of
standard CMOS integrated circuits. All devices have the ability to drive 10 LS−TTL loads.
This flip−flop has independent DATA, SET, RESET and CLOCK inputs and Q and Q outputs. he logic
level present at the data input is transferred to the output during the positive−going transition of the
clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at
the appropriate input.
Features:
D Wide Power Supply Range: 2V to 6V
D High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
D Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall
Times
D Asynchronous Set and Reset
D Complementary Outputs
D Buffered Inputs
D Typical fMAX: 50MHz at VCC = 5V, CL = 15pF, TA = +25C
D Fanout (Over Temperature Range):
Standard Outputs . . . 10 LS−TTL Loads
Bus Driver Outputs . . 15 LS−TTL Loads
D Balanced Propagation Delay and Transition Times
D Significant Power Reduction Compared to LS−TTL Logic ICs
Absolute Maximum Ratings: (Note 1, Note 2)
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to +7.0V
DC Diode Current, IIK, IOK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
DC Drain Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
DC Output Source or Sink Current (Per Output), IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA
DC VCC or GND Current (Per Pin), ICC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA
Maximum Junction, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C
Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65C to +150C
Typical Thermal Resistance, Junction−to−Ambient, RthJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80C/W
Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C
Note 1. Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2. Unless otherwise specified, all voltages are referenced to GND.
Recommended Operating Conditions:
Parameter
Supply Voltage
DC Input or Output Voltage
Operating Temperature Range
Input Rise or Fall Times
VCC = 2.0V
VCC = 4.5V
VCC = 6.0V
Symbol
Min
Typ
Max
Unit
VCC
VIN, VOUT
TA
tr, tf
2.0
0
−40
−
−
−
6.0
VCC
+85
V
V
C
−
−
−
−
−
−
1000
500
400
ns
ns
ns
DC Electrical Characteristics:
TA = +25C
Parameter
Minimum HIGH Level Input Voltage
Maximum LOW Level Input Voltage
Minimum HIGH Level Output
Voltage
Minimum LOW Level Output
Voltage
Symbol
VIH
Test Conditions
VIL
VOH
VOL
VIN = VIH
or VIL
VIN = VIH
or VIL
TA = −40 to +85C
VCC
Typ
Guaranteed Limits
2.0
−
1.5
1.5
Unit
V
4.5
−
3.15
3.15
V
6.0
−
4.2
4.2
V
2.0
−
0.5
0.5
V
4.5
−
1.35
1.35
V
6.0
−
1.8
1.8
V
VCC VCC
−0.1
VCC
−0.1
IOUT = −20A
−
IOUT = −4mA
4.5
−
3.98
3.84
V
V
IOUT = −5.2mA
6.0
−
5.48
5.34
V
IOUT = 20A
−
−
0.1
0.1
V
IOUT = 4mA
4.5
−
0.26
0.33
V
IOUT = 5.2mA
6.0
−
0.26
0.33
V
Maximum Input Leakage Current
IIN
VIN = VCC or GND
6.0
−
0.1
1.0
A
Maximum Quiescent Device Current
ICC
VIN = VCC or GND, IOUT = 0A
6.0
−
4.0
40
A
Prerequisite for Switching Specifications:
TA = +25C
Parameter
Data to CP Setup Time
Hold Time
Removal Time (R, S, to CP)
Pulse Width (R, S)
Pulse Width (CP)
CP Frequency
TA = −40 to +85C
VCC
Typ
2.0
−
60
75
Unit
ns
4.5
−
12
15
ns
6.0
−
10
13
ns
tH
All
−
3
3
ns
tREM
2.0
−
30
40
ns
4.5
−
6
8
ns
6.0
−
5
7
ns
2.0
−
80
100
ns
4.5
−
16
20
ns
6.0
−
14
17
ns
2.0
−
80
100
ns
4.5
−
16
20
ns
6.0
−
14
17
ns
2.0
−
6
5
MHz
4.5
−
30
25
MHz
6.0
−
35
29
MHz
Symbol
tSU
tW
tW
fMAX
Test Conditions
Guaranteed Limits
Switching Specifications: (tr = tf = 6ns unless otherwise specified)
TA = +25C
Parameter
Propagation Delay Time (CP to Q, Q)
Propagation Delay Time (R, S to Q, Q)
Transition Time
TA = −40 to +85C
VCC
Typ
2.0
−
175
220
Unit
ns
4.5
−
35
44
ns
CL = 15pF
5.0
14
−
−
ns
CL = 50pF
6.0
−
30
37
ns
tPLH, tPHL CL = 50pF
2.0
−
200
250
ns
4.5
−
40
50
ns
CL = 15pF
5.0
17
−
−
ns
CL = 50pF
6.0
−
34
43
ns
tTLH, tTHL CL = 50pF
2.0
−
75
95
ns
4.5
−
15
19
ns
6.0
−
13
16
ns
Symbol
Test Conditions
tPLH, tPHL CL = 50pF
Guaranteed Limits
Maximum Input Capacitance
CIN
−
−
10
10
pF
CP Frequency
fMAX
CL = 15pF
5.0
50
−
−
MHz
Power Dissipation Capacitance
CPD
Note 3
5.0
30
−
−
pF
Note 3. CPD is used to determine the dynamic power consumption, per gate.
PD = CPD VCC2 fi +  (CL VCC2 fo) where fi = Input Frequency, fo = Output Frequency,
CL = Output Load Capacitance, VCC = Supply Voltage.
Truth Table:
Inputs
Outputs
SET
RESET
CP
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (Note) H (Note)
H
H

H
H
L
H
H

L
L
H
H
H
L
X
Q0
Q0
H = HIGH Level (Steady State)
L = LOW Level (Steady State)
X = Don’t Care
 = LOW−to−HIGH Transition
Q0 = the level of Q before the indicated input conditions were established
Note: This configuration is nonstable, that is, it will not persist when set and reset
inputs return to their inactive (high) level.
Pin Connection Diagram
1R 1
14 VCC
13 2R
12 2D
1D 2
1CP 3
1S 4
11 2CP
1Q 5
10 2S
1Q 6
9 2Q
8 2Q
GND 7
14
8
1
7
.300
(7.62)
.770 (19.56)
Max
.200 (5.08)
Max
.100 (2.45)
.600 (15.24)
.125 (3.17) Min