IN74HC595A
8-BIT SERIAL-INPUT/SERIAL OR
PARALLEL-OUTPUT SHIFT REGISTER
WITH LATCHED 3-STATE OUTPUTS
High-Performance Silicon-Gate CMOS
•
•
•
•
The IN74HC595A is identical in pinout to the LS/ALS595. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
The IN74HC595A consists of an 8-bit shift register and an 8-bit
D-type latch with three-state parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register
also provides parallel data to the 8-bit latch. The shift register and
latch have independent clock inputs. This device also has an
asynchronous reset for the shift register.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC595AN Plastic
IN74HC595AD SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 16 =VCC
PIN 8 = GND
1
IN74HC595A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Current, per Pin
mA
±35
ICC
DC Supply Current, VCC and GND Pins
mA
±75
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
TA
Operating Temperature, All Package Types
t r, tf
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
2.0
0
Max
6.0
VCC
Unit
V
V
-55
0
0
0
+125
1000
500
400
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or
electric fields. However, precautions must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be
constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74HC595A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Guaranteed Limit
VCC
Symbol Parameter
Test Conditions
V
25 °C ≤85 ≤125
to
°C
°C
-55°C
1.5
1.5
VOUT=0.1 V or VCC-0.1 V
1.5
VIH
Minimum High2.0
3.15 3.15 3.15
Level Input
4.5
IOUT≤ 20 µA
4.2
4.2
4.2
Voltage
6.0
0.5
0.5
VOUT=0.1 V or VCC-0.1 V
0.5
VIL
Maximum Low 2.0
1.35 1.35 1.35
Level Input
4.5
IOUT ≤ 20 µA
1.8
1.8
1.8
Voltage
6.0
1.9
1.9
1.9
VIN=VIH or VIL
VOH
Minimum High2.0
4.4
4.4
4.4
Level Output
4.5
IOUT ≤ 20 µA
5.9
5.9
5.9
Voltage, QA-QH
6.0
VIN=VIH or VIL
3.7
3.98 3.84
4.5
IOUT ≤ 6.0 mA
5.2
5.34
5.48
6.0
IOUT ≤ 7.8 mA
0.1
0.1
0.1
VIN=VIH or VIL
VOL
Maximum Low2.0
0.1
0.1
0.1
Level Output
4.5
IOUT ≤ 20 µA
0.1
0.1
0.1
Voltage, QA-QH
6.0
VIN=VIH or VIL
0.4
0.26 0.33
4.5
IOUT ≤ 6.0 mA
0.4
0.26 0.33
6.0
IOUT ≤ 7.8 mA
1.9
1.9
1.9
VIN=VIH or VIL
VOH
Minimum High2.0
4.4
4.4
4.4
Level Output
4.5
IOUT ≤ 20 µA
5.9
5.9
5.9
Voltage, SQH
6.0
VIN=VIH or VIL
3.7
3.98 3.84
4.5
IOUT ≤ 4.0 mA
5.2
5.48 5.34
6.0
IOUT ≤ 5.2 mA
0.1
0.1
0.1
VIN=VIH or VIL
VOL
Maximum Low2.0
0.1
0.1
0.1
Level Output
4.5
IOUT ≤ 20 µA
0.1
0.1
0.1
Voltage, SQH
6.0
VIN=VIH or VIL
0.4
0.26 0.33
4.5
IOUT ≤ 4.0 mA
0.4
0.26 0.33
6.0
IOUT ≤ 5.2 mA
IIN
Maximum Input
VIN=VCC or GND
6.0
±0.1
±1.0 ±1.0
Leakage Current
IOZ
Maximum Three- Output in High6.0
±0.5
±5.0 ±10
Impedance State
State Leakage
VIN= VIL or VIH
Current, QA-QH
VIN=VCC or GND
VIN=VCC or GND
ICC
Maximum
6.0
4.0
40
160
Quiescent Supply IOUT=0µA
Current
(per Package)
3
Unit
V
V
V
V
V
V
µA
µA
µA
IN74HC595A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
≤85
≤125
25 °C
to
°C
°C
-55°C
4.0
4.8
6.0
fmax
Minimum Clock Frequency (50% Duty 2.0
20
24
30
Cycle) (Figures 1and 7)
4.5
24
28
35
6.0
210
175
140
tPLH,
Maximum Propagation Delay, Shift Clock 2.0
42
35
28
tPHL
to SQH (Figures 1and 7)
4.5
36
30
24
6.0
220
180
145
tPHL
Maximum Propagation Delay , Reset to 2.0
44
36
29
SQH (Figures 2 and 7)
4.5
38
31
25
6.0
210
175
140
tPLH,
Maximum Propagation Delay , Latch 2.0
42
35
28
tPHL
Clock to QA-QH (Figures 3 and 7)
4.5
36
30
24
6.0
225
190
150
tPLZ,
Maximum Propagation Delay , Output 2.0
45
38
30
tPHZ
Enable to QA-QH (Figures 4 and 8)
4.5
38
33
26
6.0
205
170
135
tPZL,
Maximum Propagation Delay , Output 2.0
41
34
27
tPZH
Enable to QA-QH (Figures 4 and 8)
4.5
35
29
23
6.0
90
75
60
tTLH, tTHL Maximum Output Transition Time, QA-QH 2.0
18
15
12
(Figures 3 and 7)
4.5
15
13
10
6.0
110
95
75
tTLH, tTHL Maximum Output Transition Time, SQH 2.0
22
19
15
(Figures 1 and 7)
4.5
19
16
13
6.0
CIN
Maximum Input Capacitance
10
10
10
15
15
15
COUT
Maximum
Three-State
Output
Capacitance (Output in High-Impedance
State), QA-QH
CPD
Power Dissipation Capacitance (Per
Package)
Used to determine the no-load dynamic
power
consumption:
PD=CPDVCC2f+ICCVCC
4
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
pF
pF
Typical @25°C,VCC=5.0 V
300
pF
IN74HC595A
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C to
≤85°C
-55°C
65
50
tsu
Minimum Setup Time,Serial 2.0
13
10
Data Input A to Shift Clock 4.5
11
9
6.0
(Figure 5)
95
75
tsu
Minimum Setup Time, Shift 2.0
19
15
Clock to Latch Clock (Figure 6)
4.5
16
13
6.0
5
5
th
Minimum Hold Time, Shift 2.0
5
5
Clock to Serial Data Input A 4.5
5
5
6.0
(Figure 5)
65
50
trec
Minimum
Recovery
Time, 2.0
13
10
Reset Inactive to Shift Clock 4.5
11
9
6.0
(Figure 2)
75
60
tw
Minimum Pulse Width, Reset 2.0
15
12
(Figure 2)
4.5
13
10
6.0
65
50
tw
Minimum Pulse Width, Shift 2.0
13
10
Clock (Figure 1)
4.5
11
9
6.0
65
50
tw
Minimum Pulse Width, Latch 2.0
13
10
Clock (Figure 6)
4.5
11
9
6.0
1000
1000
t r, tf
Maximum Input Rise and Fall 2.0
500
500
Times (Figure 1)
4.5
400
400
6.0
5
≤125
°C
75
15
13
110
22
19
5
5
5
75
15
13
90
18
15
75
15
13
75
15
13
1000
500
400
Unit
ns
ns
ns
ns
ns
ns
ns
ns
IN74HC595A
FUNCTION TABLE
Operation
Inputs
Resulting Function
Serial
Latch
Shift
Res Seria Shift Latc Output
h Enable Register Register Output
Cloc
et
l
SQH
Contents Content
Cloc
Input k
s
k
A
shift L
X
X
L,H,
L
L
U
L
Reset
register
Shift data into shift H
D
register
X
Shift
register H
remains
unchanged
X
Transfer
shift H
register contents
to latch register
X
Latch
register X
remains
unchanged
Enable
parallel X
X
outputs
X
Force outputs into X
high-impedance
state
SR = shift register contents
LR = latch register contents
D = data (L,H) logic level
U = remains unchanged
L,H,
Parallel
Output
s QAQH
U
L,H,
L
D SRA
SRN SRN+1
U
SRG SRH
U
L,H,
L
U
U
U
U
L
U
SRN LRN
U
SRN
L,H,
X
L,H,
L
*
U
*
U
X
X
L
*
**
*
X
X
H
*
**
*
Enable
d
Z
X = don’t care
Z = high impedance
* = depends on Reset and Shift Clock inputs
** = depends on Latch Clock input
PIN DESCRIPTIONS
INPUTS:
A - Serial Data Input. The data on this pin is shifted into the 8-bit serial shift register.
CONTROL INPUTS:
Shift Clock - Shift Register Clock Input. A low-to-high transition on this input causes the data at the
Serial Input pin to be shifted into the 8-bit shift register.
Reset - Active-low, Asynchronous, Shift Register Reset Input. A low on this pin resets the shift
register portion of this device only. The 8-bit latch is not affected.
Latch Clock - Storage Latch Clock Input. A low-to-high transition on this input latches the shift
register data.
Output Enable - Active-Low Output Enable. A low on this input allows the data from the latches to
bepresented at the outputs. A high on this input forces the outputs (QA-QH) into the high-impedance
state. The serial output is not affected by this control unit.
OUTPUTS:
QA-QH - Noninverted, 3-state, latch outputs.
SQH - Voninverted, Serial Data Output. This is the output of the eighth stage of the 8-bit shift register.
This
output
does
not
have
three-state
capability.
6
IN74HC595A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
Figure 5. Switching Waveforms
Figure 6. Switching Waveforms
Figure 7. Test Circuit
Figure 8. Test Circuit
7
IN74HC595A
TIMING DIAGRAM
8
IN74HC595A
EXPANDED LOGIC DIAGRAM
9