Carpenter, G.L., Choma, Jr., J. “Amplifiers”
The Electrical Engineering Handbook
Ed. Richard C. Dorf
Boca Raton: CRC Press LLC, 2000
28
Amplifiers
28.1 Large Signal Analysis
DC Operating Point • Graphical Approach • Power Amplifiers
Gordon L. Carpenter
28.2 Small Signal Analysis
California State University,
Long Beach
John Choma, Jr.
University of Southern California
28.1
Hybrid-Pi Equivalent Circuit • Hybrid-Pi Equivalent Circuit of a
Monolithic BJT • Common Emitter Amplifier • Design
Considerations for the Common Emitter Amplifier • Common Base
Amplifier • Design Considerations for the Common Base
Amplifier • Common Collector Amplifier
Large Signal Analysis
Gordon L. Carpenter
Large signal amplifiers are usually confined to using bipolar transistors as their solid state devices because of
the large linear region of amplification required. One exception to this is the use of VMOS for large power
outputs due to their ability to have a large linear region. There are three basic configurations of amplifiers:
common emitter (CE) amplifiers, common base (CB) amplifiers, and common collection(CC) amplifiers. The
basic configuration of each is shown in Fig. 28.1.
In an amplifier system, the last stage of a voltage amplifier string has to be considered as a large signal
amplifier, and generally EF amplifiers are used as large signal amplifiers. This then requires that the dc bias or
dc operating point (quiescent point) be located near the center of the load line in order to get the maximum
output voltage swing. Small signal analysis can be used to evaluate the amplifier for voltage gain, current gain,
input impedance, and output impedance, all of which are discussed later.
DC Operating Point
Each transistor connected in a particular amplifier configuration has a set of characteristic curves, as shown in
Fig. 28.2.
When amplifiers are coupled together with capacitors, the configuration is as shown in Fig. 28.3. The load
resistor is really the input impedance of the next stage. To be able to evaluate this amplifier, a dc equivalent
circuit needs to be developed as shown in Fig. 28.4. This will result in the following dc bias equation:
ICQ =
VBB - VBE
RB beta + RE
Assume h FE >> 1
where beta (hFE) is the current gain of the transistor and VBE is the conducting voltage across the base-emitter
junction. This equation is the same for all amplifier configurations. Looking at Fig. 28.3, the input circuit can
be reduced to the dc circuit shown in Fig. 28.4 using circuit analysis techniques, resulting in the following
equations:
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FIGURE 28.1 Amplifier circuits. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems,
2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 80. With permission.)
FIGURE 28.2 Transistor characteristic curves. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits
and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.)
FIGURE 28.3 Amplifier circuit. (Source: C.J. Savant, M.
Roden, and G. Carpenter, Electronic Design, Circuits and
Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 92. With permission.)
© 2000 by CRC Press LLC
FIGURE 28.4 Amplifier equivalent circuit. (Source: C.J.
Savant, M. Roden, and G. Carpenter, Electronic Design,
Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 82. With permission.)
V BB = V TH = VCC (R1)/(R1 + R2)
RB = RTH = R1//R2
For this biasing system, the Thévenin equivalent resistance and the Thévenin equivalent voltage can be determined. For design with the biasing system shown in Fig. 28.3, then:
R1 = RB /(1 – VBB /VCC)
R2 = RB (VC C /VBB)
Graphical Approach
To understand the graphical approach, a clear understanding of the dc and ac load lines is necessary. The dc
load line is based on the Kirchhoff ’s equation from the dc power source to ground (all capacitors open)
VCC = vCE + iC RDC
where RDC is the sum of the resistors in the collector-emitter loop.
The ac load line is the loop, assuming the transistor is the ac source and the source voltage is zero, then
V ¢CC = vce + iC Rac
where Rac is the sum of series resistors in that loop with all the capacitors shorted. The load lines then can be
constructed on the characteristic curves as shown in Fig. 28.5. From this it can be seen that to get the maximum
output voltage swing, the quiescent point, or Q point, should be located in the middle of the ac load line. To
place the Q point in the middle of the ac load line, ICQ can be determined from the equation
ICQ = VCC /(RDC + Rac )
FIGURE 28.5 Load lines. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd
ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 94. With permission.)
© 2000 by CRC Press LLC
FIGURE 28.6 Q point in middle of load line. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits
and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 135. With permission.)
To minimize distortion caused by the cutoff and saturation regions, the top 5% and the bottom 5% are discarded.
This then results in the equation (Fig. 28.6):
V o (peak to peak) = 2 (0.9) ICQ (RC //RL)
If, however, the Q point is not in the middle of the ac load line, the output voltage swing will be reduced. Below
the middle of the ac load line [Fig. 28.7(a)]:
V o (peak to peak) = 2 (ICQ – 0.05 I CMax) RC //RL
Above the middle of the ac load line [Fig. 28.7(b)]:
V o (peak to peak) = 2 (0.95 I CMax – ICQ) RC //RL
These values allow the highest allowable input signal to be used to avoid any distortion by dividing the voltage
gain of the amplifier into the maximum output voltage swing. The preceding equations are the same for the
CB configuration. For the EF configurations, the R C is changed to RE in the equations.
FIGURE 28.7 Reduced output voltage swing. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits
and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 136. With permission.)
© 2000 by CRC Press LLC
FIGURE 28.8 Complementary symmetry power amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic
Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 248. With permission.)
Power Amplifiers
Emitter followers can be used as power amplifiers. Even though they have less than unity voltage gain they can
provide high current gain. Using the standard linear EF amplifier for a maximum output voltage swing provides
less than 25% efficiency (ratio of power in to power out). The dc current carrying the ac signal is where the
loss of efficiency occurs. To avoid this power loss, the Q point is placed at ICQ equal to zero, thus using the
majority of the power for the output signal. This allows the efficiency to increase to as much as 70%. Full signal
amplification requires one transistor to amplify the positive portion of the input signal and another transistor
to amplify the negative portion of the input signal. In the past, this was referred to as push-pull operation. A
better system is to use an NPN transistor for the positive part of the input signal and a PNP transistor for the
negative part. This type of operation is referred to as Class B complementary symmetry operation (Fig. 28.8).
In Fig. 28.8, the dc voltage drop across R1 provides the voltage to bias the transistor at cutoff. Because these
are power transistors, the temperature will change based on the amount of power the transistor is absorbing.
This means the base-emitter junction voltage will have to change to keep ICQ = 0. To compensate for this change
in temperature, the R1 resistors are replaced with diodes or transistors connected as diodes with the same turnon characteristics as the power transistors. This type of configuration is referred to as the complementary
symmetry diode compensated (CSDC) amplifier and is shown in Fig. 28.9. To avoid crossover distortion, small
resistors can be placed in series with the diodes so that ICQ can be raised slightly above zero to get increased
amplification in the cutoff region. Another problem that needs to be addressed is the possibility of thermal
runaway. This can be easily solved by placing small resistors in series with the emitters of the power transistors.
For example, if the load is an 8-W speaker, the resistors should not be greater than 0.47 W to avoid output
signal loss.
To design this type of amplifier, the dc current in the bias circuit must be large enough so that the diodes
remain on during the entire input signal. This requires the dc diode current to be equal to or larger than the
zero to peak current of the input signal, or
ID ³ Iac (0 to peak)
(VCC /2 – VBE)/R2 = IB (0 to peak) + VL (0 to peak)/R2
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FIGURE 28.9 Complimentary symmetry diode compensated power amplifier. (Source: C.J. Savant, M. Roden, and G.
Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 251. With
permission.)
FIGURE 28.10 AC equivalent circuit of the CSDC amplifier. (Source: C.J. Savant, M. Roden, and G. Carpenter, Electronic
Design, Circuits and Systems, 2nd ed., Redwood City, Calif.: Benjamin-Cummings, 1991, p. 255. With permission.)
When designing to a specific power, both IB and VL can be determined. This allows the selection of the value
of R2 and the equivalent circuit shown in Fig. 28.10 can be developed. Using this equivalent circuit, both the
input resistance and the current gain can be shown. Rf is the forward resistance of the diodes.
Rin = (Rf + R2)//[Rf + (R2 //Beta RL)]
P o = I Cmax R L /2
The power rating of the transistors to be used in this circuit should be greater than
Prating = VC2 C /(4Pi2RL )
C1 = 1/(2Pi f low RL )
C2 = 10/[2Pi flow(Rin + Ri )]
where Ri is the output impedance of the previous stage and flow is the desired low frequency cutoff of the amplifier.
Related Topics
24.1 Junction Field-Effect Transistors • 30.1 Power Semiconductor Devices
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References
P.R. Gray and R.G. Meyer, Analysis and Design of Analog Integrated Circuits, New York: Wiley, 1984.
J. Millman and A. Grabel, Microelectronics, New York: McGraw-Hill, 1987.
P.O. Neudorfer and M. Hassul, Introduction to Circuit Analysis, Needham Heights, Mass.: Allyn and Bacon, 1990.
C.J. Savant, M. Roden, and G. Carpenter, Electronic Design, Circuits and Systems, 2nd ed., Redwood City, Calif.:
Benjamin-Cummings, 1991.
D.L. Schilling and C. Belove, Electronic Circuits, New York: McGraw-Hill, 1989.
28.2
Small Signal Analysis
John Choma, Jr.
This section introduces the reader to the analytical methodologies that underlie the design of small signal,
analog bipolar junction transistor (BJT) amplifiers. Analog circuit and system design entails complementing
basic circuit analysis skills with the art of architecting a circuit topology that produces acceptable input-tooutput (I/O) electrical characteristics. Because design is not the inverse of analysis, analytically proficient
engineers are not necessarily adept at design. However, circuit and system analyses that conduce an insightful
understanding of meaningful topological structures arguably foster design creativity. Accordingly, this section
focuses more on the problems of interpreting analytical results in terms of their circuit performance implications than it does on enhancing basic circuit analysis skills. Insightful interpretation breeds engineering
understanding. In turn, such an understanding of the electrical properties of circuits promotes topological
refinements and innovations that produce reliable and manufacturable, high performance electronic circuits
and systems.
Hybrid-Pi Equivalent Circuit
In order for a BJT to function properly in linear amplifier applications, it must operate in the forward active
region of its volt–ampere characteristic curves. Two conditions ensure BJT operation in the forward domain.
First, the applied emitter-base terminal voltage must forward bias the intrinsic emitter-base junction diode at
all times. Second, the instantaneous voltage established across the base-collector terminals of the transistor
must preclude a forward biased intrinsic base-collector diode. The simultaneous satisfaction of these two
conditions requires appropriate biasing subcircuits, and it imposes restrictions on the amplitudes of applied
input signals [Clarke and Hess, 1978].
The most commonly used BJT equivalent circuit for investigating the dynamical responses to small input
signals is the hybrid-pi model offered in Fig. 28.11 [Sedra and Smith, 1987]. In this model, R b, R c, and R e,
respectively, represent the internal base, collector, and emitter resistances of the considered BJT. Although these
series resistances vary somewhat with quiescent operating point [de Graaf, 1969], they can be viewed as
constants in first-order manual analyses.
FIGURE 28.11 The small signal equivalent circuit (hybrid-pi model) of a bipolar junction transistor.
© 2000 by CRC Press LLC
The emitter-base junction diffusion resistance, R p , is the small signal resistance of the emitter-base junction
diode. It represents the inverse of the slope of the common emitter static input characteristic curves. Analytically,
Rp is given by
Rp =
h FE N F VT
I CQ
(28.1)
where hFE is the static common emitter current gain of the BJT, N F is the emitter-base junction injection coefficient,
V T is the Boltzmann voltage corresponding to an absolute junction operating temperature of T, and ICQ is the
quiescent collector current.
The expression for the resistance, R o , which accounts for conductivity modulation in the neutral base, is
Ro =
VCEQ
¢ + V AF
(28.2)
æ
I CQ ö
I CQ ç 1 ÷
I KF ø
è
where VAF is the forward Early voltage, VCEQ
¢ is the quiescent voltage developed across the internal collectoremitter terminals, and IKF symbolizes the forward knee current. The knee current is a measure of the onset of
high injection effects [Gummel and Poon, 1970] in the base. In particular, a collector current numerically equal
to IKF implies that the forward biasing of the emitter-base junction promotes a net minority carrier charge
injected into the base from the emitter that is equal to the background majority charge in the neutral base. The
Early voltage is an inverse measure of the slope of the common emitter output characteristic curves.
The final low frequency parameter of the hybrid-pi model is the forward transconductance, gm. This parameter,
which is a measure of the forward small signal gain available at a quiescent operating point, is given by
gm
æ
I CQ ö
1ç
÷
I CQ ç
I KF ÷
=
N F VT ç
VCEQ ¢ ÷
ç1 +
÷
V AF ø
è
(28.3)
Two capacitances, Cp and C m , are incorporated in the small signal model to provide a first-order approximation of steady-state transistor behavior at high signal frequencies. The capacitance, C p , is the net capacitance
of the emitter-base junction diode and is given by
Cp =
C JE
ö
æ
VE
÷
ç1 V JE - 2VT ø
è
M JE
+ t f gm
(28.4)
where the first term on the right-hand side represents the depletion component and the second term is the
diffusion component of C p . In Eq. (28.4), tf is the average forward transit time of minority carriers in the fieldneutral base, CJE is the zero bias value of emitter-base junction depletion capacitance, VJE is the built-in potential
of the junction, VE is the forward biasing voltage developed across the intrinsic emitter-base junction, and MJE is
the grading coefficient of the junction. The capacitance, C m , has only a depletion component, owing to the reverse
© 2000 by CRC Press LLC
FIGURE 28.12 (a) Schematic diagram pertinent to the evaluation of the short circuit, common emitter, small signal current
gain. (b) High frequency small signal model of the circuit in part (a).
(or at most zero) bias impressed across the internal base-collector junction. Accordingly, its analytical form is
analogous to the first term on the right-hand side of Eq. (28.4). Specifically,
C JC
Cm =
ö
æ
VC
1
÷
ç
V JC - 2VT ø
è
M JC
(28.5)
where the physical interpretation of CJ C , VJ C , and MJC is analogous to CJE , VJE , and MJE , respectively.
A commonly invoked figure of merit for assessing the high speed, small signal performance attributes of a
BJT is the common emitter, short circuit gain-bandwidth product, w T , which is given by
wT =
gm
Cp + Cm
(28.6)
The significance of Eq. (28.6) is best appreciated by studying the simple circuit diagram of Fig. 28.12(a), which
depicts the grounded emitter configuration of a BJT biased for linear operation at a quiescent base current of
IB Q and a quiescent collector-emitter voltage of VCEQ . Note that the battery supplying VCEQ grounds the collector
for small signal conditions. The small signal model of the circuit at hand is resultantly seen to be the topology
offered in Fig. 28.12(b), where iBS and iCS , respectively, denote the signal components of the net instantaneous
base current, iB, and the net instantaneous collector current, i C .
For negligibly small internal collector (Rc ) and emitter (Re) resistances, it can be shown that the small signal,
short circuit, high frequency common emitter current gain, bac(jw), is expressible as
bac ( j w)D
iCS
=
i BS
æ
j wC m ö
bac ç 1 ÷
gm ø
è
jw
1+
wb
where bac , the low frequency value of bac(jw), or simply the low frequency beta, is
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(28.7)
bac = bac(0) = gm Rp
(28.8)
and
wb =
1
R p (C p + C m )
(28.9)
symbolizes the so-called beta cutoff frequency of the BJT. Because the frequency, g m /Cm , is typically much larger
than wb , wb is the approximate 3-dB bandwidth of bac (jw); that is,
*bac ( j w b ) * @
bac
(28.10)
2
It follows that the corresponding gain-bandwidth product, w T , is the product of bac and wb , which, recalling
Eq. (28.8), leads directly to the expression in Eq. (28.6). Moreover, in the neighborhood of w T ,
bac ( j w) @
bac w b
jw
=
wT
jw
(28.11)
which suggests that wT is the approximate frequency at which the magnitude of the small signal, short circuit,
common emitter current gain degrades to unity.
Hybrid-Pi Equivalent Circuit of a Monolithic BJT
The conventional hyprid-pi model in Fig. 28.11 generally fails to provide sufficiently accurate predictions of
the high frequency response of monolithic diffused or implanted BJTs. One reason for this modeling inaccuracy
is that the hybrid-pi equivalent circuit does not reflect the fact that monolithic transistors are often fabricated
on lightly doped, noninsulating substrates that establish a distributed, large area, pn junction with the collector
region. Since the substrate-collector pn junction is back biased in linear applications of a BJT, negligible static
and low frequency signal currents flow from the collector to the substrate. At high frequencies, however, the
depletion capacitance associated with the reverse biased substrate-collector junction can cause significant
susceptive loading of the collector port. In Fig. 28.13, the lumped capacitance, Cbb , whose mathematical
definition is similar to that of Cm in Eq. (28.5), provides a first-order account of this collector loading. Observe
that this substrate capacitance appears in series with a substrate resistance, Rbb , which reflects the light doping
nature of the substrate material. For monolithic transistors fabricated on insulating or semi-insulating substrates, Rbb is a very large resistance, thereby rendering Cb b unimportant with respect to the problem of predicting
steady-state transistor responses at high signal frequencies.
A problem that is even more significant than parasitic substrate dynamics stems from the fact that the hybridpi equivalent circuit in Fig. 28.11 is premised on a uniform transistor structure whose emitter-base and basecollector junction areas are identical. In a monolithic device, however, the effective base-collector junction area
is much larger than that of the emitter-base junction because the base region is diffused or implanted into the
collector [Glaser and Subak-Sharpe, 1977]. The effect of such a geometry is twofold. First, the actual value of
Cm is larger than the value predicated on the physical considerations that surround a simplified uniform structure
BJT. Second, Cm is not a single lumped capacitance that is incident with only the intrinsic base-collector junction.
Rather, the effective value of Cm is distributed between the intrinsic collector and the entire base-collector
junction interface. A first-order account of this capacitance distribution entails partitioning Cm in Fig. 28.11
into two capacitances, say Cm1 and Cm2 , as indicated in Fig. 28.13. In general, Cm2 is 3 to 5 times larger than Cm1.
Whereas Cm1 is proportional to the emitter-base junction area, Cm2 is proportional to the net base-collector
junction area, less the area of the emitter-base junction.
© 2000 by CRC Press LLC
FIGURE 28.13 The hybrid-pi equivalent circuit of a monolithic bipolar junction transistor.
Just as Cm1 and Cm2 superimpose to yield the original Cm in the simplified high frequency model of a BJT, the
effective base resistances, Rb1 and Rb2 , sum to yield the original base resistance, Rb . The resistance, Rb1, is the
contact resistance associated with the base lead and the inactive BJT base region. It is inversely proportional to
the surface area of the base contact. On the other hand, Rb2 , which is referred to as the active base resistance,
is nominally an inverse function of emitter finger length. Because of submicron base widths and the relatively
light average doping concentrations of active base regions, Rb2 is significantly larger than Rb1.
Common Emitter Amplifier
The most commonly used canonic cell of linear BJT amplifiers is the common emitter amplifier, whose basic
circuit schematic diagram is depicted in Fig. 28.14(a). In this diagram, RST is the Thévenin resistance of the
applied signal source, VST , and RLT is the effective, or Thévenin, load resistance driven by the amplifier. The
signal source has zero average, or dc, value. Although requisite biasing is not shown in the figure, it is tacitly
assumed that the transistor is biased for linear operation. Hence, the diagram at hand is actually the ac schematic
diagram; that is, it delineates only the signal paths of the circuit. Note that in the common emitter orientation,
the input signal is applied to the base of the transistor, while the resultant small signal voltage response, VOS,
is extracted at the transistor collector.
The hybrid-pi model of Fig. 28.11 forms the basis for the small signal equivalent circuit of the common
emitter cell, which is given in Fig. 28.14(b). In this configuration, the capacitance, Co , represents an effective
output port capacitance that accounts for both substrate loading of the collector port (if the BJT is a monolithic
device) and the net effective shunt capacitance associated with the load.
FIGURE 28.14 (a) AC schematic diagram of a common emitter amplifier. (b) Modified small signal, high frequency
equivalent circuit of common emitter amplifier.
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At low signal frequencies, the capacitors, Cp , Cm , and Co in the model of Fig. 28.14(b), can be replaced by
open circuits. A straightforward circuit analysis of the resultantly simplified equivalent circuit produces analytical expressions for the low frequency values of the small signal voltage gain, A v CE = VO S /VS T ; the driving
point input impedance, ZinCE ; and the driving point output impedance, ZoutCE . Because the Early resistance, Ro ,
is invariably much larger than the resistance sum (Rc + Re + RLT), the low frequency voltage gain of the common
emitter cell is expressible as
é
ù
bac RLT
A vCE (0) @ - ê
ú
êë RST + Rb + R p + (bac + 1)Re úû
(28.12)
For large Ro , conventional circuit analyses also produce a low frequency driving point input resistance of
RinCE = ZinCE(0) @ Rb + Rp + (bac + 1)R e
(28.13)
and a low frequency driving point output resistance of
æ
ö
bac Re
RoutCE = Z outCE (0) @ ç
+ 1÷ Ro
è Re + Rb + R p + RST
ø
(28.14)
At high signal frequencies, the capacitors in the small signal equivalent circuit of Fig. 28.14(b) produce a
third-order voltage gain frequency response whose analytical formulation is algebraically cumbersome [Singhal
and Vlach, 1977; Haley, 1988]. However, because the poles produced by these capacitors are real, lie in the left
half complex frequency plane, and generally have widely separated frequency values, the dominant pole approximation provides an adequate estimate of high frequency common emitter amplifier response in the usable
passband of the amplifier. Accordingly, the high frequency voltage gain, say A v CE(s), of the common emitter
amplifier can be approximated as
é 1 + sT ù
zCE
A vCE (s ) @ A vCE (0) ê
ú
êë 1 + sTpCE úû
(28.15)
In this expression, TpCE is of the form,
TpCE = R CpCp + RCmCm + RCoCo
(28.16)
where R C p, R C m, and RCo , respectively, represent the Thévenin resistances seen by the capacitors, Cp, Cm, and
Co, under the conditions that (1) all capacitors are supplanted by open circuits and (2) the independent signal
generator, VS T , is reduced to zero. Analogously, TzCE is of the form
TzCE = R CpoCp + R CmoCm + RCooCo
(28.17)
where R C po , R C mo, and RCoo, respectively, represent the Thévenin resistances seen by the capacitors, C p , C m, and
Co, under the conditions that (1) all capacitors are supplanted by open circuits and (2) the output voltage
response, VOS , is constrained to zero while maintaining nonzero input signal source voltage. It can be shown
that when Ro is very large and Rc is negligibly small,
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RC p =
R p **(RST + Rb + Re )
bac Re
1+
RST + Rb + R p + Re
(28.18)
RC m = (RLT + Rc ) + {(RST + Rb ) **[R p
é
bac (RLT + Rc ) ù
+(bac + 1)Re ]} ê1 +
ú
R p + (bac + 1)Re úû
êë
(28.19)
and
RCo = RLT
(28.20)
Additionally, R C po = RCoo = 0, and
RC mo = -
R p + (bac + 1)Re
bac
(28.21)
Once TpC E and TzC E are determined, the 3-dB voltage gain bandwidth, BCE , of the common emitter amplifier
can be estimated in accordance with
1
BCE @
æT ö
TpCE 1 - 2ç zCE ÷
è TpCE ø
(28.22)
2
The high frequency behavior of both the driving point input and output impedances, ZinCE(s) and ZoutCE(s),
respectively, can be approximated by mathematical functions whose forms are analogous to the gain expression
in Eq. (28.15). In particular,
é 1 + sTzCE1 ù
Z inCE (s ) @ R inCE ê
ú
êë 1 + sTpCE1 úû
(28.23)
é 1 + sTzCE1 ù
Z outCE (s ) @ RoutCE ê
ú
êë 1 + sTpCE 2 úû
(28.24)
and
where RinCE and RoutCE are defined by Eqs. (28.13) and (28.14). The dominant time constants, TpCE1, TzCE1, TpCE2 ,
and TzCE2 , derive directly from Eqs. (28.16) and (28.17) in accordance with [Choma and Witherspoon, 1990]
[TpCE ]
TpCE1 = R lim
®¥
ST
© 2000 by CRC Press LLC
(28.25)
FIGURE 28.15 (a) AC schematic diagram of a common emitter amplifier using an emitter degeneration resistance.
(b) Small signal, high frequency equivalent circuit of amplifier in part (a).
[TpCE ]
TzCE1 = Rlim
ST ®0
(28.26)
[TpCE ]
TpCE 2 = RLTlim
®¥
(28.27)
[TpCE ]
TzCE 2 = Rlim
LT ® 0
(28.28)
and
For reasonable values of transistor model parameters and terminating resistances, TpCE1 > TzCE1, and TpCE2 >
TzCE2. It follows that both the input and output ports of a common emitter canonic cell are capacitive at high
signal frequencies.
Design Considerations for the Common Emitter Amplifier
Equation (28.12) underscores a serious shortcoming of the canonical common emitter configuration. In particular, since the internal emitter resistance of a BJT is small, the low frequency voltage gain is sensitive to the
processing uncertainties that accompany the numerical value of the small signal beta. The problem can be
rectified at the price of a diminished voltage gain magnitude by inserting an emitter degeneration resistance,
REE, in series with the emitter lead, as shown in Fig. 28.15(a). Since REE appears in series with the internal
emitter resistance, Re , as suggested in Fig. 28.15(b), the impact of emitter degeneration can be assessed analytically by replacing Re in Eqs. (28.12) through (28.28) by the resistance sum (Re + REE). For sufficiently large
RE E , such that
Re + R EE @ R EE >>
RST + Rb + R p
bac + 1
(28.29)
a ac RLT
R EE
(28.30)
the low frequency voltage gain becomes
A vCE (0) @ -
where aac , which symbolizes the small signal, short circuit, common base current gain, or simply the ac alpha,
of the transistor is given by
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a ac =
bac
bac + 1
(28.31)
Despite numerical uncertainties in bac , minimum values of bac are much larger than one, thereby rendering
the voltage gain in Eq. (28.30) almost completely independent of small signal BJT parameters.
A second effect of emitter degeneration is an increase in both the low frequency driving point input and
output resistances. This contention is confirmed by Eq. (28.13), which shows that if Ro remains much larger
than (Rc + Re + REE + RLT), a resistance in the amount of (bac + 1)REE is added to the input resistance established
when the emitter of a common emitter amplifier is returned to signal ground. Likewise, Eq. (28.14) verifies
that emitter degeneration increases the low frequency driving point output resistance. In fact, a very large value
of REE produces an output resistance that approaches a limiting value of (bac + 1)R o . It follows that a common
emitter amplifier that exploits emitter degeneration behaves as a voltage-to-current converter at low signal
frequencies. In particular, its high input resistance does not incur an appreciable load on signal voltage sources
that are characterized by even moderately large Thévenin resistances, while its large output resistance comprises
an almost ideal current source at its output port.
A third effect of emitter degeneration is a decrease in the effective pole time constant, TpCE , as well as an
increase in the effective zero time constant, TzCE , which can be confirmed by reinvestigating Eqs. (28.18)
through (28.21) for the case of Re replaced by the resistance sum (Re + REE ). The use of an emitter degeneration
resistance therefore promotes an increased 3-dB circuit bandwidth. Unfortunately, it also yields a diminished
circuit gain-bandwidth product; that is, a given emitter degeneration resistance causes a degradation in the
low frequency gain magnitude that is larger than the corresponding bandwidth increase promoted by this
resistance. This deterioration of circuit gain-bandwidth product is a property of all negative feedback circuits
[Choma, 1984].
For reasonable values of the emitter degeneration resistance, REE , the Thévenin time constant, R CmCm, is
likely to be the dominant contribution to the effective first-order time constant, TpCE , attributed to the poles
of a common emitter amplifier. Hence, Cm is the likely device capacitance that dominantly imposes an upper
limit to the achievable 3-dB bandwidth of a common emitter cell. The reason for this substantial bandwidth
sensitivity to Cm is the so-called Miller multiplication factor, say M, which appears as the last bracketed term
on the right-hand side of Eq. (28.19), namely,
M = 1+
bac (RLT + Rc )
R p + (bac + 1)Re
(28.32)
The Miller factor, M, which effectively multiplies Cm in the expression for RCmCm, increases sharply with the
load resistance, RLT , and hence with the gain magnitude of the common emitter amplifier. Note that in the
limit of a large emitter degeneration resistance (which adds directly to Re), Eq. (28.30) reduces Eq. (28.32) to
the factor
M @ 1 + *AvCE(0)*
(28.33)
Common Base Amplifier
A second canonic cell of linear BJT amplifiers is the common base amplifier, whose ac circuit schematic diagram
appears in Fig. 28.16(a). In this diagram, RST , VST , RLT , and VOS retain the significance they respectively have
in the previously considered common emitter configuration. Note that in the common base orientation, the
input signal is applied to the base, while the resultant small signal voltage response is extracted at the collector
of a transistor.
The relevant small signal model is shown in Fig. 28.16(b). A straightforward application of Kirchhoff ’s circuit
laws gives, for the case of large Ro , a low frequency voltage gain, A vCB(0) = VO S /VS T , of
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FIGURE 28.16 (a) AC schematic diagram of a common base amplifier. (b) Small signal, high frequency equivalent circuit
of amplifier in part (a).
A vCB (0) @
a ac RLT
RST + R inCB
(28.34)
where RinCB is the low frequency value of the common base driving point input impedance,
R inCB = Z inCB (0) @ Re +
Rb + R p
bac + 1
(28.35)
Moreover, it can be shown that the low frequency driving point output resistance is
é
ù
bac (Re + RST )
RoutCB = Z outCB (0) @ ê
+ 1úRo
êë Re + Rb + R p + RST
úû
(28.36)
The preceding three equations underscore several operating characteristics that distinguish the common base
amplifier from its common emitter counterpart. For example, Eq. (28.35) suggests a low frequency input
resistance that is significantly smaller than that of a common emitter unit. To underscore this contention,
consider the case of two identical transistors, one used in a common emitter amplifier and the other used in
a common base configuration, that are biased at identical quiescent operating points. Under this circumstance,
Eqs. (28.35) and (28.13) combine to deliver
R inCB @
R inCE
bac + 1
(28.37)
which shows that the common base input resistance is a factor of (bac + 1) times smaller than the input resistance
of the common emitter cell. The resistance reflection factor, (bac + 1), in Eq. (28.37) represents the ratio of
small signal emitter current to small signal base current. Accordingly, Eq. (28.37) is self-evident when it is noted
that the input resistance of a common base stage is referred to an input emitter current, whereas the input
resistance of its common emitter counterpart is referred to an input base current.
A second difference between the common emitter and common base amplifiers is that the voltage gain of
the latter displays no phase inversion between source and response voltages. Moreover, for the same load and
source terminations and for identical transistors biased identically, the voltage gain of the common base cell is
likely to be much smaller than that of the common emitter unit. This contention is verified by substituting
Eq. (28.37) into Eq. (28.34) and using Eqs. (28.31), (28.13), and (28.12) to write
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A vCB (0) @
* A vCE (0) *
bac RST
1+
RST + R inCE
(28.38)
At high signal frequencies, the voltage gain, driving point input impedance, and driving point output
impedance can be approximated by functions whose analytical forms mirror those of Eqs. (28.15), (28.23), and
(28.24). Let TpCB and TzCB designate the time constants of the effective dominant pole and the effective dominant
zero, respectively, of the common base cell. An analysis of the structure of Fig. 28.16(b) resultantly produces,
with Ro and Rc ignored,
TpCB = R Cp Cp + R CmCm + RCoCo
(28.39)
where
RC p =
R p * * (R ST + R b + Re )
bac (RST + Re )
1+
RST + Rb + R p + Re
(28.40)
RC m = Rb * * [R p + (bac + 1)(RST + Re )]
é
ù
bac Rb
+ RLT ê1 +
ú
Rb + R p + (bac + 1)(RST + Re ) úû
êë
(28.41)
and RCo remains given by Eq. (28.20). Moreover,
TzCB =
R bC m
a ac
(28.42)
Design Considerations for the Common Base Amplifier
An adaptation of Eqs. (28.25) through (28.28) to the common base stage confirms that the driving point input
impedance is capacitive at high signal frequencies. On the other hand, gmRb > 1 renders a common base driving
point input impedance that is inductive at high frequencies. This impedance property can be gainfully exploited
to realize monolithic shunt peaked amplifiers in which the requisite circuit inductance is synthesized as the
driving point input impedance of a common base stage (or the driving point output impedance of a common
collector cell) [Grebene, 1984].
The common base stage is often used to broadband the common emitter amplifier by forming the common
emitter–common base cascode, whose ac schematic diagram is given in Fig. 28.17. The broadbanding afforded
by the cascode structure stems from the fact that the effective low frequency load resistance, say RLe , seen by
the common emitter transistor, QE, is the small driving point input resistance of the common base amplifier,
QB. This effective load resistance, as witnessed by Cm of the common emitter transistor, is much smaller than
the actual load resistance that terminates the output port of the amplifier, thereby decreasing the Miller
multiplication of the Cm in QE. If the time constant savings afforded by decreased Miller multiplication is larger
than the sum of the additional time constants presented to the circuit by the common base transistor, an
enhancement of common emitter bandwidth occurs. Note that such bandwidth enhancement is realized without
compromising the common emitter gain-bandwidth product, since the voltage gain of the common emitter–common base unit is almost identical to that of the common emitter amplifier alone.
© 2000 by CRC Press LLC
FIGURE 28.17 AC schematic diagram of a common emitter–common base cascode amplifier.
Common Collector Amplifier
The final canonic cell of linear BJT amplifiers is the common collector amplifier. The ac schematic diagram of
this stage, which is often referred to as an emitter follower, is given in Fig. 28.18(a). In emitter followers, the
input signal is applied to the base, and the resultant small signal output voltage is extracted at the transistor
emitter.
The small signal equivalent circuit corresponding to the amplifier in Fig. 28.18(a) is shown in Fig. 28.18(b).
A straightforward circuit analysis gives, for the case of large Ro , a low frequency voltage gain, A vCC (0) = VO S /VS T ,
of
A vCC (0) @
RLT
RLT
+ RoutCC
(28.43)
where RoutCC is the low frequency value of the driving point output impedance,
RoutCC = Z outCC (0) @ Re +
Rb + R p + RST
bac + 1
(28.44)
The low frequency driving point output resistance is
RinCC = ZinCC(0) @ Rb + Rp + (bac + 1)(Re+ RLT)
(28.45)
FIGURE 28.18 (a) AC schematic diagram of a common collector (emitter follower) amplifier. (b) Small signal, high
frequency equivalent circuit of amplifier in part (a).
© 2000 by CRC Press LLC
The facts that the voltage gain is less than one and is without phase inversion, the output resistance is small,
and the input resistance is large make the emitter follower an excellent candidate for impedance buffering
applications.
As in the cases of the common emitter and the common base amplifiers, the high frequency voltage gain,
driving point input resistance, and driving point output resistance can be approximated by functions having
analytical forms that are similar to those of Eqs. (28.15), (28.23), and (28.24). Let TpCC and TzCC designate the
time constants of the effective dominant pole and the effective dominant zero, respectively, of the emitter
follower. Since the output port capacitance, Co , appears across a short circuit, TpCC is expressible as
TpCC = R Cp Cp + R CmCm
(28.46)
With Ro ignored,
RC p =
R p * * (R ST + R b + RLT + Re )
bac (RLT + Re )
1+
RST + Rb + R p + RLT + Re
(28.47)
and
RC m = (RST + Rb ) * * [R p + (bac + 1)(RLT + Re )
é
ù
bac (RST + Rb )
+ ê1 +
ú Rc
RST + Rb + R p + (bac + 1)(RLT + Re ) úû
êë
(28.48)
The time constant of the effective dominant zero is
TzCC =
R pC p
bac + 1
(28.49)
Although the emitter follower possesses excellent wideband response characteristics, it should be noted in
Eq. (28.48) that the internal collector resistance, R c, incurs some Miller multiplication of the base-collector
junction capacitance, Cm. For this reason, monolithic common collector amplifiers work best in broadband
impedance buffering applications when they exploit transistors that have collector sinker diffusions and buried
collector layers, which collectively serve to minimize the parasitic internal collector resistance.
Defining Terms
ac schematic diagram: A circuit schematic diagram, divorced of biasing subcircuits, that depicts only the
dynamic signal flow paths of an electronic circuit.
Driving point impedance: The effective impedance presented at a port of a circuit under the condition that
all other circuit ports are terminated in the resistances actually used in the design realization.
Hybrid-pi model: A two-pole linear circuit used to model the small signal responses of bipolar circuits and
circuits fabricated in other device technologies.
Miller effect: The deterioration of the effective input impedance caused by the presence of feedback from the
output port to the input port of a phase-inverting voltage amplifier.
Short circuit gain-bandwidth product: A measure of the frequency response capability of an electronic
circuit. When applied to bipolar circuits, it is nominally the signal frequency at which the magnitude of
the current gain degrades to one.
© 2000 by CRC Press LLC
Three-decibel bandwidth: A measure of the frequency response capability of low-pass and bandpass electronic circuits. It is the range of signal frequencies over which the maximum gain of the circuit is constant
to within a factor of the square root of two.
Related Topic
24.2 Bipolar Transistors
References
W.K. Chen, Circuits and Filters Handbook, Boca Raton, Fla: CRC Press, 1995.
J. Choma, “A generalized bandwidth estimation theory for feedback amplifiers,” IEEE Transactions on Circuits
and Systems, vol. CAS-31, Oct. 1984.
J. Choma and S. Witherspoon, “Computationally efficient estimation of frequency response and driving point
impedances in wide-band analog amplifiers,” IEEE Transactions on Circuits and Systems, vol. CAS-37,
June 1990.
K.K. Clarke and D.T. Hess, Communication Circuits: Analysis and Design, Reading, Mass.: Addison-Wesley, 1978.
H.C. de Graaf, “Two New Methods for Determining the Collector Series Resistance in Bipolar Transistors With
Lightly Doped Collectors,” Phillips Research Report, 24, 1969.
A.B. Glaser and G.E. Subak-Sharpe, Integrated Circuit Engineering: Design, Fabrication, and Applications, Reading, Mass.: Addison-Wesley, 1977.
A.B. Grebene, Bipolar and MOS Analog Integrated Circuit Design, New York: Wiley Interscience, 1984.
H.K. Gummel and H.C. Poon, “An integral charge-control model of bipolar transistors,” Bell System Technical
Journal, 49, May–June 1970.
S. B. Haley, “The general eigenproblem: pole-zero computation,” Proc. IEEE, 76, Feb. 1988.
J.D. Irwin, Industrial Electronics Handbook, Boca Raton, Fla.: CRC Press, 1997.
A.S. Sedra and K.C. Smith, Microelectronic Circuits, 3rd ed., New York: Holt, Rinehart and Winston, 1991.
K. Singhal and J. Vlach, “Symbolic analysis of analog and digital circuits,” IEEE Transactions on Circuits and
Systems, vol. CAS-24, Nov. 1977.
Further Information
The IEEE Journal of Solid-State Circuits publishes state-of-the-art articles on all aspects of integrated electronic
circuit design. The December issue of this journal focuses on analog electronics.
The IEEE Transactions on Circuits and Systems also publishes circuit design articles. Unlike the IEEE Journal
of Solid-State Circuits, this journal addresses passive and active, discrete component circuits, as well as integrated
circuits and systems, and it features theoretic research that underpins circuit design strategies.
The Journal of Analog Integrated Circuits and Signal Processing publishes design-oriented papers with emphasis
on design methodologies and design results.
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