CME-M5 Family
Data Sheet
September 2014
Capital Microelectronics Co., Ltd.
CME-M5 Family Data Sheet
Notes
Copyright © 2014 Capital Microelectronics,
Inc. All rights reserved.
No part of this document may be copied,
transmitted, transcribed, stored in a retrieval
system, or translated into any language or
computer language, in any form or by any
means, electronic, mechanical, magnetic,
optical, chemical, manual or otherwise, without
the written permission of Capital
Microelectronics, Inc. All trademarks are the
property of their respective companies.
Version Part Number
CME-M5DSE08
Contact Us
If you have any problems or requirements
during using our product, please contact
Capital Microelectronics, Inc. or your local
distributors, or send e-mail to
sales@capital-micro.com
Environmental Considerations
To avoid the harmful substances being
released into the environment or harming
human health, we encourage you to recycle this
product in an appropriate way to make sure that
most of the materials are reused or recycled
appropriately. Please contact your local
authorities for disposal or recycle information.
Warranty
The information in this document has been
carefully checked and is believed to be entirely
reliable. However, no responsibility is assumed for
inaccuracies. Furthermore, Capital
Microelectronics, Inc. reserves the right to
discontinue or make changes, without prior notice,
to any products herein to improve reliability,
function, or design.
Capital Microelectronics, Inc. advises its
customers to obtain the latest version of the
relevant information to verify, before placing
orders, that the information being relied upon is
current.
The product introduced in this book is not
authorized for use as critical components in life
support devices or systems without the express
written approval of Capital Microelectronics, Inc.
As used herein: 1. Life support devices or systems
are devices or systems that (a) are intended for
surgical implant into the body or (b) support or
sustain life, and whose failure to perform, when
properly used in accordance with instructions for
use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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1
CME-M5 Family Data Sheet
Revision History
The table below shows the revision history for this document.
Date
Version
June 2012
1.0
Initial release.
July 2012
1.1
First updated.
October 2012
CME-M5DSE03
November 2012
CME-M5DSE04
IO38/MSEL_2->IO39/MSEL_2
EMIF Read Waveform modified
CME-M5DSE05
Update the MSS peripheral information;
Update the Device-package, see Table 2;
Add the information about GUBF, see section GBUF;
Update figures: Figure 1, Figure 24, etc.;
Revise bugs in the manual.
CME-M5DSE06
Add QFN68 Pin Package, see P75 and P79
The Temperature Range in Industrial level is changed
from (TJ = -40°C to +100°C) to (TJ = -40°C to +125°C),
see P82;
In SDR mode, the read port 256x16 does not support the
following write ports:
4K × 1, 2K × 2, 1K × 4 and 512 × 8, see Table 8;
ISCHEADER3 is updated from 0x2A to 0x22, see
ISCHEADER3 = 0x22;
The max TD Junction temperature is corrected from -85°C
to 125°C, see Table 37.
CME-M5DSE07
Update dimensions of LQFP144 Low-profile Quad
Flat-Pack Package Specifications, TQFP100 Thin
Quad Flat-Pack Package Specifications and QFN68
Package Specifications;
Update the 9 Ordering Information;
Correct the formula of PLL configuration in section of
MSS in System Clock Configuration;
Change the Pins of QFN68 Package Pin List:
Pin 20 is changed from IO15_0 to IO15_1;
Pin 21 is changed from IO16_0 to IO16_1;
Pin 22 is changed from IO17_0 to IO17_1;
Pin 23 is changed from IO18_0 to IO18_1;
April 2013
November 2013
March 2014
Revision
Update new device name and FBGA256 package
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2
CME-M5 Family Data Sheet
Date
September 2014
Version
Revision
CME-M5DSE08
Update Table 39 Supply Voltage Ramp Rate:
The minimum Supply Voltage Ramp Rate of VCCINT is
changed from 10us to 10ms and the VCCINT must be
powered to threshold before the VCCIO.
Add Figure 38 Power on waveform.
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3
CME-M5 Family Data Sheet
Table of Contents
Notes .......................................................................................................................................................... 1
Revision History ....................................................................................................................................... 2
Table of Contents ..................................................................................................................................... 4
Before You Start........................................................................................................................................ 7
About this Guide.................................................................................................................................. 7
CME-M5 Family FPGA Introduction.................................................................................................... 7
1
CME-M5 Family FPGA Features ...................................................................................................... 8
1.1
1.2
2
CME-M5 Family FPGA Feature Summary ........................................................................... 9
Architecture Overview ........................................................................................................ 10
FPGA ................................................................................................................................................ 12
2.1
2.1.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.4
2.4.1
2.4.2
2.5
2.5.1
2.6
2.6.1
Programmable Logic Block (PLB) ...................................................................................... 12
LP................................................................................................................................... 12
(1) Look-Up Table ............................................................................................................ 13
(2) Register ...................................................................................................................... 13
(3) Carry, Cascade and Arithmetic Logic ........................................................................ 13
LE ....................................................................................................................................... 14
(1) LE Cascade ............................................................................................................... 14
(2) LE Carry and Skip ...................................................................................................... 14
(3) LE Shift....................................................................................................................... 14
Embedded Memory Block .................................................................................................. 14
EMB5K Port Definitions ................................................................................................. 15
EMB5K Operations ........................................................................................................ 16
EMB5K Operation Mode................................................................................................ 17
(1) EMB5K True Dual-port............................................................................................... 17
(2) EMB5K Simple Dual-port ........................................................................................... 18
(3) EMB5K Single-port .................................................................................................... 19
Conflict Avoidance ......................................................................................................... 20
DSP Block........................................................................................................................... 20
DSP Primitive................................................................................................................. 20
DSP Usage Mode .......................................................................................................... 22
(1) Multiplier ..................................................................................................................... 23
(2) Multiplier and adder ................................................................................................... 23
(3) Multiplier and Accumulator......................................................................................... 24
Embedded Single Port SRAM ............................................................................................ 24
SRAM Port Definitions ................................................................................................... 24
Input/output Blocks ............................................................................................................. 25
Pull-Up/Down/Keeper Resistors .................................................................................... 27
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CME-M5 Family Data Sheet
2.6.2
2.6.3
2.6.4
2.6.5
2.7
2.8
2.8.1
2.8.2
2.8.3
2.8.4
2.9
2.9.1
2.9.2
2.9.3
2.9.4
3
MSS Subsystem .............................................................................................................................. 39
3.1
3.1.1
3.2
3.3
3.4
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
4
ESD Protection .............................................................................................................. 27
Drive Strength ................................................................................................................ 27
The Organization of IOBs into Banks ............................................................................ 27
The I/Os During Power-On, Configuration, and User Mode ......................................... 28
Interconnect ........................................................................................................................ 28
PLL ..................................................................................................................................... 29
PLL features................................................................................................................... 29
PLL Hardware Description ............................................................................................. 29
PLL Primitive Port Signal Definitions ............................................................................. 30
Clock Feedback Modes ................................................................................................. 32
(1) Internal Feedback Mode (Frequency Synchronous Mode) ....................................... 33
(2) External Feedback Mode ........................................................................................... 33
Global Clock & Reset Resources ....................................................................................... 34
External Crystal Input .................................................................................................... 35
Clocking Infrastructure................................................................................................... 35
GBUF ............................................................................................................................. 36
Clock Switch .................................................................................................................. 37
8051 Instantiation ............................................................................................................... 40
8051 Macro Primitive Description.................................................................................. 40
Multiplex of P Port Pins ...................................................................................................... 42
MSS Clock Description ....................................................................................................... 43
MSS Memory Map .............................................................................................................. 43
MSS External Memory Interface (EMIF) ............................................................................ 44
(1) Synchronous EMIF .................................................................................................... 44
(2) Asynchronous EMIF .................................................................................................. 45
RTC..................................................................................................................................... 46
MSS in System Management ............................................................................................. 47
Device Register ............................................................................................................. 47
ISC Register Frame ....................................................................................................... 48
Extended SFR ............................................................................................................... 48
MSS In System Configuration ....................................................................................... 49
MSS in System Clock Configuration ............................................................................. 51
(1) PLL Configuration ...................................................................................................... 51
(2) GCLK Dynamic Switch .............................................................................................. 51
(3) MSS Clock Dynamic Switch ...................................................................................... 52
Configuration and Debug ............................................................................................................... 53
4.1
Configuration Mode ............................................................................................................ 53
4.1.1
AS Mode ........................................................................................................................ 53
4.1.2
PS Mode ........................................................................................................................ 54
4.1.3
JTAG Mode .................................................................................................................... 55
4.2
SPI Flash ............................................................................................................................ 55
(1) Using embedded SPI-Flash ....................................................................................... 55
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CME-M5 Family Data Sheet
(2) Using External SPI-Flash........................................................................................... 56
ISC ...................................................................................................................................... 56
Debug ................................................................................................................................. 56
Power-On-Reset (POR) ..................................................................................................... 56
eFUSE Program ................................................................................................................. 57
4.3
4.4
4.5
4.6
5
Security ............................................................................................................................................ 58
5.1
Bitstream Generation Security Level .................................................................................. 58
(1) prot_flagn ................................................................................................................... 58
(2) read_disable0 ............................................................................................................ 59
(3) read_disable1 ............................................................................................................ 59
On-Chip eFuse ................................................................................................................... 59
Embedded SPI-Flash Hidden Bitstream ............................................................................ 59
AES Security ...................................................................................................................... 60
5.2
5.3
5.4
6
DC & Switching Characteristics .................................................................................................... 61
6.1
6.1.1
6.1.2
6.1.3
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
7
DC Electrical Characteristics .............................................................................................. 61
Absolute Maximum Ratings ........................................................................................... 61
Power Supply Specifications ......................................................................................... 61
General Recommended Operating Conditions ............................................................. 62
Switching Characteristics ................................................................................................... 65
Clock Performance ........................................................................................................ 66
I/O Performance ............................................................................................................ 66
PLB Performance .......................................................................................................... 66
EMB5K Performance ..................................................................................................... 66
DSP Performance .......................................................................................................... 67
Pins and Package............................................................................................................................ 68
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.3
7.3.1
7.3.2
7.3.3
7.3.4
Pins Definitions and Rules ................................................................................................. 68
Pin List ................................................................................................................................ 69
LQFP144 Package Pin List ........................................................................................... 69
TQFP100 Package Pin List ........................................................................................... 72
FBGA256 Package Pin List ........................................................................................... 73
QFN68 Package Pin List ............................................................................................... 76
Package Information .......................................................................................................... 77
LQFP144 Low-profile Quad Flat-Pack Package Specifications.................................... 77
TQFP100 Thin Quad Flat-Pack Package Specifications .............................................. 78
FBGA256-Pin FineLine Ball-Grid Array (FBGA) – THIN – Wire Bond.......................... 79
QFN68 Package Specifications..................................................................................... 80
8
Developer Kits ................................................................................................................................. 81
9
Ordering Information ...................................................................................................................... 82
10
Legends ...................................................................................................................................... 84
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6
CME-M5 Family Data Sheet
Before You Start
About this Guide
This guide is only a part of an overall of documentation on CME-M5 family FPGA. It serves as a
technical reference guiding you to be familiar with the CME-M5 family FPGA module with its heart
functions and characteristics.
The CME-M5 Family FPGA consists of CME-M5 C, CME-M5 R and CME-M5 P series FPGA
modules. And this manual is available for all modules contained in this family except where
noted.
For the detailed information of this family module, please go to http://www.capital-micro.com.
Note:
CME-M5 Family FPGA is just a name that replaces the manuals of CME3000-M and CME3000-C FPGA
Data Sheet.
CME-M5 Family FPGA Introduction
CME-M5 family FPGA has C, R and P three series devices.
The C series devices are an intelligent device integrated enhanced 8051 MCU and high performance
FPGA, which can fulfill customized system design and IP protection (128 bit AES). Embedded optimized
RAM confers the highest speed and performance on 8051 processor hardcore. Designers can design
FPGA with CME’s Primace as well as embedded design with third party EDA tool KeilTM conveniently
and quickly. Based on CME-M5 single chip, CAP (Configurable Application Platform on chip) is ideal for
hardware and embedded designers who need a true system-on-chip (SoC) solution that gives more
flexibility than traditional fixed-function microcontrollers and is more cost-efficient than FPGAs-without
the excessive cost of soft processor cores on traditional FPGAs.
The R series devices are with no hard MCU core and P series devices are special for tradition FPGA
application with no hard MCU core and large embedded SRAM.
The three series FPGA can be used widely in industry, medical, communication system,
consumer electronics, etc.
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7
CME-M5 Family Data Sheet
1 CME-M5 Family FPGA Features
FPGA






SRAM-based FPGA Fabric
Up to 6144 4-input Look-up Tables, 4096
DFF-based registers
Performance up to 250MHz
Embedded RAM Block Memory
32 4.5Kbit programmable dual-port
DPRAM memory EMB5K blocks
Embedded DSPs block
16 18x18 DSP (MAC) blocks
Clock Network
8 de-skew global clocks
2 PLLs support frequency multiplication,
frequency division, phase-shifting,
de-skew
8 external input clocks, 1 external crystal
clock input
I/O
3.3/2.5/1.8/1.5V LVTTL/LVCMOS support
Programmable Pull-Up, Pull down and
Bus Keeper control
Programmable driver strength: 2, 4, 8, 12,
16 mA
Level slope ratio control

Configuration



MSS



Enhanced 8051 MCU
Reduced instruction cycle time (Up to 12
times in respect to standard 8051),
frequency up to 200MHz
Compatible to 8051 instruction system
Support up to 8MB data/code memory
extension
Support hardware 32/16-bit MDU
On-chip debugger system (OCDS)
8-channel DMA
Embedded SRAM Memory
128KByte single-port SRAM
Data/code unified addressing, flexible
memory configuration
Peripheral
3 16-bit Timers
1 I2C interface
1 SPI interface
Master rate up to 100Mb/s @200MHz
Slave rate up to 25Mb/s @200MHz
2 Full Duplex Serial Interfaces, the rate is
up to 6.25Mb/s @200MHz
Enhanced hardware operation unit
supports multiplication, division, skip and
normalization.
STOP, IDLE Mode Power Management
In System Management
ISC Control
Dynamic clock management in system
Configuration Mode
JTAG Mode
AS Mode
PS Mode
JTAG Interface
JTAG Chip Configuration
JTAG 8051 Debugging
Dynamic/Multi-configuration Image Support
Security



Encrypted Bitstream with 128-bit AES
Based Efuse and SPI Flash security settings
control accessing the device memory
Protection against copying, overbuilding,
cloning and tampering with both of
customer's FPGA and 8051 firmware IP
Package




TQFP-100
LQFP-144
FBGA-256
QFN-68
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8
CME-M5 Family Data Sheet
1.1 CME-M5 Family FPGA Feature Summary
Table 1 CME-M5 C Series FPGA Feature Summary
Series
C
R
P
Device (1)
LUT
Programmable
Embedded
Logic
Memory
SRAM
Block(PLB) (2)
Block
(3)
LP
Register
4.5Kb
Max
DSP
Max
Block
PLL
Flash
MCU
User
(4)
I/O
M5C03N0
3072
1024
2048
32
144Kb
128KB
16
2
-
1
186
M5C06N0
6144
2048
4096
32
144Kb
128KB
16
2
-
1
186
M5C03N3
3072
1024
2048
32
144Kb
128KB
16
2
4Mb
1
186
M5C06N3
6144
2048
4096
32
144Kb
128KB
16
2
4Mb
1
186
M5R03N0
3072
1024
2048
32
144Kb
128KB
16
2
-
-
186
M5R06N0
6144
2048
4096
32
144Kb
128KB
16
2
-
-
186
M5R03N3
3072
1024
2048
32
144Kb
128KB
16
2
4Mb
-
186
M5R06N3
6144
2048
4096
32
144Kb
128KB
16
2
4Mb
-
186
M5P03N0
3072
1024
2048
32
144Kb
-
16
2
-
-
186
M5P06N0
6144
2048
4096
32
144Kb
-
16
2
-
-
186
M5P03N3
3072
1024
2048
32
144Kb
-
16
2
4Mb
-
186
M5P06N3
6144
2048
4096
32
144Kb
-
16
2
4Mb
-
186
Note:
(1) C: FPGA + SRAM (used by MCU) + MCU; R: FPGA + SRAM; P: FPGA.
‘N0’: indicates device contains no Flash, ‘N3 ’indicates that device contains 4Mb Flash.
(2) Each CME-M5 PLB contains 4 LPs (Logic parcel). Each LP contains 3 LUTs, 2 registers.
(3) M5CXX series devices: SRAM could only be used by MCU; M5RXX series devices: SRAM could be
used by FPGA.
(4) Each DSP Block contains an 18 x 18 multiplier with 41 bits accumulator, an adder. Each DSP Block
can also support 2 independent 12 x 9 multipliers with 21 bits accumulator.
Table 2 CME-M5 FPGA Device-Package and Available I/Os
Package
TQFP100
LQFP144
FBGA256
QFN68
Pitch(mm)
0.5
0.5
1.0
0.4
Body Size(mm)
16 x 16
22 x 22
17 x 17
8x8
Device
User I/O
User I/O
User I/O
User I/O
M5x03N0
69
100
186
46
M5x06N0
69
100
186
46
M5x03N3
69
100
186
46
M5x06N3
69
100
186
46
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CME-M5 Family Data Sheet
1.2 Architecture Overview
The CME-M5 FPGA architecture consists of 5 fundamental programmable functional tiles and an
enhanced 8051 MSS. The PLBs, IOBs, EMB, DSPs and PLLs make up the FPGA. The enhanced 8051
and SRAM make up the MSS. The EMB and DSP can be called as special function block (SFB).







Programmable Logic Blocks (PLBs) contain RAM-based Look-Up Tables (LUT-4) to implement
logic and storage elements that can be used as flip-flops. PLBs can be programmed to perform a
wide variety of logical functions as well as to store data.
Embedded Memory Block provides data storage in the form of 4.5K bit dual-port blocks.
DSPs accept two 18-bit binary numbers as inputs and calculate the product. The DSP block
includes special DSP multiply-accumulate blocks.
Phase (PLL) blocks provide self-calibrating, fully digital solutions for distributing, delaying,
multiplying, dividing, and phase shifting clock signals.
Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus 3-state operation.
The monocycle enhanced 8051 CPU is used as central processing unit, whose instruction set is
compatible with standard ASM51 completely.
The embedded 128KB SRAM is only used as the 8051 coding and data memory for C Series
devices.
These elements are organized as shown in figure below. A ring of IOBs surrounds a regular array of
PLBs. The CME-M5 family FPGA has a single column of block EMB and DSP in the array. The PLLs and
GCLK_CTRL blocks are positioned at the top and bottom right corner. The 8051 and SRAM memory are
laid out at the right side of the diagram. All these elements include the Xbars that interconnect the
functional elements, transmitting signals among them.
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10
CME-M5 Family Data Sheet
IOBs
C1
r31
C2
PLB
PLB
C3
PLB
PLB
C4
PLB
PLB
C5
PLB
PLB
PLB
PLB
C6
PLB
PLB
C7
C8
PLB PLB
200um
PLB
C9
C1
0
PLB
C1
1
PLB
C1
2
PLB
C1
C1
3
4
PLB
300um
PLB
PLB
PLB
PLB
MAC
PLB
C1
C1
C1
C1
C1
5
6
7
8
9
PLB PLB PLB PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
GCLK_Ctrl
PLL
EMB
r30
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
MAC
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r27
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r26
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r29
r28
RTC analog
r32
RTC
Digital
MAC
EMB
MAC
r25
r24
r23
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
MAC
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
64KB SRAM
EMB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r21
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r20
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r19
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r18
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
MAC
8051
PLB
r22
MAC
EMB
MAC
IOBs
r17
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r16
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r15
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r14
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r13
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
IOBs
MAC
EMB
r12
r11
r10
MAC
MAC
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
MAC
r9
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r8
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
r7
64KB SRAM
EMB
SPI
Config /
JTAG
MAC
EMB
r6
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
MAC
r5
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
MAC
EMB
r2
r1
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
GCLK_Ctrl
MAC
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLB
PLL
Efuse ESD
r4
r3
PLB
IOBs
Figure 1 CME-M5 FAMILY FPGA Architecture
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11
CME-M5 Family Data Sheet
2 FPGA
The CME-M5 FAMILY FPGA consists of up to 512 PLBs, 32 EMB5K blocks, 16 18x18 DSPs and 2 PLLs.
This chapter describes these element blocks.
2.1 Programmable Logic Block (PLB)
The Programmable Logic Block (PLB) is the fabric basic logic tile that is composed of LE and Xbar. The
PLB is the basic tile of the Fabric. Their organization is shown in the following figure. One LE contains
four interconnected Logic Parcels (LP). The LE constitutes the main logic resource for implementing
synchronous as well as combinatorial circuits.
The Xbar switches and passes the signals between the tile elements.
LP3
LE
LP2
Xbar
LP1
LP0
PLB
Figure 2 PLB Schematic Diagram
The PLBs are arranged in a regular array of rows and columns, as shown in Figure 1.
The CME development software designates the location of a PLB according to its C and R coordinates,
starting in the bottom left corner, as shown in Figure 1. The letter ‘C’ followed by a number identifies
columns of PLBs, incrementing from the left side of the die to the right. The letter ‘R’ followed by a
number identifies the position of each PLB in the CLB row, incrementing from the bottom of the die.
2.1.1
LP
LP is the basic programmable logic element. The LP has the following elements to provide logic,
arithmetic functions, as shown in the figure below.
 Three 4-input LUT function generators
 Two registers
 Carry, cascade and arithmetic logic
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12
CME-M5 Family Data Sheet
carry output
shift up/down
dx4b
fast cascade to next LP above
fast cascade to next PLB
din[1:0]
f0[8]
f1[8]
f2[8]
LUT5
Gen
byp[8]
dy[0]
LUT4
di
4_1
qx[4]
shift
din[1]
a_sr
en
4
Cascade Gen
LUT5
Gen
byp[12]
f0[4]
f1[4]
f2[4]
fast cascades
from prev PLB
fy[0]
dx[4]
LUT4C
4_0
din[0]
di
byp[4]
en
f0[0]
f1[0]
f2[0]
Lut5 cascades
from next LP up
0
LUT4
Cascad
e Gen
byp[0]
qx[0]
shift
a_sr
dx[0]
0
fx4b
carry input
shift[1:0]
clk
shift up/down
Figure 3 LP Schematic Diagram
(1) Look-Up Table
The Look-Up Table or LUT is a RAM-based function generator and is the main resource for
implementing logic functions. Each of the three LUTs in a LP has four logic inputs (f0-f3) and a single
output (d). Any four-variable Boolean logic operation can be implemented in one LUT. Functions with
more inputs can be implemented by cascading LUTs that are in one LP or adjacent LPs.
(2) Register
The register is a programmable D-type flip-flop. There are two level multiplexers on the D input select of
the registers. The first level multiplexer selects either the LUT combinatorial output or the bypass signal
byp[x]. The second level multiplexer selects either the first level multiplexer output signal byp[x] or signal
shift. The shift signal is from the next up/down relative register output qx.
The storage element output, qx, offers three possible paths:
 Drives the interconnect line directly
 Feedbacks to the LUT input
 Cascade to the next up/down relative storage element signal shift
(3) Carry, Cascade and Arithmetic Logic
The vertical up cascading from near down LP feeds the LUT0 input, the LUT40 or LUT41 generates the
cascading output. Functions with more inputs can be implemented by cascading LUTs between PLBs.
The carry chain, together with various dedicated arithmetic logic gates, support fast and efficient
implementations of math operations such as adders, counters, comparators, multipliers, wide logic gates,
and related functions. The carry logic is automatically used for most arithmetic functions in a design. The
gates and multiplexers of the carry and arithmetic logic can also be used for general-purpose logic,
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13
CME-M5 Family Data Sheet
including simple wide Boolean functions.
The carry input from LUT40 of the near down LP enters the LUT40 and the LUT40 generates the carry
out which can be cascaded to next up LUT40.
2.2 LE
The LE contains 4 LPs and Carry Ship, Register Control circuitry which make LE implement many
complex functions, such as cascading, Carry and Skip, LE Shift. These functions provide higher
performance and lower resources usage than normal LUT implemented because these connections are
hardware logic and connections.
(1) LE Cascade
The LEs can be cascaded vertically and horizontally to implement large and complex functions.
(2) LE Carry and Skip
The LEs can implement flexible carry function with skip 4 and skip 8 fast carry logics.
(3) LE Shift
The LE registers can be cascaded to implement the register shift up or down vertically with next up LE
register.
2.3 Embedded Memory Block
CME-M5 family device supports embedded memory block (EMB), which is organized as one column
total 32 4.5Kbit EMB5K. EMB5K module is a true dual-port memory that permits independent access to
the common EMB block. Each port has its own dedicated set of data, control and clock lines for
synchronous read and writes operations. EMB5K provides the features as below:
 4.5Kbits
 Mixed clock mode
 A, B data width configured independently
 Support write data through output
 Parity bit. The EMB5K blocks support a parity bit for each byte. The parity bit, along with internal LC,
can implement parity checking for error detection to ensure data integrity. Parity-sized data words
can be used to store user-specified control bits.
 Initialization support. The format of initialization file is either .hex or .dat (a hexadecimal number
each line, the number of lines depends on depth of EMB5K). Initialization files initialize EMB5K
memory during configuration.
 Two EMB5K cascade
 Three Memory Modes available. EMB5K can be configured into the following modes:
- emb_tdp
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CME-M5 Family Data Sheet
-
emb_sdp
emb_sp
2.3.1
EMB5K Port Definitions
The dual-port primitive EMB5K signals are defined in the following table.
Table 3 EMB5K Port Definition
Port Name
Type
Width
Description
clka
I
1
Input clock for port A
cea
I
1
Chip enable for port A
wea
I
1
Write enable for port A
aa
I
12
Address line for port A
da
I
18
Data input for port A
clkb
I
1
Input clock for port B
ceb
I
1
Chip enable for port B
web
I
1
Wire enable for port B
ab
I
12
Address line for port B
db
I
18
Data input for port B
q
O
18
Memory data q output
wq_in
I
9
Input from paired EMB5K for wide true dual port mode
wq_out
O
9
Output to paired EMB5K for wide true dual port mode
Table 4 EMB5K Parameters
Parameters
Type
Description
string
Port a usage mode setting:
256x18, 512x9, 1kx4, 2kx2, 4kx1, wtdp (wide true dual port)
Default: 256x18
string
Port b usage mode setting:
256x18, 512x9, 1kx4, 2kx2, 4kx1, wtdp (wide true dual port)
Default: 256x18
string
Bypassing of write data from write port to read port enable for port a,
true or false
Default: false
portb_wr_through
string
Bypassing of write data from write port to read port enable for port b,
true or false
Default: false
init_file
string
EMB initial file
Default: “” (No initial file)
operation_mode
string
EMB working mode, just for simulation
true_dual_port, single_port, simple_dual_port
porta_data_width
string
EMB port a data width
modea_sel
modeb_sel
porta_wr_through
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CME-M5 Family Data Sheet
Parameters
Type
portb_data_width
string
2.3.2
Description
EMB port b data width
EMB5K Operations
Writing data to and accessing data from the EMB5K are synchronous operations that take place
independently on each of the two ports.
When the we and ce signals enable the active edge of clk, data at the d input bus is written to the
EMB5K location addressed by the a lines. There are two write actions which are selected by wr_through
parameter. The write data is also passed to q output bus if the wr_through is true during the writing
process. The q output bus value will be the previous read output value during the writing process if the
wr_through is false. The two operation waveforms are shown in Figure 4 and Figure 5.
clk
ce
we
a
ab
d
0000
q
bb
FFFF
men[ab]
FFFF
mem[bb]
Figure 4 wr_through is false Waveform
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CME-M5 Family Data Sheet
clk
ce
we
1
a
ab
d
0000
bb
1
q
FFFF
mem[ab]
FFFF
mem[bb]
FFFF
Figure 5 wr_through is true Waveform
2.3.3
EMB5K Operation Mode
(1) EMB5K True Dual-port
EMB5K supports any combination of dual-port operation: two read ports, two write ports, or one read and
one write at different clock frequencies. The following figure shows true dual-port memory configuration.
Port A
Port B
db[]
aa[]
ab[]
wea
clka
EMB5K
da[]
web
clkb
cea
ceb
qa[]
qb[]
Figure 6 True Dual-port Memory Mode
Table 5 Port Descriptions of True Dual-port Memory Mode
Port Name
Type
Description
aa (b)
Input
Port A (B) Address.
da (b)
Input
Port A (B) Data Input.
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CME-M5 Family Data Sheet
Port Name
Type
Description
qa (b)
Output
wea (b)
Input
Port A (B) Write Enable. Data is written into the dual-port SRAM upon the
rising edge of the clock when both wea (b) and cea (b) are high.
cea (b)
Input
Port A (B) Enable. When cea (b) is high and wea (a) is low, data read from the
dual-port SRAM address aa (b). If cea (b) is low, qa (b) retains its value.
clka (b)
Input
Port Clock.
Port A (B) Data Output.
Table 6 True Dual-port Configurations
B Port
A Port
4K×1
2K×2
1K×4
512×8
4K × 1
√
√
√
√
2K × 2
√
√
√
√
1K × 4
√
√
√
√
512 × 8
√
√
√
√
512×9
256×16
256×18
√
512 × 9
256 × 16
256 × 18
(2) EMB5K Simple Dual-port
EMB5K also supports simple dual-port memory mode: one read port while one write port. The following
figure shows simple dual-port memory configuration.
qr[]
aw[]
ar[]
cew
clkw
EMB5K
dw[]
cer
clkr
Figure 7 Simple Dual-port Memory Mode
Table 7 Port Descriptions of Simple Dual-port Memory Mode
Port Name
Type
Description
dw
Input
Write Data
aw
Input
Write Address
clkw
Input
Write Clock
cew
Input
Write Port Enable. Active high.
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CME-M5 Family Data Sheet
Port Name
Type
Description
qr
Output
ar
Input
Read Address
cer
Input
Read Enable. Active high
clkr
Input
Read Clock
Read Data
Table 8 Simple Dual-port Configurations
W Port
Read Port
4K×1
2K×2
1K×4
512×8
4K × 1
√
√
√
√
2K × 2
√
√
√
√
1K × 4
√
√
√
√
512 × 8
√
√
√
√
512×9
256×18
√
512 × 9
256 × 16
256×16
√
√
√
√
√
√
256 × 18
(3) EMB5K Single-port
EMB5K also supports single-port memory mode as shown in the figure below.
EMB5K
we
clk
ce
d[]
a[]
q[]
Figure 8 Single-port Memory Mode
Table 9 Pin Description of Single-port Memory Mode
Port Name
Type
Description
d
Input
Write Data
a
Input
Write Address.
we
Input
Write Enable. Active high.
clk
Input
Write Clock.
ce
Input
Port Enable. Active high.
q
Output
Read Data
Table 10 Single-port Configuration
Port
4K×1
2K×2
1K×4
512×8
512×9
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256×16
256×18
19
CME-M5 Family Data Sheet
2.3.4
Conflict Avoidance
In the dual-port memory mode, both ports can access any memory address at any time. When both ports
access the same address, the read and write behavior should observe certain clock timing restrictions.
These restrictions are applicable to both synchronous and asynchronous clocks.
2.4 DSP Block
The CME-M5 family devices have one column of 8 DSP MAC tiles. Within the DSP column, a single DSP
tile is combined with extra logic and routing.
dinx
dinx_input_mode
diny
diny_input_mode
+
X
acc_en
dinz_en
mac_out
mac_output_mode
sload
dinz
dinz_input_mode
Figure 9 DSP Block
DSP tile contains an 18 x 18 two’s complement multiplier and a 40-bit sign-extended accumulator, a
function that is widely used in digital signal processing (DSP). Programmable pipelining of input
operands, intermediate products, and accumulator outputs enhances throughput.
DSP provides features as below:





18 x 18 two's-complement multiplier with a full-precision 36-bit result
Flexible 40-bit post-accumulator with optional registered accumulation feedback
Dynamic user-controlled operating modes to adapt DSP functions from clock cycle to clock cycle
Registers, ensuring maximum clock performance and highest possible sample rates with no area
cost
One DSP support 2 independent 12 x 9 multiplier with 21-bit accumulator
2.4.1
DSP Primitive
The following figure shows DSP (MAC) block.
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CME-M5 Family Data Sheet
MAC
a_dinx[13:0]
a_diny[9:0]
a_dinz[20:0]
a_mac_out[20:0]
a_over_flow
a_sload
a_acc_en
a_dinz_en
clk
rst_n
b_dinx[13:0]
b_diny[9:0]
b_dinz[20:0]
b_mac_out[20:0]
b_over_flow
b_sload
b_acc_en
b_dinz_en
Figure 10 MAC Block
Table 11 Port Definition
Port
Direction
Width
Description
a_dinx[13:0]
I
14
Multiplicand inputs from ixbar to mult A MSBs, 6 bit LSBs
for usage in 18x18 mode.
b_dinx[13:0]
I
14
Multiplicand inputs from ixbar to mult B MSBs.
a_diny[9:0]
I
10
Multiplier input from ixbar to mult A, LSBs of multiplier
input in 18x18 mode.
b_diny[9:0]
I
10
Multiplier input from ixbar to mult B, MSBs of multiplier
input in 18x18 mode.
a_dinz[20:0]
I
21
Ixbar and bypass inputs to mult A post add and post add
LSBs in 18x18 mode.
b_dinz[20:0]
I
21
Ixbar and bypass inputs to mult B post add and post add
MSBs in 18x18 mode.
a_sload
I
1
sloadA, when asserted directly loads the post add input
into the accumulator.
b_sload
I
1
sloadB, when asserted directly loads the post add input
into the accumulator.
a_acc_en
I
1
Accumulator A enable.
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CME-M5 Family Data Sheet
Port
Direction
Width
Description
a_dinz_en
I
1
Post adder A enable.
b_acc_en
I
1
Accumulator B enable.
b_dinz_en
I
1
Post adder B enable.
a_mac_out[20:0]
O
21
Outputs to oxbar mult A.
b_mac_out[20:0]
O
21
Outputs to oxbar mult B.
a_overflow
O
1
mulA Overflow flag.
b_overflow
O
1
mulB Overflow flag.
clk
I
1
Clock input.
rstn
I
1
Reset input, Active low.
Table 12 Parameter Table
Parameters
Type
mode_sel
string
MAC working mode select, default: 000.
signed_sel
string
Set signed/unsigned multiplication, true or false, default: true.
adinx_input_mode
string
a_dinx input mode setting: bypass or register, default: bypass.
adiny_input_mode
string
a_diny input mode setting: bypass or register, default: bypass.
adinz_input_mode
string
a_dinz input mode setting: bypass or register, default: bypass.
amac_output_mode
string
a_mac_out output mode setting: bypass or register
Default: bypass.
bdinx_input_mode
string
b_dinx input mode setting: bypass or register, default: bypass.
bdiny_input_mode
string
b_diny input mode setting: bypass or register, default: bypass.
bdinz_input_mode
string
b_dinz input mode setting: bypass or register, default: bypass.
bmac_output_mode
string
b_mac_out output mode setting: bypass or register,
Default: bypass.
2.4.2
Description
DSP Usage Mode
The DSP can be used as two dependent 12x9 A-MAC and B-MAC or one 18x18 MAC function. These
MACs have the same functions is shown as Figure 9. The CME Primace® deals with use input width and
maps to 12x9 A-MAC and B-MAC or one 18x18 MAC automatically.
Table 13 Port Description
Port name
Type
Description
clk
Input
Clock, posedge active.
rstn
Input
Reset, active low.
dinx
Input
Multiplier input (Range: 2~18).
diny
Input
Multiplier input (Range: 2~18).
dinz
Input
Input (Range: 2~40).
sload
Input
Accumulate load.
acc_en
Input
Accumulate enable, active high.
dinz_en
Input
Adder enable, active high.
mac_out
Output
Output (Range: 2~40).
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CME-M5 Family Data Sheet
Port name
Type
overflow
Output
Description
Overflow, 1 overflow; 0 not active high.
Note: The acc_en and dinz_en both are not active if they are both high.
Table 14 Parameter Description
Parameter
Type
Description
signedx_sel
string
“true” dinx input type is signed
“false” dinx input type is unsigned
signedy_sel
string
“true” diny input type is signed
“false” diny input type is unsigned
signedz_sel
string
“true” dinz input type is signed
“false” dinz input type is unsigned
dinx_input_mode
string
" bypass " input directly to multiplier;
" register " input via register
diny_input_mode
string
" bypass " input directly to multiplier;
" register " input via register
dinz_input_mode
string
" bypass" input directly;
" register" input via register
mac_output_mode
string
" bypass" mac output directly;
" register" mac output via register
The x * y multiplier output will be an unsigned result only when both the x and y are unsigned, otherwise
the x * y multiplier output will be a signed and two’s complement result. The mac_out will be an unsigned
result only when both the dinz and multiplier output are unsigned, otherwise the mac_out will be a signed
and two’s complement result.
(1) Multiplier
The following figure describes that the DSP is used as a multiplier which outputs the dinx * diny result.
dinx
dinx_input_mode
diny
X
+
mac_out
mac_output_mod
e
diny_input_mode
Figure 11 Multiplier
(2) Multiplier and adder
The following figure describes that the DSP is used as a multiplier and adder which output the dinx * diny
+ dinz result.
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CME-M5 Family Data Sheet
dinx
dinx_input_mode
diny
+
X
mac_out
mac_output_mode
acc_en
dinz_en
diny_input_mode
dinz
dinz_input_mode
Figure 12 Multiplier and Adder
(3) Multiplier and Accumulator
The following figure describes that the DSP is used as a multiplier and adder which output the dinx * diny
+ mac_out(n-1) result.
dinx
dinx_input_mode
diny
diny_input_mode
+
X
acc_en
dinz_en
mac_out
mac_output_mode
sload
dinz
dinz_input_mode
Figure 13 Multiplier and Accumulator
2.5 Embedded Single Port SRAM
CME-M5 family device contains an embedded SPRAM. The synchronous SPRAM total size is 128Kbyte
that can be configured as 128x8 or 64x16 mode.
2.5.1
SRAM Port Definitions
The dual-port primitive SPRAM signals are defined in the table below.
Table 15 SRAM Port Definition
Port Name
Type
Width
Description
clk
I
1
Input clock for SRAM, posedge active
cen
I
1
Chip enable for SRAM, active low
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CME-M5 Family Data Sheet
Port Name
Type
Width
Description
wen
I
1
Write enable for SRAM, active low
addr
I
12
Address line for SRAM
datai
I
8/16
Data input for SRAM
datao
o
8/16
Input clock for SRAM
Table 16 SRAM Parameters
Parameters
Type
Description
data_width
string
SPRAM port data width, “8” or “16”
init_file
string
SPRAM initial file, the suffix name is .dat or .hex
Default: “”
2.6 Input/output Blocks
The Input/output Block (IOB) provides a programmable, bidirectional interface between an I/O pin and
the FPGA’s internal logic. The IOC is the function for an I/O pin. A simplified diagram of the IOC’s
internal structure appears in Figure 14. There are three main signal paths within the IOC: the output path,
input path, and tri-state path. Each path has its own pair of registers that can act as registers. The three
main signal paths are as follows:




The input path carries data from the pad, which is bonded to a package pin, through an optional
programmable delay element directly to the id line. There are alternate routes through a register to
the id line. The id line is lead to the FPGA’s logic.
The output path, starting with od, carries data from the FPGA’s internal logic through a multiplexer
and then a tri-state driver to the IOC pad. In addition to this direct path, the multiplexer provides the
path to registers.
The tri-state path determines when the output driver is high impedance. The oen line carries data
from the FPGA’s internal logic through a multiplexer to the output driver. In addition to this direct
path, the multiplexer provides the option to insert a register. When the oen line is asserted high, the
output driver is high-impedance (Floating, Hi-Z). The output driver is active-low enabled.
The output and tri-state paths entering the IOC have an inverter option. Any inverter placed on
these paths is automatically absorbed into the IOC.
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CME-M5 Family Data Sheet
id_setn
0
1
id
Q
setn
rxd
D
CK
Qresetn
Level Shifters DOWN
clk
RXD_S
Vddc
Vddio
In
out
id_resetn
VDDIO
Schmitt Trigger
ESD
od
Pull
UP
od_setn
1
0
setn
D
clk
Q
CK
Q
resetn
1
0
2
3 txd
1
0
Single-ended
Transmitter (Driver)
Vddc
Vddio
In
out
Pad
od_resetn
Pull
DOWN
Level Shifters UP
oen
oen_setn
1
0
setn
D
clk
CK
Q
Q
resetn
0
1
Vddc
Vddio
In
out
2
3 txe
1
0
Bus
Beeper
VSS
oen_resetn
Figure 14 IOC
The IOC Symbol is shown in the following figure.
clk
clken
setn
rstn
oen
od
pad
IOC
id
Figure 15 IOC Symbol
Table 17 OC Port Definition
Port
Width
Direction
Description
clk
1
I
IO input clock
rstn
1
I
IO input reset, active low
setn
1
I
IO input set, active low
clk_en
1
I
IO clock enable
oen
1
I
IO output enable, active low
od
1
I
Output data from fabric
id
1
O
Input data from IO
pad
1
IO
IO pad
Parameters
is_en_used
string
Whether external enable is used. Default: false
reg_always_en
string
Register for id/od/oen enable setting. True or false,
default: false
is_rstn_inv
string
Reset input invert enable, true or false, default: false
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CME-M5 Family Data Sheet
Port
Width
Direction
Description
is_setn_inv
string
Set input invert enable, true or false, default: false
is_clk_inv
string
Clock input invert enable, true or false, default: false
is_od_inv
string
Input data from fabric invert enable, true or false,
default: false
is_oen_inv
string
Output enable invert enable, true or false, default:
false
oen_sel
string
Output enable mux selection control from
bypass/register/vcc(1)/gnd(0)
Default: bypass
od_sel
string
IO input data mux selection control from
bypass/register/vcc(1)/gnd(0)
id_sel
string
IO output to fabric mux selection from
bypass/register
Default: bypass
oen_setn_en
string
Output enable register set enable
oen_rstn_en
string
Output enable register reset enable
od_setn_en
string
IO input register set enable
od_rstn_en
string
IO input register reset enable
id_setn_en
string
IO output register set enable
id_rstn_en
string
IO output register reset enable
2.6.1
Pull-Up/Down/Keeper Resistors
The optional pull-up and pull-down resistors are intended to establish logic High or Low, at unused I/Os.
The pull-up resistor optionally connects each IOB pad to VCCIO and the pull-sown resistor optionally
connects each IOB pad to GND. The resistors are about 50KΩ~100KΩ. Each I/O has an optional keeper
circuit that retains the last logic level on a line after all drivers have been turned off. This is useful to keep
bus lines from floating when all connected drivers are in a high-impedance state. These resistors are
used in a design using the “pull up”, “pull down” and “bus keeper “attributes in Primace .aoc file.
2.6.2
ESD Protection
The Electro-Static Discharge (ESD) protection circuitries protect all device pads against damage from
ESD as well as excessive voltage transients.
The VIN absolute maximum rating in Table 37 specifies the voltage range that I/Os can tolerate.
2.6.3
Drive Strength
CME-M5 I/O current drive strength is programmable 2, 4, 8, 12, 16mA
2.6.4
The Organization of IOBs into Banks
IOBs are allocated among 4 banks, so that each side of the device has one bank, as shown in Figure 1.
For all packages, each bank has independent VCCIO lines. For example, the VCCIO Bank 1 lines are
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CME-M5 Family Data Sheet
separate from the VCCIO lines going to all other banks.
2.6.5
The I/Os During Power-On, Configuration, and User Mode
With no power applied to the FPGA, all I/Os are in a high-impedance state. The VCCINT and VCCIO
supplies may be applied in any order. Before power-on can finish, VCCINT, VCCIO must have reached
their respective minimum recommended operating levels. At this time, all I/O drivers also will be in a
high-impedance state.
VCCIO and VCCINT serve as inputs to the internal Power-On Reset circuit (POR). When the power is
applied, the FPGA begins initializing its configuration memory. At the same time, the FPGA internally
asserts the Global Set-Reset (GSR), which asynchronously resets all IOB registers to a pull-up state. A
Low level applied to nCONFIG input also serves as a GSR.
At this point, the configuration data is loaded into the FPGA. The I/O drivers remain in a high-impedance
state (with pull-up resistors) throughout configuration. The signal is released during Start-Up, marking
the end of configuration and the beginning of design operation in the user mode. At this point, those I/Os
to which signals have been assigned go active while all unused I/Os remain in a high-impedance state.
2.7 Interconnect
All the CME-M5 family device tile includes Xbar that is interconnect, also called routing resources and
function element. The Xbar passes signals among the various functional tiles of CME-M5 family devices.
There are four kinds of interconnect: Octal lines, Triple lines, Single lines, and Diagonal lines.
Octal lines span the die both horizontally and vertically and connect to one out of every eight and four
Xbars (see Figure 16).
Triple lines connect to one out of every three, two and one Xbars horizontally and vertically (see Figure
16).
The octal and triple lines are very useful for one driver fanouting several tiles which span different tiles
numbers.
triple
xbar
xbar
xbar
xbar
xbar
xbar
xbar
xbar
triple
xbar
xbar
xbar
octal
xbar
xbar
xbar
xbar
xbar
xbar
octal
Figure 16 Octal and Triple Lines
Single and Diagonal lines directly connect lines route signals to neighboring tiles: vertically, horizontally.
These lines most often drive a signal from a "source" tile to an octal and triple line and conversely from
the longer interconnect back to a direct line accessing a "destination" tile.
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CME-M5 Family Data Sheet
xbar
xbar
xbar
xbar
xbar
xbar
xbar
xbar
xbar
diagonal
single
Figure 17 Single and Diagonal Lines
2.8 PLL
2.8.1 PLL features












Input frequency:
PFD input frequency:
Output frequency:
VCO operating rang:
Clock bypass mode:
Power supply:
Output clock duty-cycle:
Run power current consumption:
Power down current:
Operation junction temperature:
PLL outputs:
Lock detection output
2.8.2
5~472.5 MHz
5 ~ 325 MHz
10 ~ 450 MHz
600 ~ 1200 MHz
Allow bypass of input clock directly to PLL output
DVDD: 1.0 ~ 1.2V, VDDA: 1.0 ~ 1.2V
45-55%
< 2mA
< 20uA (VDDA), < 10uA(DVDD)
-40 to 125 °C
CO0, CO1, CO2, CO3
PLL Hardware Description
CME-M5 family device contains two PLLs (PLL0 and PLL1) with advanced clock management features.
The main goal of a PLL is to synchronize the phase and frequency of an internal or external clock to an
input reference clock. The PFD produces an up or down signal that determines whether the
voltage-controlled oscillator (VCO) needs to operate at a higher or lower frequency. The output of the
PFD feeds the charge pump and loop filter, which produces a control voltage for setting the VCO
frequency. The loop filter also removes glitches from the charge pump and prevents voltage overshoot,
which filters the jitter on the VCO. A divide counter (m) is inserted in the feedback loop to increase the
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CME-M5 Family Data Sheet
VCO frequency above the input reference frequency. VCO frequency (fVCO) is equal to (m+1) times the
input reference clock (fIN). The input reference clock (fIN) to the PFD is equal to the input clock (fIN)
divided by the pre-scale counter (N+1). Therefore, the feedback clock (fFB) applied to one input of the
PFD is locked to the fIN that is applied to the other input of the PFD. The VCO output can feed 4
post-scale counters (C[0..3]), while the corresponding VCO output from Top/Bottom PLLs can feed ten
post-scale counters (C[0..3]). These post-scale counters allow a number of harmonically related
frequencies to be produced by the PLL.
The figure below shows a simplified block diagram of the major components of the CME-M5 FAMILY
PLL.
pll_lock
Lock
fREF
fIN
clkin
fVCO
pre-divider
1/(n+1)
PFD
Charg
e
Pump
Loop
Filter
VCO
vco_divide_mod
e
DIV2
8
8
post-divider
1/(c0+1)
clkout0
1/(c1+1)
clkout1
1/(c2+1)
clkout2
1/(c3+1)
clkout3
fFB
1/(m+1
)
loop-divider
fbclkin
operation_mod
e
Figure 18 PLL Block Diagram
The dedicated pin CLK0~CLK3, XIN and OSC (internal configuration oscillator) and FPGA logic feed the
Bottom PLL0 clkin as the PLL clock input. The external feedback fbclkin must come from the dedicated
pin CLK0~CLK3 or internal clkout0 if the PLL is used as external feedback mode. The PLL generates
four clock outputs.
The Top PLL1 is same as the PLL0 only when the clkin and fbclkin are come from the dedicated pin
CLK4~CLK7.
2.8.3
PLL Primitive Port Signal Definitions
CME-M5 family PLLs primitive module port signal definition and parameter table are shown in the table
below. The CME-M5 family PLL can be generated using the Primace wizard.
Table 18 Port Definition
Port Name
Type
Description
clkin
Input
PLL reference clock input
fbclkin
Input
Feedback input to the PLL. Come from the dedicated CLK pin or
PLL clkout0.
clkout0
Output
PLL output 0 driving to the global clocks.
clkout1
Output
PLL output 1 driving to the global clocks.
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CME-M5 Family Data Sheet
Port Name
Type
clkout2
Output
PLL output 2 driving to the global clocks.
clkout3
Output
PLL output 3 driving to the global clocks.
locked
Output
Lock output from lock detect circuit. Active high
pwrdown
Input
Description
Power down control.
1: Power on PLL
0: Power down PLL (default)
Table 19 Parameter Definition
Parameters
pwr_mode
operation_mode
rst_mode
bandwidth_type
vco_phase_shift
co0_enable
Type
Description
string
PLL power mode.
"always_off": make PLL always stay in power down status
"always_on": make PLL always stay in power on status
"mcu_ctrl": mcu control the PLL power
"fp_ctrl": FP control the PLL power
Default: "always_off",
string
PLL feedback source path.
"internal_feedback": select the internal PLL output as the feedback
source
"external_feedback": select the external dedicated CLK pin as the
source
default: "internal_feedback"
string
PLL reset mode
"auto": chip power on to reset the PLL automatically
"mcu_control": MSS 8051 mcu control the PLL reset
test_control: reserved for chip test
default: "auto"
string
PLL bandwidth setting
"low": filters out reference clock jitter but increases lock time
"medium": default
"high": provides a fast lock time and tracks jitter on the reference
clock source
string
VCO phase shift setting
VCO phase select from the "0", "45", "90", "135", "180", "225",
"270", "315" degree.
default: “0”
string
PLL CO0 output enable
"true": PLL CO0 output enable
"false" PLL CO0 output disable
default : "true"
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CME-M5 Family Data Sheet
Parameters
Type
Description
string
PLL CO1 output enable
"true": PLL CO1 output enable
"false" PLL CO1 output disable
default : "false"
string
PLL CO2 output enable
"true": PLL CO2 output enable
"false" PLL CO2 output disable
default : "false"
co3_enable
string
PLL CO3 output enable
"true": PLL CO3 output enable
"false" PLL CO3 output disable
default : "false"
multiply_by(M)
decimal
PLL loop-divider setting, range is from 1 to 256
divide_by(N)
decimal
PLL pre-divider setting, range is from 1 to 256
co0_divide_by(C0)
decimal
PLL output 0 counter setting, range is from 1 to 256
co1_divide_by(C1)
decimal
PLL output 1 counter setting, range is from 1 to 256
co2_divide_by(C2)
decimal
PLL output 2 counter setting, range is from 1 to 256
co3_divide_by(C3)
decimal
PLL output 3 counter setting, range is from 1 to 256
co0_delay_by
decimal
PLL output 0 to counter delay the VCO cycles , range is from 0
to255
co1_delay_by
decimal
PLL output 1 to counter delay the VCO cycles , range is from 0 to
255
co2_delay_by
decimal
PLL output 2 to counter delay the VCO cycles , range is from 0 to
255
co3_delay_by
decimal
PLL output 3 to counter delay the VCO cycles , range is from 0 to
255
co0_phase_shift
string
PLL output 0 to counter phase shift to VCO, select from the 8
"0","45","90","135","180","225","270","315" degree phase
co1_phase_shift
string
PLL output 1 to counter phase shift to VCO, select from the 8
"0","45","90","135","180","225","270","315" degree phase
co2_phase_shift
string
PLL output 2 to counter phase shift to VCO, select from the 8
"0","45","90","135","180","225","270","315" degree phase
co3_phase_shift
string
PLL output 3 to counter phase shift to VCO, select from the 8
"0","45","90","135","180","225","270","315" degree phase
co1_enable
co2_enable
The CME-M5 family device is a SoC device. The 8051 of MSS can control the PLL parameter such as
loop-divider M and pre-divider N. Post-divider C0, C1, C2 and C3 also can be modified or reconfigured
by 8051 in system. For more details, please refer to 3.7.5 MSS in System Clock Configuration.
2.8.4
Clock Feedback Modes
CME-M5 family PLLs support up to two feedback modes. Each mode allows clock multiplication and
division, phase shifting. The mode is controlled by the operation_mode parameter.
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CME-M5 Family Data Sheet
(1) Internal Feedback Mode (Frequency Synchronous Mode)
In frequency synthesize mode, the feedback is from the internal VCO, the PLL does not compensate for
any clock networks. This provides better jitter performance because clock feedback into the PFD passes
through less circuitry.
pll_lock
Lock
post-divider
fREF
fIN
clkin
fVCO
pre-divider
1/(n+1)
PFD
Charge
Pump
Loop
Filter
VCO
vco_divide_mode
8 DIV2
8
1/(c0+1)
clkout0
1/(c1+1)
clkout1
1/(c2+1)
clkout2
1/(c3+1)
clkout3
fFB
1/(m+1)
Figure 19 Internal Feedback Mode
fpfd = fIN /(N+1) ;
fVCO = fIN *DIV2*(M+1)/(N+1), DIV2 = 1 or 2 ;
fFB = fVCO / m;
fclkout0 = fIN * (M+1) / ((N+1) * (C0+1));
fclkout1 = fIN * (M+1) / ((N+1) * (C1+1));
fclkout2 = fIN * (M+1) / ((N+1) * (C2+1));
fclkout3 = fIN * (M+1) / ((N+1) * (C3+1));
(2) External Feedback Mode
In external feedback mode, the external feedback input pin (fbclkin) is phase-aligned with the clock input
pin. Aligning these clocks allows you to remove clock delay and skew between the devices. This mode is
supported on all CME-M5 family PLLs. The feedback signal fbclkin comes from internal global clock PLL
clkout0 as shown in Figure 20 or clock pin CLK0~3/CLK4-7 as shown in Figure 21.
The clock pin CLK0~3/CLK4-7 is connected with the pin which is driven by the clkout0 on the board.
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CME-M5 Family Data Sheet
pll_lock
Lock
post-divider
pre-divider
fIN
fREF
fVCO
vco_divide_mode
1/(n+1)
clkin
Charge
Pump
PFD
Loop
Filter
VCO
1/(c0+1)
clkout0
1/(c1+1)
clkout1
1/(c2+1)
clkout2
1/(c3+1)
clkout3
8
8 DIV2
fFB
1/(m+1)
fbclkin
loop-divider
Figure 20 Feedback Signal from clkout0
pll_lock
Lock
post-divider
pre-divider
fREF
fIN
clkin
fVCO
vco_divide_mode
1/(n+1)
PFD
Charge
Pump
Loop
Filter
VCO 8 DIV2
8
pin
1/(c0+1)
clkout0
1/(c1+1)
clkout1
1/(c2+1)
clkout2
1/(c3+1)
clkout3
IC
fFB
1/(m+1)
fbclkin
loop-divider
clk pin
Figure 21 Feedback Signal from Clock Pin clk0~3/clk4~7
fpfd = fIN /(N+1) ;
fVCO = fIN *DIV2*(M+1)/( (C0+1) (N+1)), DIV2 = 1 or 2 ;
fFB = fVCO / (M+1);
fclkout0 = fIN * (M+1) / (N+1);
fclkout1 = fIN * (M+1) (C0+1) / ((N+1) * (C1+1));
fclkout2 = fIN * (M+1) (C0+1) / ((N+1) * (C2+1));
fclkout3 = fIN * (M+1) (C0+1) / ((N+1) * (C3+1));
2.9 Global Clock & Reset Resources
CME-M5 family global clock resources include the dedicated clock inputs, buffers, and routing. The
clocking infrastructure provides eight low-capacitances and low-skew interconnect global clock lines.
The global clock lines can provide high-performance, low-jitter and low-skew clock source for each
blocks in FPGA. These resources also can be used for high-fanout signals.
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CME-M5 Family Data Sheet
2.9.1
External Crystal Input
XIN and XOUT are external crystal input and output pins respectively. Their frequency ranges from 10
MHz to 20 MHz. When XIN works as external clock input, input clock connects to global clock tree
through XIN; meanwhile XOUT floats or connects to GND. The connection diagram when the external
crystal works as clock input connection is shown in the figure below.
XOUT
1M
CME Device
XIN
330
22P
22
P
10~20M
Figure 22 External Crystal Input
2.9.2
Clocking Infrastructure
The global clock resources consist of two connected components: two clock generators blocks and
Global Clock routing network. The CME-M5 family clock network infrastructure is shown in the figure
below.
2
IO
…
SEAM
6
Logic
Inputs
LBUF
6
6
…… RBUF
GCLK
Spine
GBUF
Gbuf
4:1*2
4
EMIF
4
gbuf
2:1*6
RBUF
GBUF
2
LBUF
MSS
4
GCLK
2
gclk to EMIF clock
gclk to MSS clock
Clock generator
FP input
LBUF
…… RBUF
…
…
Gclk[4]~Gclk[7]
2
RBUF
Logic
Inputs
Logic
Inputs
LBUF
…
…
6
LBUF
…
Gbuf
4:1*2
4
Gclk[0]~Gclk[3]
4
2
LBUF
…
…
4
gbuf
2:1*6
RBUF
LBUF
…… RBUF
clk4-clk7
6
LBUF
…… RBUF
4
gbuf
2:1*6
PLL1
Mux &
deglitch
FP input
Mux &
deglitch
PLL0
clk0-clk3
XIN
2
gbuf
2:1*6
RBUF
6
Logic
Inputs
4
IO
Gbuf
4:1*2
2
Figure 23 Clock Infrastructure
The clock generator 0 is located in the right of the bottom edge. The clock generator selects from the
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CME-M5 Family Data Sheet
dedicated pins CLK0 – CLK3, XI, 4 PLL0 outputs and fabric logic signals source to generate four global
clocks to the GBUFs(global buf). The clock generator 1 is placed in the right of the top corner. Its
function is same as the clock generator 0, only the dedicated pin CLK4 - CLK7 replaced the CLK0 –
CLK3. Each clock generators has four multiplexers named as CFG_DYN_SWITCH which can deglitch
and hand off between pairs of clock sources, including a clock from the other clock and generator 4
global clocks to GBUFs. Two clock generators generate 8 global clocks to GBUFs.
GBUFs are located in the vertical spine, just to the right of the FP fabric, as shown schematically in the
above figure. Clocks from the clock generators are distributed to the GBUFs in a skew-balanced tree.
Each GBUF selects from the 8 spine clocks, a set of Gclks to distribute along its respective horizontal
seam. There are six seams, four for Fabric and two for I/O blocks.
The 2 IO GBUFs each select 2 Gclks for their seams. One MSS GBUF and EMIF GBUF also select one
GCLK from the 8 spine clocks for the clock of the MSS and EMIF interface.
Each of the four FP GBUFs selects 6 Gclks. In addition to the 8 spine clocks, the FP GBUFs may also
select from logic inputs from the FP fabric to distribute as Gclks. The four GBUFs are designed not as full
cross-bars, but as sparsely-populated crossbars, in order to reduce circuitry while providing a fully
nonblocking network (every PLL clock can reach every seam without blocking any other clock from
reaching any seam). A special GBUF selects from the 8 spine clocks, two more Gclks to distribute to all
FP fabric seams in a lowskew, recombinant mesh. These two clocks are rebuffered from this point all the
way down to PLBs without further selection or regional gating before final, LBUF muxes, so may be
connected in recombinant grids wherever their logic levels match. This provides a very
low-structural-skew option for any two clocks throughout the entire FP array; the remaining Gclks and
Rclks have flexible selectability and hierarchical gating, so cannot be recombined between seams.
All 8 Gclks in each FP fabric horizontal seam are distributed in a skew-balanced tree to each RBUF.
RBUFs select regional clocks to four rows of PLBs above and four below the seam, in two PLB columns,
or to one SFB above and one SFB below the seam. The two low-skew Gclks are simply rebuffered into
the low-skew Rclk grid; at the top and bottom of their columns, they connect to matching Rclks arriving
from the adjacent seam.
LBUFs are the last stage in the clock tree; they directly drive the flipflops. LBUFs provide local, precise
clock gating. Each two PLBs contain an LBUF, to select a local clock for its 8 registers from the 6 Rclks;
each SFB contains one or more LBUFs, one per clock domain, as needed.
2.9.3
GBUF
The GBUF generated by the Wizard allows a clock or general signal to enter the Global Clock Network
directly.
Table 20 GBUF Port Definition
Port Name
Type
in
Input
Description
GBUF input
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CME-M5 Family Data Sheet
Port Name
Type
out
Output
Description
GBUF clock output
M5 is designed with two gated global clocks that can be easily controlled by using GBUF_GATE.
Table 21 GBUF_GATE Port Definition
Port Name
Type
clk
Input
Clock input
en
Input
Clock enable, active high
clk_out
Output
2.9.4
Description
GBUF clock output
Clock Switch
The clock generator contains one PLL and a four input deglitch CFG_DYN_SWITCH multiplexer. Each
of the four CFG_DYN_SWITCH multiplexer generates a gclk clock. The CFG_DYN_SWITCH
multiplexer not only can be used as a static clock path, but also can provide seamless clock dynamic
switchover between two clock sources in system, for both startup sequencing and entering/exiting
low-power operating modes.
The primitive CFG_DYN_SWITCH h is used to implement the clock dynamic switching in system. The
CFG_DYN_SWITCH is selected by MSS. About how to use the dynamic clock switch function, see MSS
Subsystem.
Table 22 CFG_DYN_SWITCH Port Definition
Port Name
Type
Description
in0
Input
GCLK clock source 0 input.
in1
Input
GCLK clock source 1 input.
out
Output
Global clock to GBUF.
Table 23 Parameter Descriptions of CFG_DYN_SWITCH
Parameters Name
Type
gclk_mux
digital
Description
Define the CFG_DYN_SWITCH location.
Table 24 Clock Routability Table
GCLK
IN0
IN1
GCLK[0]/
gclk_mux 0
PLL0O0
PLL0O1
CLK0
CLK1
PLL0O2
PLL0O3
GCLK[1]/
gclk_mux 1
PLL0O1
PLL0O3
CLK2
CLK3
PLL0O0
PLL0O2
GCLK[4]
FP
GCLK[2]/
gclk_mux 2
PLL0O1
PLL0O2
CLK1
CLK2
PLL0O0
PLL0O3
XIN
FP
GCLK[3]/
gclk_mux 3
PLL0O0
PLL0O1
CLK0
CLK3
PLL0O2
PLL0O3
XIN
FP
GCLK[4]/
PLL1O0
PLL1O1
CLK4
CLK5
PLL1O2
PLL1O3
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FP
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CME-M5 Family Data Sheet
GCLK
IN0
IN1
gclk_mux 4
GCLK[5]/
gclk_mux 5
PLL1O1
PLL1O3
CLK6
CLK7
PLL1O0
PLL1O2
GCLK[0]
FP
GCLK[6]/
gclk_mux 6
PLL1O1
PLL1O2
CLK5
CLK6
PLL1O0
PLL1O3
XIN
FP
GCLK[7]/
gclk_mux 7
PLL1O0
PLL1O1
CLK4
CLK7
PLL1O2
PLL1O3
XIN
FP
For each of the eight GCLK, the CFG_DYN_SWITCH input in0 and in1 only can be fed as listed in the
table. The MSS can select the in0 or kin1 in system via the special extended SFR. About how to use the
dynamic clock switch function, please refer to MSS Subsystem.
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CME-M5 Family Data Sheet
3 MSS Subsystem
MSS Subsystem is composed of 200 MHz enhanced 8051 processor, embedded peripherals, SRAM
and other components which are interconnected via the Xbar or hardware connection. This chapter only
describes the MSS system and functions which are special for the CME-M5 family device. The
enhanced r8051xc2 core and peripherals are described in 8051 User Guide.
The MSS features are listed as follows:
 Enhanced 8051MCU
Reduced instruction cycle, 12 times in respect of standard 8051 MIPS, up to 200 MHz
Compatible 8051 instruction system
On-chip debugger system (OCDS), online JTAG debugging
Up to 8M data/code memory
 Embedded SRAM Memory
128KByte single port memory SRAM, up to 200 MHz
Data/code unified addressing, flexible memory configuration
Flexible chip inside and outside memory expand (EMIF)
 Peripheral
1 MDU
3 16-bit Timers, Timer 2 can be used as capture unit
1 16-bit Watch Dog Timer
1 I2C/SMBus Interface
1 SPI Interface
2 Full Duplex Asynchronous Series Ports
1 RTC
4-channel DMA
 Suspend, Idle Mode Power Management
 Chip system management
ISC control
Dynamic clock management
The figure below describes the functions of MSS and connections between MSS and FPGA.
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CME-M5 Family Data Sheet
MSS
FPGA
Peripheral
RTC
I2C
I2C
SPI
SPI
USART
Interrupt
P0,1,2,3...
P Port
SFR
PLL0
GCLK
PLL1
SFR
SFR
ISC
8051 MCU
EMIF
EMIF
SRAM
Figure 24 MSS Diagram
3.1 8051 Instantiation
In the view of a user design, the 8051 IP is considered to be a macro block as other IP, which will be
instantiated in the RTL code of the user design. The 8051 tile also contains Xbar that is used to connect
with other tiles.
3.1.1
8051 Macro Primitive Description
Table 25 8051 Port Definition
Name
Type
Bus size
Description
Global Interface
clkcpu
I
1
MSS 8051 clock, come from MSS GBUF or internal
OSC.
clkcpuen
O
1
Be low when CPU is in STOP and IDLE mode.
clkperen
O
1
Be low when CPU is in IDLE mode.
resetn
I
1
MSS reset, active low.
ro
O
1
MSS core reset output.
1
Start Watchdog Timer input.
High level on this pin during reset starts the Watchdog
Timer immediately after reset is released.
swd
I
SPI Interface
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CME-M5 Family Data Sheet
Name
Type
Bus size
Description
scki
I
1
Serial clock input.
scko
O
1
Serial clock output.
scktri
O
1
Serial clock tri-state enables.
ssn
I
1
Slave select input.
misoi
I
1
“Master input / slave output” input pin.
misoo
O
1
“Master input / slave output” output pin.
misotri
O
1
“Master input / slave output” tri-state enable.
mosii
I
1
“Master output / slave input” input pin.
mosio
O
1
“Master output / slave input” output pin.
mositri
O
1
“Master output / slave input” tri-state enables.
spssn
O
8
Eight slave select output.
scli,
I
1
Serial clock input.
sdai,
I
1
Serial data input.
sclo,
O
1
Serial clock output.
sdao,
O
1
Serial data output.
port0i
I
8
8-bit input port.
port0o
O
8
8-bit output port.
port1i
I
8
8-bit input port, combine with int2-7, ccu, t2, rxd1.
port1o
O
8
8-bit output port, combine with ccu, txd1.
port2i
I
8
8-bit input port.
port2o
O
8
8-bit output port.
port3i
I
8
8-bit input port, combine with int0-1, rxd0, t0, t1.
port3o
O
8
8-bit output port, combine with txd0, rxd0o.
clkemif
I
1
EMIF interface clock.
memack
I
1
Memory acknowledges.
memdatai
I
8
Memory data input.
memdatao
O
8
Memory data output.
memaddr
O
23
Memory address.
memwr
O
1
Memory write enable.
memrd
O
1
Memory read enable.
hold
I
1
Hold mode request, active high.
holda
O
1
Hold mode acknowledge signal.
intoccur
O
1
Interrupt occurs in hold mode signal.
waitstaten
O
1
Wait state indicator, active low when 8051 performs a
wait cycle.
I2C Interface
General I/O
EMIF Interface
Hold Interface
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CME-M5 Family Data Sheet
Table 26 Parameter Table
Parameters
Type
Description
rtc_div_num
String
Mcu rtc divide number.
sync_mode_en
String
Mcu synchronous mode enable,
True: synchronous mode, false: asynchronous mode.
program_file
String
Mcu/8051 program file: *.hex.
3.2 Multiplex of P Port Pins
Some function modules, such as: external interrupt1, USART0, USART1, Timer 0~2, and Compare –
Capture Unit, share pins with port1 and port3. The following shows the details.
Table 27 Port Pin Multiplex
Name
Polarity
Bus size
Type
Alternate
Port
Description
External Interrupts Inputs
int0
I
Low/Fall
port3i[2]
External interrupt 0
int1
I
Low/Fall
port3i[3]
External interrupt 1
int2
I
Fall/Rise
port1i[4]
External interrupt 2
int3
I
Fall/Rise
port1i[0]
External interrupt 3
int4
I
Rise
port1i[1]
External interrupt 4
int5
I
Rise
port1i[2]
External interrupt 5
int6
I
Rise
port1i[3]
External interrupt 6
int7
I
Rise
port1i[6]
External interrupt 7
Serial 0 Interface
rxd0i
I
1
port3i[0]
Serial 0 receive data
rxd0o
O
1
port3o[0]
Serial 0 transmit data
txd0
O
1
port3o[1]
Serial 0 transmit data or receive clock in
mode 0
Serial 1 Interface
rxd1
I
1
port1i[0]
Serial 1 receive data
txd1
O
1
port1o[1]
Serial 1 transmit data
t0
I
Fall
port3i[4]
Timer 0 external input
t1
I
Fall
port3i[5]
Timer 1 external input
t2
I
Fall
port1i[7]
Timer 2 external input
t2ex
I
Fall
port1i[5]
Timer 2 capture trigger
Timers Inputs
Compare – Capture Unit
cc(0)
I
Rise/Fall
port1i[0]
Compare/Capture 0 input
cc(1)
I
Rise
port1i[1]
Compare/Capture 1 input
cc(2)
I
Rise
port1i[2]
Compare/Capture 2 input
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CME-M5 Family Data Sheet
Name
Polarity
Bus size
Type
Alternate
Port
Description
cc(3)
I
Rise
port1i[3]
Compare/Capture 3 input
Ccubus[0]
O
1
port1o[0]
Compare/Capture 0 Output
Ccubus[1]
O
1
port1o[1]
Compare/Capture 1 Output
Ccubus[2]
O
1
port1o[2]
Compare/Capture 2 Output
Ccubus[3]
O
1
port1o[3]
Compare/Capture 3 Output
3.3 MSS Clock Description
SRAM
clk
GCLK from EMIF
GBUF
GCLK from MSS GBUF
clkemif
clkcpu
8051
Figure 25 MSS Clock
The clock signal gclk comes from the 8 global clocks, see Figure 23. The SRAM clock and clkcpu use
the same clock.
3.4 MSS Memory Map
CME-M5 family integrates 2 blocks of 64 KByte (128 Kbyte in total) SRAM. The 128 KByte SRAM is only
available by MSS. 8051 can access SRAM, at the speed of up to 200 MHz.
The 8051 MCU core can extend both Program Memory and External Data Memory (independently) up to
8 MB by means of dedicated page address register. But CME-M5 family ORs the 8051 write and read
program and external data signals to one write and read signals, this makes the program and external
data memory share the memory space. The program memory is up to increase from address 0, and the
reset and interrupt vectors are stored in the low memory. The 128 KB SRAM can be used as program or
external data memory. Users must separate program memory space from external data memory space,
do not make them overlapped.
The parameter program_file is used to locate the 8051 firmware *.hex file which will be the part of the
initialized data and is add to configuration file.
The following figure describes the CME-M5 family MSS memory map which includes the FP extend
memory.
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CME-M5 Family Data Sheet
7FFFFF
FP Expand
20000
1FFFF
128K SRAM
000000
Figure 26 MSS Memory Map
3.5 MSS External Memory Interface (EMIF)
EMIF is used to extend the MSS memory, with the address 20000~7FFFFF, which can be used by
Fabric.
The CME-M5 family provides synchronous and asynchronous EMIF for Fabric extended memory which
has the same data/address and control ports but in different timing waveforms. The synchronous or
asynchronous EMIF mode is selected by the parameter sync_mode_en.
Table 28 EMIF Port Description
Port Name
Type
Width
Description
clkemif
Input
1
Fabric EMIF clock. Posedge active.
memaddr
Output
23
EMIF Address, MSS to Fabric.
memdatai
Input
8
Read Data，Fabric to MSS.
memdatao
Output
8
Write data，MSS to Fabric.
memrd
Output
1
Read Enable. Active high.
memwr
Output
1
Write Enable. Active high.
memack
Input
1
Fabric to MSS operation acknowledge.
(1) Synchronous EMIF
The Fabric extended memory uses the same clkcpu as the 8051 clock. The signals are connected
directly to Fabric. For detailed description and waveform on synchronous mode, see the MSS
Subsystem User Guide.
The synchronous EMIF connection with fabric is shown as in figure below:
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CME-M5 Family Data Sheet
memaddr
memdatao
memdatai
8051
Fabric
memwr
memrd
memack
clkcpu
clkemif
clkcpu
clkcpu
Figure 27 sync_mode_en is “true”
(2) Asynchronous EMIF
The Fabric extended memory is in clkemif clock domain which is different with the 8051 clkcpu clock
domain. The hardware SyncBridge is used to synchronize the control signals from one side clock
domain to the other side clock domain during the memory accessing process. EMIF implements two-way
synchronization between Fabric clock domain and MSS clock domain of Fabric. Each read/write
operation of Fabric extended memory takes about 4 clkemif cycles+ three 8051 clock cycles.
The asynchronous EMIF connection with fabric is shown as in figure below:
memaddr
memdatao
memdatai
8051
Fabric
memwr
memrd
memwr_cpu
memrd_cpu
memack_cpu
SyncBrige
clkemif
clkcpu
clkcpu
clkemif
Figure 28 sync_mode_en is “false”
Control signals of “memrd”, “memwr” and “memack” are in the clkemif domain and generated on the
posedge clkemif. The “memrd”, “memwr”, “memack” control signals and “memaddr”, “memdatao” bus
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CME-M5 Family Data Sheet
will be held if there is no valid “memack” to be sent to 8051 core. Both “memrd “and “memwr” will be
invalid when “memack” changes to be low, and either “memaddr” or “memdatao” will be delayed for
several periods.
In read cycle, Fabric places the read data to “memdatai” bus and does not output a valid “memack” after
one or several cycles until the fabric data is ready after the “memrd” is asserted. EMIF read waveform is
shown in the following figure.
clkemif
memdatai
memaddr
...
...
...
...
memrd
memack
Figure 29 EMIF Read Waveform
In write cycle, when the “memwr” is asserted, Fabric writes the “memdatao” to the extended memory and
sends a valid “memack” to MSS on the next cycle.
EMIF write waveform is shown in the following figure:
clkemif
memaddr
memdatao
...
...
...
memwr
memack
Figure 30 EMIF Write Waveform
3.6 RTC
The RTC circuitry has analog and digital parts. The 8051 RTC SFRs and control signals are partitioned
to the CME-M5 family device core VCCINT power domain, while the internal time counters relative
circuitry is partitioned to RTC power domain. The RTC analog circuitry is in the RTC power domain. The
external battery supplies the RTC power via the VCCRTC and GNDRTC pins and ensures the normal
operation of the RTC, whether the CME-M5 family device is power on or down. The circuitry partition
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CME-M5 Family Data Sheet
makes the battery to run for long time.
The RTC crystal connection circuitry is shown in the following figure.
RTCXO
15M
CME Device
RTCXI
22P
22P
32.768K
Figure 31 RTC Crystal Connection Circuitry
3.7 MSS in System Management
Via special extended SFRs, the MSS can control certain components of CME-M5 family, such as special
configuration register, PLL and CFG_DYN_SWITCH multiplexer registers in system. The MSS can
control the ISC, PLL reconfiguration and clock dynamic switch functions directly in system by the
extended SFRs operation.
3.7.1
Device Register
The device registers directly determine and control the device working functions and status. There are
two types of registers: one is the ISC register, the other is the PLL and gclk_switch multiplexer clock
registers.
Table 29 ISC Register
Register
ISCREG
Location
1
Attribute
R/W
Reset Value
0x00000000
Description
[31:8]: Flash start address for read access
[0]: Bit0 ISCEN: reconfiguration enable, be
used to trigger the reconfiguration
sequence, auto clear
0: disable 1:enable
Table 30 Global Clock Register
Register
Location
Attribute
Reset Value
Description
DIVM
6
R/W
0
PLL 0/1 loop-divider M
DIVN
5
R/W
0
PLL 0/1 pre-divider N
DIVC0
4
R/W
0
PLL 0/1 post-divider C0
DIVC1
3
R/W
0
PLL 0/1 post-divider C1
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CME-M5 Family Data Sheet
Register
Location
Attribute
Reset Value
DIVC2
2
R/W
0
PLL 0/1 post-divider C2
DIVC3
1
R/W
0
PLL 0/1 post-divider C3
0
Dynamical control register
[7:6]: reserved
[5]: Pll 0/1 reset control bit
1:reset PLL, 0: PLL work
[4]: Pll 0/1 power down control bit
0:Down PLL,1:On PLL
[3:0]: see Table 24
[3]: CFG_DYN_SWITCH 3/7 output select
0: gclk source is in0,1: gclk source is in1
[2]: CFG_DYN_SWITCH 2/6 output select
0: gclk source is in0,1: gclk source is in1
[1]: CFG_DYN_SWITCH 1/5 output select
0: gclk source is in0,1: gclk source is in1
[0]: CFG_DYN_SWITCH 0/4 output select
0: gclk source is in0,1: gclk source is in1
DYN_
CTRL[7:0]
3.7.2
0
R/W
Description
ISC Register Frame
When accessing the ISC register, please follow the frame below, which is a 32-bit header followed by a
32-bit write or read data.
Table 31 ISC Header Format
Bit[31:29]
Bit[28]
Bit[27]
Bit[26]
0
0
0
Bit[25]
Bit[24]
Bit[23:10]
Bit[9:0]
0
14’h1f
10 h1
1: write
3’h001
3.7.3
0: read
Extended SFR
There are three types of SFR, ISC SFR, RTC SFR, global clock SFR and direct switch SFR.
The ISC SFR is used to transform the data between the MSS and device register. The MSS uses the
RTC SFRs to access RTC internal registers. The MSS manages the clock functions via the clock SFR.
The MSS accesses and controls the relative function directly via the direct switch SFR.
Table 32 Register Definition
Register
Location
Attribute
Reset
Value
ISCDATD0
AC
R/W
0x00
ISC data [7:0]
ISCDATD1
AD
R/W
0x00
ISC data [15:8]
ISCDATD2
AE
R/W
0x00
ISC data [23:16]
ISCDATD3
AF
R/W
0x00
ISC data [31:24]
Description
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CME-M5 Family Data Sheet
Register
Location
Attribute
Reset
Value
Description
ISCCMD
F2
R/W
0x00
[7] Write instruction
1: trigger to write, auto-return to zero when
completed.
ISCHEADER0
F3
R/W
0x00
ISC header [7:0]
ISCHEADER1
F4
R/W
0x00
ISC header [15:8]
ISCHEADER2
F5
R/W
0x00
ISC header [23:16]
ISCHEADER3
F6
R/W
0x00
ISC header [31:24]
0x00
[7]WRITE go
1: write serial command,
self-cleared when done
[6:0] reserved
RTCCMD
E5
R/W
RTCSEL
E6
R/W
0x00
[7:5]reserved
[4] 1: write operation, 0: read operation
[3:0] Register Address defined in RTC
(See MSS 8051 Subsystem User Guide).
RTCDATA
E7
R/W
0x00
write or read RTC data
0x00
[7]WRITE go
1: write serial command,
self-cleared when done
[6:0] reserved
GCLKCMD
F8
R/W
GCLKADDR
F9
R/W
0x00
[7]reserved
[6:5]clock generator select
00: clock generator 0
01: clock generator 1
[4] WRITE/READN
1: write
0: read
[3:0] Register address defined in clock register
table
GCLKDATA
FA
R/W
0x00
write to or read from global clock data
0x00
[7] PLL 1 locked status, 1: locked, 0: not locked
[6] PLL 0 locked status, 1: locked, 0: not locked
[5:1] Reserved
[0] MSS clock switch
1: select the gclk
0: select the internal oscillator
ISMDIRCTRL
3.7.4
FB
R/W
MSS In System Configuration
The configuration Image of CME-M5 family consists of FPGA configuration data and MSS programming
code. FPGA configuration data sizes are substantially about 0x30000 byte, while MSS code size
changes with the size of program. The configuration Image is stored in SPI FLASH. Sector is the
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CME-M5 Family Data Sheet
smallest unit to store Images, one image need about 3 sectors. In addition, one Image can take more
than one sectors. The following figure describes mapping of multi-Image stored in SPI FLASH, therein
the Image size is smaller than three sectors. Configuration packer in Primace can generate .mcf file with
multi Images, while Download can download Images of .mcf into SPI FLASH once. Utilizing ISC features,
CME-M5 family can make use of SPI FLASH space to expand the CME-M5 family device volume in
return, and in other words, CME-M5 family can fulfill several CME-M5 family FPGAs if each of the
multi-image logic can be implemented by CME-M5.
SPI-FLASH
address
0000000
SFR
bitstream
Image1
ISCCMD
ISCREG
firmware
ISCDATA
0030000
ISCHEADER
bitstream
Image2
firmware
MSS
0060000
…
…
…
ISCEN
bitstream
Image3
Configuration
firmware
CME
Device
SPI Interface
Figure 32 ISC
The following example describes that the 8051 program reconfigures the CME-M5 family device using
the Image 2.
Write SPI-FLASH Image starts address to device ISCREG [31:8], and then sets ISCREG [0] to trigger
the configuring process.
ISC steps are as follows:
//Switch the 8051 clock to internal osc
1) ISMDIRCTRL = 0;
//Write frame header, refer to Table 31 ISC Header Format
2) ISCHEADER0 = 0x01;
ISCHEADER1 = 0x7c;
ISCHEADER2 = 0x00;
ISCHEADER3 = 0x22;
//Write SPI-FLASH address and trigger the reconfiguration refer to and Table 32 and Table 29 ISC
Register
3) ISCDATA0 = 1;
ISCDATA1 = 0x00;
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CME-M5 Family Data Sheet
ISCDATA2 = 0x00;
ISCDATA3 = 0x03;
//Write ISCCMD to enable data write to ISC register
4) ISCCMD = 0x80;
3.7.5
MSS in System Clock Configuration
If you want to use the clock configuration in system, you must get familiar with the clock network path
from the clock sources to the special gclk and its mechanism. For more information, see Table 24 Clock
Routability Table.
(1) PLL Configuration
MSS can reconfigure the PLL and make the PLL output another frequency. The following example is to
change the PLL0 clkout0 frequency from 100 MHz to 50 MHz.
fIN = 20MHz, m = 40, n =1, c0 =8;
fVCO = = fIN * (m+1) /( n+1) = 800MHz;
fclkout0 = fVCO / (c0+1) = fIN * (m+1) /( (n+1) * (c0+1)) = 100MHz;
The steps are listed as follows:
//Switch the 8051 clock to internal osc
1) ISMDIRCTRL = 0;
2) Select the PLL0 in PLL wizard of Primace.
//Write GCLKADDR to select PLL0, DIVC0 (4)
3) GCLKADDR = 00010100B
//Write new c0 to GCLKDATA
4) GCLKDATA = 16
//Write new c0 to PLL C0 register from GCLKDATA
5) GCLKCMD = 0x80
After the steps, the clkout0 of PLL0 will output a 50MHz clock.
(2) GCLK Dynamic Switch
MSS can switch the gclk from one clock to another clock dynamically.
The following example is to switch the GCLK [5] from PLL1 clkout1 to PLL1 clkout0. The steps are listed
as follow:
//Switch the 8051 clock to internal osc
1) ISMDIRCTRL = 0;
2) Select the PLL1 in PLL wizard of Primace.
3) Instantiate the CFG_DYN_SWITCH make the parameter gclk_mux is 5
4) Connect the PLL1 clkout0 to in1 and clkout1 to in0 of CFG_DYN_SWITCH
//Write GCLKADDR to select PLL1, DYN_ CTRL [7:0] (0)
5) GCLKADDR = 00110000B
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CME-M5 Family Data Sheet
//Write new DYN_ TRL to GCLKDATA, select the clkin1 as the source of gclk[5]
6) GCLKDATA = 00010010
//Write new value to DYN_CTRL registers from GCLKDATA
7) GCLKCMD = 0x80
(3) MSS Clock Dynamic Switch
The MSS can switch MSS clock dynamically between gclk and internal OSC via CFG_DYN_SWITCH.
All the above 8051 In System managements should switch the MSS clock to OSC before the following
actions.
Steps of switching between the gclk and OSC are listed as follows:
//MSS clock switch to gclk
1) ISMDIRCTRL = 0x1
//MSS clock switch to OSC
1) ISMDIRCTRL = 0x0
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CME-M5 Family Data Sheet
4 Configuration and Debug
4.1 Configuration Mode
There are three configuration modes: JTAG, AS and PS mode. AS, PS mode configuration are controlled
by a mode-select pin MSEL, as described in table below
Note: CME-M5 family with FLASH only provides two modes, AS and JTAG.
Table 33 Configuration Mode
Mode select pin
MSEL
4.1.1
Mode
Description
0
AS
Active Serial mode. The chip will be configured automatically.
Configuration data is stored in the SPI flash.
1
PS
Chip acts as slave.
External microcontroller feeds configuration data into the chip.
0/1
JTAG
JTAG-based configuration. This mode takes higher privilege over AS
and PS modes
AS Mode
In AS configuration mode, CME-M5 family POR or pin nCONFIG reset reads configuration data from SPI
flash 0 address automatically, and configures FPGA and embedded RAM of MSS.
The following figure illustrates the AS mode of CME-M5 family without FLASH.
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CME-M5 Family Data Sheet
VCC
VCC
10K
10K
10K
Pin 1
Pin 2
TMS
TDI
TCK
TDO
MSEL
nCONFIG
nCS
sclk
SDO
SDI
JTAG
10K
SO
SI
SPI Flash
sclk
CS#
Figure 33 AS Configuration without Flash
The following figure illustrates the AS mode of CME-M5 family with FLASH.
VCC
VCC
10K
10K
10K
Pin 1
Pin 2
TMS
TDI
TCK
TDO
nCONFIG
MSEL
JTAG
10K
Figure 34 AS Configuration with Flash
4.1.2
PS Mode
In the PS mode, CME-M5 family works as slave device, receive configuration data from external master
controller passively. SPI Master cannot read configuration data from CME-M5 family.
The following figure shows CME-M5 family in PS configuration.
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CME-M5 Family Data Sheet
VCC
VCC
10K
10K
10K
Pin 1
Pin 2
TMS
TDI
TCK
VCC
TDO
MSEL
nCONFIG
nCS
sclk
SDO
SDI
JTAG
10K
SO
SI
sclk
SPI Master
CS#
Figure 35 PS Configuration
4.1.3
JTAG Mode
There are two JTAG devices inside CME-M5 family, one is for fabric debugging and configuration,
another is for OCDS of MCU. These two JTAG devices are cascaded into one JTAG chain according to
the IEEE standard.
In JTAG mode, JTAG host computer configures and debugs both FPGA and MSS through CME-M5
family JTAG interface.
JTAG interface has higher priority than other configuration modes, and can download configuration files
and debug device.
4.2 SPI Flash
SPI-Flash is used for configuring CME-M5 family and can be operated in user mode, no matter it is
embedded or external configured SPI-Flash.
(1) Using embedded SPI-Flash
Invoke spi_interface in user design, to use SPI-FLASH in CME-M5 family device. For embedded
SPI-Flash datasheet, please refer to GD25QXX_Rev1.0.pdf.
Table 34 Embedded SPI Interface Port
Port Name
Type
Description
sclk
Input
spi flash input clock
sdo
output
spi flash serial output data
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CME-M5 Family Data Sheet
Port Name
Type
Description
cson
Input
spi flash chip select，low active
sdi
Input
spi flash serial input data
(2) Using External SPI-Flash
When using external SPI-Flash, follow the connection illustrated in Figure 33, and set corresponding IO
as user IO during user design. See SPI related contents of 7.1 Pins Definitions and Rules and 7.2 Pin
List .
4.3 ISC
ISC (In System Configuration) enables MSS to re-configure CME-M5 family dynamically or statically.
ISC can only be achieved in AS mode.
During static re-configuration, MSS program writes addresses and instructions to ISC corresponding
SFR to make CME-M5 family re-load corresponding Image from certain SPI Flash address, to achieve
the reconfiguration of CME-M5 family device.
During dynamic re-configuration, MSS program reads Image from external (USART or other interfaces),
writes to corresponding Image space through SPI interface, and updates the Image. Then MSS writes
addresses and instructions to corresponding ISC SFR to configure CME-M5 family with the updated
Image. For more details, see 3.7.4 MSS In System Configuration.
4.4 Debug
There are two JTAG devices inside CME-M5 family: one is for fabric debugging and configuration, the
other is for OCDS of MCU, the two JTAG devices are cascaded into one JTAG chain according to the
IEEE standard. The CME-M5 family device identifies the different device operations and transforms the
data to the right JTAG device automatically.
4.5 Power-On-Reset (POR)
CME-M5 family device has internal POR circuits to monitor VCCINT and VCCIO voltage levels during
power-up. The POR circuit can keep the device in reset state until VCCINT and VCCIO reach the trigger
point. After the device enters into user mode, the POR circuit continues monitoring the VCCINT voltage
levels, but does not monitor VCCIO voltage anymore. POR is also controlled by external manual reset
control signal.
The POR circuit has the following features:
Power-up monitor, trigger point:
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CME-M5 Family Data Sheet
- VCCINT: 0.75V-1.08V
Power down monitor, trigger point:
- VCCINT: 0.65V-0.9V
Delay time: typical 4.9ms, range 3.3ms ~ 7.4ms
4.6 eFUSE Program
The eFUSE is a macro that contains electrically programmable fuses which is One Time Program
memory. Using Primace tool E-Fuse Burner can program the eFUSE via CME download cable. The two
additional FUSE_CLK, VDDQ pins and JTAG pins should be connected as shown in the following figure.
For more information about FUSE_CLK and VDDQ pins definition and pinouts, see Chapter 7 Pins and
Package.
VCC
VCC
10K
Pin 1
Pin 2
10K
10K
TMS
TDI
TCK
TDO
nCONFIG
MSEL
VDDQ
FUSE_CLK
JTAG
10K
1K
Figure 36 eFUSE Program Schematic
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CME-M5 Family Data Sheet
5 Security
The CME-M5 family device has several security levels to help protect customer products and benefits.
Configuration bitstream encryption using 128 bit AES
Efuse-based protection mechanism
SPI-based flash protection mechanism
5.1 Bitstream Generation Security Level
During the test and debug phase of a design, you can decide to leave the JTAG interface in the design
for possible maintenance or for random check-ups after the design goes into production. While this is
handy for the designer, it can leave a potential security hole.
The Bitstream Generator adds security information to configuration .acf file based on the security setting
in Primace. As shown in the following table, the Bitstream Generator has three settings: the first one is
the default, and the remaining two (Level1 and Level2) are optional to provide additional security. JTAG
can be fully or partially disabled via JTAG selection (Except special configuration memory).
Table 35 Bitstream Generator Security Level Settings
Security Level
Description
None
Default. JTAG unrestricted access to all configuration memory and functions
Level1
Disable JTAG to access the SPI-FLASH, fabric configuration memory or MSS
memory
Level2
Disable JTAG to access any memory completely
There are three settings for Bitstream Generator in Primace: prot_flagn, read_disable0 and
read_disable1. After the setting is completed, the Bitstream Generator will add security bits to the
configuration bitstream. User can decide to use a 128-bit key set as the AES algorithm input to encrypt
the bitstream according to the three level settings of Primace Bitstream Generator.
(1) prot_flagn
If Bitstream Generator is set to prot_flagn, the prot_flagn security bit will be programmed to SPI-FLASH.
The security bit is employed to protect flash content, to prevent fabric and register reading/writing, and to
prevent accessing MCU memory space via OCDS. Once prot_flagn is asserted, only several flash
instructions can be sent to flash, e.g. WREN, BE, RDSR, WRSR. So The SPI-FLASH can’t be accessed
by JTAG except the erase operation.
An internal signal prot_flagn is employed to obtain value of the security bit and control the security
protection. When power-up, the prot_flagn security bit stored in the SPI-FLASH is not loaded to the
internal prot_flagn, so the internal prot_flagn is LOW and active by default. User must send a specified
set of JTAG instruction to transfer the prot_flagn bit from SPI-FLASH to internal prot_flagn signals which
is then used to provide security control over the whole chip referring to user setting.
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CME-M5 Family Data Sheet
(2) read_disable0
The security signal read_disable0 is stored in the internal register after the device is configured by the
bitstream. The signal read_disable0 that is high active is used to prevent fabric chain reading, and to
prevent accessing MCU memory space via OCDS.
When power-up, read_disable0 is 0 by default to enable JTAG read. The read_disable0 bit stored in the
internal register will load to the read_disable0. If it is written with 1, then it can’t be changed by writing
with 0.
(3) read_disable1
The security signal read_disable1 is generated by the SECU chain. The signal read_disable1 is also
used to prevent fabric chain reading, and to prevent accessing MCU memory space via OCDS.
When power-up, read_disable1 is 1 to enable the security protection. If the SECU chain matches the
fixed data pattern, read_disable1 will change to 0, so that read_disable1 is de-asserted and JTAG can
read FPGA static configuration SRAM and MCU memory, otherwise, the JTAG will be disabled.
The JTAG can’t read the fabric chain and MCU memory space if anyone of the three security signals is
active.
5.2 On-Chip eFuse
The CME-M5 family device has two 128-bit eFUSE. The eFUSE0 is used to store the 128-bit AES cipher
key that is used to decrypt the encrypted configuration bitsream generated by Primace Bitgen tool. The
eFUSE1 is used to store the security protection bits and other reserved information.
The following table provides more information about security bit.
Table 36 Security Bit
eFUSE1 Bit
Description
[5]
Decryption flag:
1: the key stored in Efuse0 used to decrypt the bitstream. The key must match
with the key that is used for encryption by user in Primace.
0: Bitstream decryption is not required
[4]
JTAG & OCDS disabled:
1: disable the JTAG operation, whether the Security Level Settings is set or not.
The cipher key and security bits can be programmed to eFUSE0/1 by Primace tool to prohibit the cloners,
over builders, and reverse engineers from embezzling the user design. Even if the embedded or external
SPI-FLASH content is copied completely, the user’s intellectual property rights can still be protected, as
long as the cipher key stored in Efuse0 is not decrypted.
5.3 Embedded SPI-Flash Hidden Bitstream
The embedded SPI-Flash is used to store CME-M5 family configuration data.
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CME-M5 Family Data Sheet
The CME-M5 family device bitstream is hidden during configuration because the Flash is inside the
FPGA. This configuration provides a starting point for security in a design, where it cannot directly be
copied from the Flash.
5.4 AES Security
Advanced Encryption Standard (AES) is a specification for the encryption of electronic data. The AES
algorithm is adopted to encrypt the configuration bitstream using a 128-bit key. The CME-M5 family will
decrypt the encrypted bitstream using the 128-bit key stored in Efuse0. The configuration succeeds if the
two 128-bit keys match, otherwise the configuration fails and the device can’t work.
The following figure illustrates the encryption and decryption process.
Step 3. Configure the device using
encrypted configuration data.
Step 1. Generate the encrypted configuration data and store
in configuration memory.
Primace
abc
Bitgen
Configuratio
n Data
AES
Encryptor
Encrypted
Configuration
Data
Encryption Key
Programming
File
Memory
Storage
Encrypted
Configuration
Data
Encrypted
Configuration
Data
AES Decryptor
Check with
Expected Value
Efuse
Volatile Key
Storage
Security Setting
Volatile Key
FPGA
Yes/No
Step 2. Program
volatile key into Efuse. Volatile
Key
Figure 37 Encryption and Decryption Process
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CME-M5 Family Data Sheet
6 DC & Switching Characteristics
All parameter limits are representative of worst-case supply voltage and junction temperature conditions.
The following information applies unless otherwise noted: AC and DC characteristics are
specified using the same numbers for both commercial and industrial grades. All parameters
representing voltages are measured with respect to GND.
6.1 DC Electrical Characteristics
6.1.1
Absolute Maximum Ratings
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other
conditions beyond those listed under the Recommended Operating Conditions is not implied. Exposure
to absolute maximum conditions for extended periods of time adversely affects device reliability.
Table 37 Absolute Maximum Ratings
Symbol
Description
VCCINT
VCCIO
Min
Max
Units
Internal supply voltage
-0.5
1.3
V
I/O driver supply
voltage
-0.5
5.5
V
Voltage applied to all
User I/O pins and
dual-purpose pins
VIN
Voltage applied to all
Dedicated pins
Electrostatic Discharge
Voltage
VESD
Conditions
Driver in a high-impedance
state
-0.95
V
-0.8
V
Human body model
0
±2000
V
Charged device model
-
±500
V
Machine model
-
±200
V
TJ
Junction temperature
-40
125
°C
TSTG
Storage temperature
–65
150
°C
6.1.2
Power Supply Specifications
Table 38 Supply Voltage Thresholds for Power-On Reset
Symbol
Description
Min
Max
Units
VCCINTT
Threshold for the VCCINT supply
0.7
V
VCCIOT
Threshold for the VCCIO supply
2.26
V
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CME-M5 Family Data Sheet
Table 39 Supply Voltage Ramp Rate
Symbol
Description
Min
Max
Units
VCCINTR
Ramp rate from GND to valid
VCCINT supply level
10
ms
VCCIOR
Ramp rate from GND to valid
VCCIO supply level
10
us
Note: The VCCINT must be powered to threshold before the VCCIO.
V
VCCIO
3V
VCCIOT
TVCCIOR
TVCCINTR
VCCINT
1V
VCCINTT
T1
T3
T2 T4
T
T4>T1
Figure 38 Power on waveform
6.1.3
General Recommended Operating Conditions
Table 40 Recommended Basic Operating Conditions for Single I/O
Symbol
Min
Typ
Max
Junction temperature
-40°C
25°C
85°C
VCCIN
T
Core power
1.0V
1.1V
1.21V
VCCA_
PLL
PLL analog power
1.0V
1.1V
1.21V
I/O supply voltage @ 3.3V
2.97V
3.3V
3.63V
I/O supply voltage @2.5V
2.25V
2.5V
2.75V
I/O supply voltage @1.8V
1.62V
1.8V
1.98V
I/O supply voltage @1.5V
1.35V
1.5V
1.65V
TJ
VCCIO
VIH
VIL
Parameter
Input High Voltage @3.3V LVCMOS
2V
VCCIO +0.3
Input High Voltage @2.5V LVCMOS
1.7V
VCCIO +0.3
Input High Voltage @1.8V LVCMOS
0.65*
VCCIO
VCCIO +0.3
Input Low Voltage @3.3V LVCMOS
-0.3
0.8V
Input Low Voltage @2.5V LVCMOS
-0.3
0.7V
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CME-M5 Family Data Sheet
Symbol
Parameter
Min
Input Low Voltage @1.8V LVCMOS
VT+
VT-
Typ
0.35*
VCCIO
-0.3
Schmitt trig Low to High threshold point @3.3V
0.6*
VCCIO
Schmitt trig Low to High threshold point @2.5V
0.6*
VCCIO
Schmitt trig Low to High threshold point @1.8V
0.6*
VCCIO
Schmitt trig High to Low threshold point @3.3V
0.4* VCCIO
Schmitt trig High to Low threshold point @2.5V
0.4* VCCIO
Schmitt trig High to Low threshold point @1.8V
0.4* VCCIO
TJ
Junction Temperature
IL
Input Leakage Current
±1μA
Output low voltage @IOL=2,4…16mA @3.3V
0.4V
Output low voltage @IOL=2,4…16mA @2.5V
0.7V
Output low voltage @IOL=2,4…16mA @1.8V
0.45V
Output high voltage @ IOH=2,4…16mA @3.3V
2.9V
Output high voltage @ IOH=2,4…16mA @2.5V
1.7V
Output high voltage @ IOH=2,4…16mA @1.8V
VCCIO -0.45
VOL
VOH
-40°C
Low level output current @VOL=0.4V
VCCIO =3.3V
25°C
Min
Typ
Drive Strength=4mA
>4mA
6
Drive Strength=8mA
>8mA
16
Drive Strength=12mA
>12mA
19
Drive Strength=16mA
>16mA
25
Min
Typ
Drive Strength=4mA
>4mA
5
Drive Strength=8mA
>8mA
14
Drive Strength=12mA
>12mA
16.8
Drive Strength=16mA
>16mA
21
Min
Typ
Drive Strength=4mA
>4mA
4
Drive Strength=8mA
>8mA
10
Drive Strength=12mA
>12mA
13
Drive Strength=16mA
>16mA
16
Min
Typ
Low level output current @VOL=0.7V
VCCIO =2.5V
IOL
Max
Low level output current @VOL=0.45V
VCCIO =1.8V
Low level output current @VOL=0.375V
VCCIO =1.5V
Drive Strength=4mA
2.8
Drive Strength=8mA
7
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125°C
Max
Max
Max
Max
63
CME-M5 Family Data Sheet
Symbol
Parameter
Min
Drive Strength=12mA
8.4
Drive Strength=16mA
11
High level output current @VOH=2.9V
VCCIO =3.3V
Min
Typ
Drive Strength=4mA
>4mA
6
Drive Strength=8mA
>8mA
17
Drive Strength=12mA
>12mA
18
Drive Strength=16mA
>16mA
25
Min
Typ
Drive Strength=4mA
>4mA
5.4
Drive Strength=8mA
>8mA
14
Drive Strength=12mA
>12m
16
Drive Strength=16mA
>16mA
19
Min
Typ
Drive Strength=4mA
>4mA
4
Drive Strength=8mA
>8mA
11
Drive Strength=12mA
>12mA
13
High level output current @VOH=2.1V
VCCIO =2.5V
IOH
Typ
High level output current @VOH= VCCIO -0.45
VCCIO =1.8V
Drive Strength=16mA
Max
Max
Max
Max
15
High level output current
@VOH= VCCIO -0.375 VCCIO =1.5V
Min
Typ
Drive Strength=4mA
2.8
Drive Strength=8mA
7.8
Drive Strength=12mA
8.5
Drive Strength=16mA
11
Max
Table 41 Recommended Operating Conditions of Programmable Transmitter Features
Supported Voltage and
Current Capabilities
Attributes
Value
4mA
IOH
8mA
12mA
16mA
Drive strength
4mA
IOL
8mA
12mA
16mA
slow
Slew-rate control
Rising Slew
nominal
fast
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CME-M5 Family Data Sheet
Supported Voltage and
Current Capabilities
Attributes
Value
slow
nominal
Falling Slew
fast
TX impedance control
Pull up
75kΩ
Pull down
50kΩ
keeper
50kΩ to 75kΩ
Note: All IOs support single-ended IO standards, such as LVCMOS. Measured between 10% and 90%
VCCIO
Table 42 Quiescent Current Requirements
Symbol
Description
IFPINTQ
Quiescent VCCINT supply current only for
Fabric.
18
mA
IMSSINTQ
Quiescent VCCINT supply current only for
MSS include the 8051 SRAM (128KB).
2
mA
Quiescent VCCINT supply current for
whole device.
20
mA
IINTQ
Device
Typical(1)
Maximum(2)
Units
Note:
(1) The numbers in this table are based on the conditions set forth in General Recommended Operating
Conditions.
(2) Quiescent supply current is measured with all I/O drivers in a high-impedance state and with all
pull-up/pull-down resistors at the I/O pads disabled. Typical values are characterized using typical
devices at room temperature (TJ of 25°C at VCCINT = 1.1V).The FPGA is programmed with a
"blank" configuration data file (i.e., a design with no functional elements instantiated).The maximum
limits are tested for each device at the respective maximum specified junction temperature and at
maximum voltage limits with MAX VCCINT and VCCIO.
(3) The maximum numbers in this table indicate the minimum current each power rail requires in order
for the FPGA to power-on successfully.
6.2 Switching Characteristics
Timing parameters and their representative values are selected for inclusion below either because they
are important as general design requirements or they indicate fundamental device performance
characteristics.
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CME-M5 Family Data Sheet
6.2.1
Clock Performance
Table 43 Recommended Operating Frequency of Global Clock
6.2.2
Symbol
Max Frequency
Units
GCLK
500
MHz
I/O Performance
Table 44 Recommended Operating Frequency of I/O
IO Standard
Primary Usage
Max
Frequency
LVCMOS/LVTTL
1.5v/1.8v/2.5v/3.3v general purpose
160 MHz
6.2.3
PLB Performance
Table 45 Recommended Operating Frequency of PLB
Symbol
Description
Speed
Min
Units
Max
ADD16
16 bit adder performance @
recommended operating condition.
400
ADD32
32 bit adder performance @
recommended operating condition.
360
Add64
64 bit adder performance @
recommended operating condition.
215
CNT8
8 bit counter performance @
recommended operating condition.
720
CNT16
16 bit counter performance @
recommended operating condition.
640
CNT32
32 bit counter performance @
recommended operating condition.
580
6.2.4
MHz
EMB5K Performance
Table 46 Recommended Operating Frequency of EMB5K
Symbol
EMB5K
Description
Speed
Min
EMB5K performance at
recommended operating condition.
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Units
Max
MHz
200
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CME-M5 Family Data Sheet
6.2.5
DSP Performance
Table 47 Recommended Operating Frequency of DSP
Symbol
DSP
Description
Speed
Min
Units
Max
DSP using register path.
200
DSP not using the register path.
200
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MHz
67
CME-M5 Family Data Sheet
7 Pins and Package
7.1 Pins Definitions and Rules
Table 48 Pins Definitions and Rules
Pin Name
Direction
Description
User I/O Pins
IOXX_#
inout
user I/O pin
Multi-Function Pins
Multi-function pins are labeled IOXXX/YYY_#, where YYY represents
one or more of the following functions in addition to being general
purpose user I/O.
If not used for their special function, these pins can be user I/O.
IOXXX/ZZZ_#
Multi-Function Pins: SPI serial configuration Pins
SCLK
input/output
In passive serial configuration mode, SCLK is a clock input used to
clock configuration data from external device source into device.
In active serial configuration mode, SCLK is a clock output from device.
The pin can be used as regular user I/Os after configuration.
SDI
input
Dedicated configuration data input pin in AS mode.
The pin can be used as regular user I/Os after configuration in AS mode
output
Active serial data output from the device.
The pin can be used as regular user I/Os after configuration in AS
mode.
This pin is only user I/O pin when the device is in PS mode.
output
or input
Chip select output to enable/disable a serial configuration device.
This output is used during AS mode. The pin can be used as regular
user I/Os after configuration in AS mode.
it is used as chip selection control (input) during PS.The pin can be used
as regular user I/Os after configuration in PS mode.
SDO
nCS
Multi-Function Pins: Configuraiton Pins
CONF_DONE
output
This is a dedicated configuration status pin, the pin will output high
during configuration. The pin can be used as regular user I/Os after
configuration.
0: Active Serial mode, 1 Passive Serial mode.
The pin can be used as regular user I/Os after configuration.
MSEL
Multi-Function Pins: Clock Pins
CLKX
input
These clock pins connect to Global Clock Buffers.
These pins become regular user I/Os when not needed for clocks.
Multi-Function Pins: Efuse clock
FUSE_CLK
input
Efuse program clock.
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CME-M5 Family Data Sheet
Pin Name
Direction
Description
Dedicated Pins: JTAG
TCK
input
TCK Input Boundary-Scan Clock.
TDI
input
TDI Input Boundary-Scan Data Input.
TDO
output
TDO Output Boundary-Scan Data Output.
TMS
input
TMS Input Boundary-Scan Mode Select.
Dedicated Pins: JTAG
nCONFIG
input
Chip global reset input. Active low.
Dedicated Pins: Crystal Pins
XIN
input
External crystal input.
If not used it is better to connect to GND.
XOUT
output
Output to crystal. Not used can be floating.
Dedicated Pins: RTC Pins
RTCXI
input
External crystal input for RTC 32K clock.
If not used it is better to connect to GND.
RTCXOUT
output
32K clock output to crystal.
If not used can be floating.
VCCRTC
N/A
RTC power. 2.0-3.3V.
GNDRTC
N/A
RTC ground.
Dedicated Pins: Power
VCCIO
N/A
Digital power for IO.
VCCINT
N/A
Digital power for core, 1.1V.
VCCA_PLL
N/A
Analog power for PLLs, 1.1V.
VDDQ
N/A
Efuse program power.
GND
N/A
Digital ground.
Note:
(1) VCCIO_0 and VCCIO_2 MUST be powered at 3.3V.
(2) VDDQ should connect to the pin6 of 10 pin header on CME JTAG cable and use a 1K resistor to
make the signal pull down to GND for programming the Efuse.
(3) FUSE_CLK should connect to CME JTAG cable 10 pin header pin8.
7.2 Pin List
7.2.1
LQFP144 Package Pin List
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CME-M5 Family Data Sheet
Table 49 LQFP144 Package Pin List
No.
LQFP144
No.
LQFP144
No.
LQFP144
1
VCCIO_0
40
IO31_1
79
CONF_DONE_2
2
GND
41
VCCIO_1
80
IO56/MSEL_2
3
IO1_0
42
IO32_1
81
IO57/SDO_2
4
IO2_0
43
IO33_1
82
VCCIO_2
5
IO3_0
44
VCCINT
83
IO58/SCLK_2
6
IO4_0
45
IO34_1
84
IO59_2
7
IO5_0
46
IO35_1
85
GND
8
IO6_0
47
GND
86
VCCINT
9
IO7_0
48
IO36_1
87
IO60_2
10
IO8/nCS_0
49
IO37_1
88
IO61_2
11
IO9_0
50
IO38_1
89
VCCIO_2
12
VCCINT
51
IO39_1
90
GND
13
IO10_0
52
VCCIO_1
91
IO62_2
14
IO11/SDI_0
53
IO40_1
92
IO63_2
15
IO12_0
54
IO41_1
93
IO64_2
16
IO13_0
55
GND
94
VCCINT
17
IO14_0
56
IO42_1
95
IO65_2
18
IO15_0
57
IO43_1
96
IO66_2
19
IO16_0
58
IO44_1
97
GND
20
IO17_0
59
IO45_1
98
IO67_2
21
IO18_0
60
IO46_1
99
IO68_2
22
IO19_0
61
IO47_1
100
IO69_2
23
VCCIO_0
62
IO48/CLK0_1
101
IO70_2
24
GND
63
IO49/CLK1_1
102
IO71_2
25
IO20_0
64
VCCIO_1
103
IO72_2
26
IO21_0
65
IO50/CLK2_1
104
VCCIO_2
27
IO22_0
66
IO51/CLK3/FUSE_CLK_1
105
IO73_2
28
IO23_0
67
IO52_1
106
IO74_2
29
IO24_0
68
IO53_1
107
IO75_2
30
VCCINT
69
IO54_1
108
IO76_2
31
IO25_0
70
VDDQ_1
109
RTCXI_3
32
IO26_0
71
XIN_1
110
RTCXO_3
33
IO27_0
72
XOUT_1
111
VCCRTC
34
IO28_0
73
VCCA_PLL _2
112
GNDRTC
35
GND
74
nCONFIG_2
113
IO77_3
36
VCCIO_0
75
TMS_2
114
IO78/CLK4_3
37
IO29_1
76
TDI_2
115
IO79/CLK5_3
38
IO30_1
77
TCK_2
116
VCCIO_3
39
GND
78
TDO_2
117
IO80/CLK6_3
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CME-M5 Family Data Sheet
No.
LQFP144
118
IO81/CLK7_3
119
IO82_3
120
IO83_3
121
IO84_3
122
GND
123
IO85_3
124
IO86_3
125
IO87_3
126
IO88_3
127
IO89_3
128
VCCIO_3
129
IO90_3
130
IO91_3
131
IO92_3
132
IO93_3
133
IO94_3
134
IO95_3
135
GND
136
IO96_3
137
VCCINT
138
IO97_3
139
IO98_3
140
IO99_3
141
VCCIO_3
142
GND
143
IO100_3
144
IO101_3
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71
CME-M5 Family Data Sheet
7.2.2
TQFP100 Package Pin List
Table 50 TQFP-100 Package Pin List
No.
TQFP100
No.
TQFP100
No.
TQFP100
1
VCCIO_0
37
IO29_1
73
IO49_2
2
GND
38
IO30 _1
74
VCCIO_2
3
IO1_0
39
IO31/CLK0_1
75
IO50_2
4
IO2_0
40
IO32/CLK1_1
76
IO51_3
5
IO3_0
41
VCCIO_1
77
IO52/CLK4_3
6
IO4_0
42
IO33/CLK2_1
78
IO53/CLK5_3
7
IO5_0
43
IO34/CLK3/FUSE_CLK_1
79
VCCIO_3
8
IO6/nCS_0
44
IO35_1
80
IO54/CLK6_3
9
IO7_0
45
IO36_1
81
IO55/CLK7_3
10
VCCINT
46
IO37_1
82
IO56_3
11
IO8_0
47
VDDQ_1
83
IO57_3
12
IO9/SDI_0
48
GND
84
GND
13
IO10_0
49
XIN_1
85
IO58_3
14
IO11_0
50
XOUT_1
86
IO59_3
15
IO12_0
51
VDDA _2
87
IO60_3
16
IO13_0
52
nCONFIG_2
88
IO61_3
17
GND
53
TMS_2
89
IO62_3
18
IO14_0
54
TDI_2
90
VCCIO_3
19
IO15_0
55
TCK_2
91
IO63_3
20
IO16_0
56
TDO_2
92
IO64_3
21
IO17_0
57
CONF_DONE_2
93
IO65_3
22
IO18_0
58
IO39/MSEL_2
94
IO66_3
23
IO19_0
59
IO40/SDO_2
95
GND
24
IO20_0
60
VCCIO_2
96
IO67_3
25
VCCIO_0
61
IO41/SCLK_2
97
VCCINT
26
VCCINT
62
GND
98
IO68_3
27
IO21_1
63
VCCINT
99
IO69_3
28
IO22_1
64
IO42_2
100
IO70_3
29
VCCIO_1
65
IO43_2
30
IO23_1
66
IO44_2
31
IO24_1
67
VCCINT
32
GND
68
GND
33
IO25_1
69
IO45_2
34
IO26_1
70
IO46_2
35
IO27_1
71
IO47_2
36
IO28_1
72
IO48_2
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72
CME-M5 Family Data Sheet
7.2.3
FBGA256 Package Pin List
Table 51 FBGA256 Package Pin List
No.
BGA256
No.
BGA256
No.
BGA256
M14
VCCIO_0
B16
IO31_0
A15
IO60_1
H7
GND
F14
IO32_0
A10
IO61_1
H8
GND
D16
IO33_0
B10
IO62_1
N13
IO1_0
D15
IO34_0
C9
IO63_1
M12
IO2_0
G11
IO35_0
D9
IO64_1
L12
IO3_0
C16
IO36_0
E9
IO65_1
K12
IO4_0
C15
IO37_0
A9
IO66_1
N14
IO5_0
E12
IO38_0
B9
IO67_1
P15
IO6_0
J7
GND
A8
IO68_1
P16
IO7_0
J8
GND
B8
IO69_1
D2
IO8_0
E14
VCCIO_0
C8
IO70_1
R16
IO9_0
F12
IO39_1
C10
VCCIO_1
K11
IO10_0
H12
IO40_1
C7
VCCIO_1
G6
VCCINT
H13
IO41_1
D8
IO71_1
N16
IO11_0
C14
IO42_1
E8
IO72_1
N15
IO12_0
D14
IO43_1
F8
IO73_1
H2
IO13_0
J9
GND
A7
IO74_1
L14
IO14_0
J10
GND
B7
IO75_1
L13
IO15_0
D11
IO44_1
F6
IO76_1
L16
IO16_0
D12
IO45_1
F7
IO77_1
L15
IO17_0
A13
IO46_1
C6
IO78_1
J11
IO18_0
B13
IO47_1
A6
IO79_1
K16
IO19_0
A16
VCCIO_1
C5
GND
K15
IO20_0
C13
VCCIO_1
C12
GND
J16
IO21_0
A14
IO48_1
B6
IO80_1
J15
IO22_0
B14
IO49_1
E7
IO81_1
K14
VCCIO_0
E11
IO50_1
E6
IO82_1
G14
VCCIO_0
E10
IO51_1
A5
IO83_1
H9
GND
A12
IO52_1
A2
IO84_1
H10
GND
B12
IO53_1
B5
IO85_1
J14
IO23_0
G8
VCCINT
A4
IO86_1
J12
IO24_0
A11
IO54_1
B4
IO87_1
J13
IO25_0
B11
IO55_1
E2
IO88/CLK0_1
G16
IO26_0
C11
IO56_1
E1
IO89/CLK1_1
G15
IO27_0
F10
IO57_1
C4
VCCIO_1
F13
IO28_0
F9
IO58_1
A1
VCCIO_1
F16
IO29_0
F11
IO59_1
M2
IO90/CLK2_1
G7
VCCINT
B2
GND
M1
IO91/CLK3/FUSE_CLK_1
F15
IO30_0
B15
GND
D5
IO92_1
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73
CME-M5 Family Data Sheet
No.
BGA256
No.
BGA256
No.
BGA256
D6
IO93_1
G13
GND
M6
IO144_3
A3
IO94_1
J6
IO116_2
P6
IO145_3
B3
IO95_1
K6
IO117_2
M7
IO146_3
C3
IO96_1
L6
IO118_2
K8
IO147_3
D3
IO97_1
K2
IO119_2
R5
IO148_3
M5
VDDQ_1
K1
IO120_2
T5
IO149_3
G9
VCCINT
L2
IO121_2
R6
IO150_3
D7
GND
L1
IO122_2
N7
GND
D10
GND
H6
VCCINT
N10
GND
H15
XIN_1
L3
IO123_2
T6
IO151_3
H16
XOUT_1
N2
IO124_2
L7
IO152_3
D13
VDDA0_2
N1
IO125_2
R7
IO153_3
H5
nCONFIG_2
K4
GND
T7
IO154_3
J5
TMS_2
K13
GND
L8
IO155_3
H4
TDI_2
K5
IO126_2
M8
IO156_3
H3
TCK_2
L4
IO127_2
N8
IO157_3
J4
TDO_2
R1
IO128_2
P8
IO158_3
H14
/CONF_DONE_2
P2
IO129_2
R8
IO159_3
G12
IO99/MSEL_2
P1
IO130_2
T8
IO160_3
D4
IO100_2
M3
VCCIO_2
R9
IO161_3
C1
IO101_2
N3
IO131_2
P7
VCCIO_3
E5
IO102_2
P3
IO132_2
P10
VCCIO_3
E3
VCCIO_2
R3
IO133_2
T9
IO162_3
F5
IO103_2
J3
RTCXI_3
K9
IO163_3
B1
IO104_2
N4
RTCXO_3
L9
IO164_3
H1
IO105_2
L5
VCCRTC_3
M9
IO165_3
C2
IO106_2
F4
GNDRTC_3
N9
IO166_3
E4
GND
M4
GND
R10
IO167_3
E13
GND
M13
GND
T10
IO168_3
G10
VCCINT
H11
VCCINT
R11
IO169_3
F3
IO107_2
T3
IO134_3
T11
IO170_3
D1
IO108_2
T2
IO135_3
P5
GND
G5
IO109_2
R4
IO136_3
P12
GND
F2
IO110_2
T4
IO137_3
R2
GND
F1
IO111_2
N5
IO138_3
R12
IO171_3
G2
IO112_2
E15
IO139/CLK4_3
T12
IO172_3
G1
IO113_2
E16
IO140/CLK5_3
K10
IO173_3
J2
IO114_2
T1
VCCIO_3
L10
IO174_3
J1
IO115_2
P4
VCCIO_3
P9
IO175_3
G3
VCCIO_2
M15
IO141/CLK6_3
K7
VCCINT
K3
VCCIO_2
M16
IO142/CLK7_3
P11
IO176_3
G4
GND
N6
IO143_3
R13
IO177_3
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74
CME-M5 Family Data Sheet
No.
BGA256
No.
BGA256
No.
BGA256
T13
IO178_3
P13
VCCIO_3
L11
IO185_3
M10
IO179_3
T16
VCCIO_3
M11
IO186_3
N11
IO180_3
R15
GND
N12
IO187_3
T14
IO181_3
R14
IO183_3
T15
IO182_3
P14
IO184_3
Table 52 FBGA256 Footprint
1
2
3
4
5
IO86_1
IO83_1
6
7
8
9
IO68_1
IO66_1
10
11
12
13
14
15
IO52_1
IO46_1
IO48_1
IO60_1
VCCIO_
A
16
VCCIO_
IO84_1 IO94_1
IO79_1 IO74_1
IO61_1 IO54_1
1
A
1
IO104_
B
GND
IO95_1
IO87_1
IO85_1
IO80_1 IO75_1
IO69_1
IO67_1
IO70_1
IO63_1
IO62_1 IO55_1
IO53_1
IO47_1
IO49_1
GND
IO31_0
B
IO42_1
IO37_0 IO36_0
C
IO43_1
IO34_0 IO33_0
D
2
IO101/
IO106_
C
VCCIO_
IO96_1
SDO_2
2
IO108_
IO8/nC
D
S_0
IO89/
IO88/
1
IO93_1
GND
VCCIO_
1
IO71_1
IO64_1
GND
IO44_1
IO45_1
IO102_
2
VCCIO_ IO139/
IO82_1 IO81_1
IO72_1
IO65_1
IO51_1 IO50_1
IO38_0
IO140/
GND
2
E
0
CLK4_3 CLK5_3
IO32_0
IO30_0 IO29_0
F
IO27_0 IO26_0
G
IO110_ IO107_ GNDRT IO103_
2
2
C_3
IO112_ VCCIO_
G
2
IO73_1
IO58_1
IO57_1 IO59_1
IO109_
2
IO39_1
IO28_0
2
GND
2
1
LL _2
IO76_1 IO77_1
IO113_
GND
2
F
2
VCCIO_
IO56_1
VCCAP
IO92_1
GND
IO111_
VCCIO_
IO100_
E
CLK1_1 CLK0_1
IO78_1
1
IO97_1
2
VCCIO_
GND
IO99/M
VCCINT VCCINT VCCINT VCCINT VCCINT IO35_0
2
VCCIO_
GND
SEL_2
0
CONF_
IO105/S IO13/S
H
nCONFI
TCK_2
CLK_2
TDI_2
DI_0
XOUT_
VCCINT
GND
GND
GND
GND
VCCINT IO40_1
IO41_1 DONE_
XIN_1
G_2
H
1
2
IO115_
IO114_ RTCXI_
J
IO116_
TDO_2
2
IO120_
2
TMS_2
3
IO119_ VCCIO_
K
GND
IO126_
IO117_
GND
2
IO122_
2
2
IO121_ IO123_
GND
GND
GND
IO147_
IO163_
IO173_
IO18_0
IO24_0
IO25_0
IO10_0
IO4_0
GND
VCCINT
2
2
IO90/
VCCIO_
IO22_0 IO21_0
J
2
2
IO127_ VCCRT IO118_ IO152_
3
3
IO20_0 IO19_0
K
IO155_
IO164_
3
3
IO17_0 IO16_0
L
IO156_
IO165_
3
3
IO157_
IO166_
VCCIO_
3
0
IO174_ IO185_
L
2
IO23_0
2
2
C_3
2
3
3
IO3_0
IO15_0
IO2_0
GND
IO14_0
3
IO91/CL
K3/FUS
M
VDDQ_ IO144_ IO146_
IO179_ IO186_
GND
E_CLK_ CLK2_1
2
1
3
3
3
VCCIO_ IO141/
3
IO142/
M
0
CLK6_3 CLK7_3
IO5_0
IO12_0 IO11_0
N
IO6_0
IO7_0
P
GND
IO9_0
R
1
IO125_
IO124_ IO131_ RTCXO IO138_
IO143_
N
GND
2
IO130_
2
2
_3
3
IO129_ IO132_ VCCIO_
P
3
IO180_
IO187_
3
3
GND
3
IO145_ VCCIO_ IO158_
3
IO1_0
IO175_ VCCIO_ IO176_
GND
2
2
IO128_
R
2
3
IO133_
IO136_
IO148_
2
3
3
VCCIO_ IO184_
GND
3
3
IO150_ IO153_
3
3
IO159_
IO161_
3
3
3
3
IO167_ IO169_
3
3
IO171_
IO177_
IO183_
3
3
3
GND
2
3
3
3
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3
75
CME-M5 Family Data Sheet
VCCIO_ IO135_ IO134_
IO137_
IO149_
IO151_ IO154_
IO160_
IO162_
IO168_ IO170_
IO172_
IO178_
IO181_
IO182_ VCCIO_
T
T
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
7.2.4
VCCINT
VCCIO_2
IOXXX_0
VCCIO_0
VCCIO_3
IOXXX_1
VCCIO_1
GND
IOXXX_2
IOXXX_3
QFN68 Package Pin List
Table 53 QFN68 Package Pin List
No.
QFN68
No.
QFN68
No.
QFN68
1
VCCIO_0
25
IO20_0/CLK1_1
49
IO31_2
2
IO1_0
26
VCCIO_1
50
IO32_2
3
IO2_0
27
IO21/CLK2_1
51
IO33_2
4
IO3_0
28
IO22/CLK3/FUSE_CLK_1
52
IO34_3
5
IO4_0
29
IO23_1
53
IO35/CLK4_3
6
IO5_0
30
IO24_1
54
IO36/CLK5_3
7
VCCINT_0
31
IO25_1
55
VCCIO_3
8
IO6 _0
32
VDDQ_1
56
IO37/CLK6_3
9
IO7_0
33
XIN_1
57
IO38/CLK7_3
10
IO8_0
34
XOUT_1
58
IO39_3
11
IO9_0
35
VDDA_2
59
IO40_3
12
IO10_0
36
nCONFIG_2
60
IO41_3
13
IO11_0
37
TMS_2
61
IO42_3
14
VCCIO_0
38
TDI_2
62
IO43_3
15
IO12_0
39
TCK_2
63
IO44_3
16
IO13_0
40
TDO_2
64
IO45_2
17
IO14_0
41
CONF_DONE_2
65
VCCIO_3
18
VCCINT_1
42
IO27_2
66
IO46_3
19
VCCIO_1
43
IO28_2
67
IO47_3
20
IO15_1
44
VCCIO_2
68
VCCINT_3
21
IO16_1
45
VCCIO_2
22
IO17_1
46
VCCINT_2
23
IO18_1
47
IO29_2
24
IO19_0/CLK0_1
48
IO30_2
Note: The exposed pad at the center of the chip backside should be connected to GND.
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76
CME-M5 Family Data Sheet
7.3 Package Information
7.3.1
LQFP144 Low-profile Quad Flat-Pack Package Specifications
D 1
θ2
D1 2
PIN 1
IDENTI
FIER
θ1
4
14
4
R1
10
9
R2
10
8
1
B
GAGE PLANE
.25
E1
2
E
1
θ
B
S
L
…
A
36
73
37
L1
θ3
A
SECTION A-A
72
b
5
3
c
A
A2
A1
C
6
e
b
0.08
c1
5
SEATING PLANE
5
C
b1
5
WITH PLATING
SECTION B-B
BASE METAL
Symbol
Dimension in mm
Min Nom Max
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R
R1
S
θ
θ1
θ2
θ3
1.60
0.05
1.35 1.40 1.45
0.17 0.22 0.27
0.20 REF
0.12
0.20
0.13 REF
21.85 22.00 22.15
19.90 20.00 20.10
21.85 22.00 22.15
19.90 20.00 20.10
0.50 BSC
0.45 0.60 0.75
1.00 REF
0.15 REF
0.15 REF
0.19 REF
0° 3.5° 7°
7° REF
12° REF
12° REF
C
1
TO BE DETERMINED AT SEATING PLANE
2
DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION
D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSION
INCLUDING MOLD MISMATCH.
3
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS
OR THE FOOT.
4
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
5
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP.
6
A1 IS DEFINED AS THE DISTANCE FROM THE SEATING
PLANE
7
CONTROLLING DIMENSION : MILLIMETER.
TO THE LOWEST POINT OF THE PACKAGE BODY.
8
REFERENCE DOCUMENT : JEDEC MS–026 , BFB
Figure 39 LQFP144 package
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77
CME-M5 Family Data Sheet
7.3.2
TQFP100 Thin Quad Flat-Pack Package Specifications
D 1
θ2 (4x)
D1 2
PIN 1
IDENTI
FIER
1
θ1
4
10
0
R1
76
R2
75
B
GAGE PLANE
.25
E1 E
2
1
θ
B
S
L
…
51
25
L1
θ3
(4x)
SECTION A-A
26
5
0
b 5
3
SEE DETAIL A-A
A A2
A16
e
b
c
SEATING PLANE
C
5
WITH PLATING
cccC
c1
5
b1 5
BASE METAL
SECTION B-B
Symbol
A
A1
A2
b
b1
c
c1
D
D1
E
E1
e
L
L1
R
R1
S
θ
θ1
θ2
θ3
ccc
Dimension in mm
Min Nom Max
1.20
0.05
0.15
0.95 1.00 1.05
0.17 0.22 0.27
0.17 0.20 0.23
0.09
0.20
0.09
16.00
14.00
16.00
14.00
0.16
BSC
BSC
BSC
BSC
0.50 BSC
0.45 0.60 0.75
0.15 REF
0.08
0.08
0.20
0.20
0°
3.5°
7°
0°
11° 12°
13°
11° 12°
13°
0.08
1
TO BE DETERMINED AT SEATING PLANE C
DIMENSION D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION
D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSION
2
INCLUDING MOLD MISMATCH.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION
3
DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR
THEFOOT.
4
EXACT SHAPE OF EACH CORNER IS OPTIONAL.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD
5
BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP.
6
7
A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE
CONTROLLING DIMENSION : MILLIMETER.
TO THE LOWEST POINT OF THE PACKAGE BODY.
8
REFERENCE DOCUMENT : JEDEC MS–026 , BFB
9
SPECIAL CHARACTERISTICS C CLASS : ccc
Figure 40 TQFP100 package
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CME-M5 Family Data Sheet
7.3.3
FBGA256-Pin FineLine Ball-Grid Array (FBGA) – THIN – Wire Bond
Figure 41 FBGA256 package


Controlling dimension is in millimeters.
Pin A1 may be indicated by an ID dot, or a special feature, in its proximity on package
surface.
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CME-M5 Family Data Sheet
7.3.4
QFN68 Package Specifications
Figure 42 QFN68 package
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CME-M5 Family Data Sheet
8 Developer Kits
Capital Microelectronics developer kits can achieve 2 designs for CME-M5 family: FPGA design and
embedded software design.
Capital Microelectronics Primace Integrated Design Environment (IDE) supports all CME’s chips, and
can implement synthesis, mapper, placement, routing, bitgen, simulation etc, and support 3rd-party EDA
tools: Modelsim as well.
AGDI is developed by Keil (Keil is a part of ARM), as a general purposed debugger interface to Keil-C
IDE, with which designers can compile and debug 8051 firmware online. The CME-M5 family device has
on-chip debug (OCDS) capability, which can help the user debug 8051 program easily. For more
information, please refer to CME 8051 Debugger User Manual.
If you want to program, compile, debug 8051, or perform other 8051 related operations, please purchase
Keil-C software tool. For more information, please refer to http://www.keil.com/c51 .
Currently, the CME-M5 family device does not support other 3rd-party development environment. If you
have any questions or suggestions, please contact us at: support@capital-micro.com .
OCDS debugging interface of MSS share the same JTAG interface with FPGA.
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CME-M5 Family Data Sheet
9 Ordering Information
All part numbers have the following conventions:
Table 54 Part number conventions
Vendor
Product
Series
Device
Type
LUT
Density
CME-
M5
C
06
NVM
Density
Package
Type
Temperature
Range
Speed
Grade
N3
L144
C
7
Product Series
M5
JINSHAN family
Device Type
P
R
C
FPGA
FPGA + SRAM
FPGA + SRAM + MCU
LUT Density
06
03
01
6K LUTs
3K LUTs
1K LUTs
Configuration NVM (SPI-flash) Option
N0
Without internal SPI-flash
N1
With 1Mb internal SPI-flash
N2
With 2Mb internal SPI-flash
N3
With 4Mb internal SPI-flash
N4
With 8Mb internal SPI-flash
Package Type: <type><#>
T
L
Q
F
#
Thin Quad Flat Pack (TQFP)
Low profile quad flat package (LQFP)
Plastic Quad Flat Pack (QFN)
Fineline BGA
Pin number (208 for 208pin, 100 for 100pin…)
Temperature Range
C
I
Commercial (0℃ to 85℃)
Industrial (-40℃ to 125℃)
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CME-M5 Family Data Sheet
Speed Grade
#
Speed (7 for speed 7, 6 for speed 6, …)
Example:
CME-M5C06N3L144C7
Device Type
NVM Density
N0:Without SPI-flash
N1: With 1Mb SPI-flash
N2: With 2Mb SPI-flash
N3: With 4Mb SPI-flash
N4: With 8Mb SPI-flash
P: FPGA
R: FPGA + SRAM
C: FPGA + SRAM + MCU
Vendor
CME
CME- M5
Product Series
C
LUT Density
M5: JINSHAN family 06:6K LUTs
03:3K LUTs
01:1K LUTs
06
N3
L144
C
7
Package Type
Speed Grade
T:TQFP
Temperature Range
7: speed 7
L:LQFP
6: speed 6
C: Commercial (0℃~85℃)
Q:QFN
I: Industrial (-40℃~+125℃)
F:BGA
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CME-M5 Family Data Sheet
10 Legends
Abbreviation
Full Name
AES
Advanced Encryption Standard
ALU
Arithmetic-Logic Unit
AS
Active Serial
CAP
Configurable Application Platform on Chip
CCU
Compare Capture Unit
CMS
Control Mux Switch
CPU
Control Processor Unit
DPRAM
Dual Port RAM
DC
Direct Current
DSP
Digital Signal Processor
EMB
Embedded Memory Block
IAP
In Application Programming
I2C
Inter-IC – a serial interface designed by Philips Semiconductors
ISC
In System Configuration
ISP
In System Programming
ISR
Interrupt Service Routine Unit
LE
Logic Element
LP
Logic Parcel
LSB
Least Significant Bit
MAC
Multiply Accumulate Counter
MDU
Multiplication-Division Unit
MOVC
Move Program Memory
MOVX
Move External Memory
MSB
Most Significant Bit
MSS
Microcontroller Subsystem
OCDS
On-Chip Debug Support
OCI
On-Chip Instrumentations
PLB
Programmable Logic Block
PMU
Power Management Unit
PS
Passive Serial
RTC
Real Time Clock
SFR
Special Function Register
SPI
Serial Peripheral Interface
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