CDX-727
SERVICE MANUAL
US Model
Canadian Model
AEP Model
UK Model
E Model
Model Name Using Similar Mechanism
CDX-715
CD Drive Mechanism Type
MG-250C-137
Optical Pick-up Name
KSS-521A/J2N
SPECIFICATIONS
COMPACT DISC CHANGER
MICROFILM
CDX-727
7-6.
SCHEMATIC DIAGRAM – RF/SW Boards –
• See page 41 for Waveforms. • See page 43 for IC Block Diagrams.
(Page 35)
The components identified by mark ! or dotted
line with mark ! are critical for safety.
Replace only with part number specified.
– 29 –
– 30 –
Les composants identifiés par une marque ! sont
critiques pour la sécurité. Ne les remplacer que
par une piéce portant le numéro spécifié.
CDX-727
7-9. SCHEMATIC DIAGRAM – MAIN Board (1/2) –
• See page 41 for Waveforms. • See page 44 for IC Block Diagrams.
(Page 30)
– 35 –
– 36 –
CDX-727
7-10.
SCHEMATIC DIAGRAM – MAIN Board (2/2) –
• See page 42 for Waveforms. • See page 45 for IC Block Diagrams.
(Page 40)
– 37 –
– 38 –
7-11.
PRINTED WIRING BOARD – JACK Board –
(Page 31)
– 39 –
7-12.
SCHEMATIC DIAGRAM – JACK Board –
(Page 38)
– 40 –
• Waveforms
– RF Board –
– MAIN Board (1/2) –
1 IC101 @¶ (MDP)
1 IC11 #£ (RF O)
500 mV/DIV, 500 ns/DIV
6 IC101 ^™ (RFCK)
2.5 Vp-p
6.4 Vp-p
1.4 Vp-p
13.6 µs
7.6 µs
2 IC11 2 (FEI)
50 mV/DIV, 1 µs/DIV
2 IC101 #§ (V16M)
7 IC101 &º (C4M)
6.5 Vp-p
6.3 Vp-p
Approx.
110 mVp-p
119 ns
119 ns
3 IC11 $¶ (TEI)
200 mV/DIV, 500 µs/DIV
3 IC101 $ª (WDCK)
8 IC101 &¢ (WFCK)
6.3 Vp-p
5.8 Vp-p
Approx.
280 mVp-p
11.4 µs
136 µs
4 IC101 %º (LRCK)
9 IC101 *ª (XTAI)
6.2 Vp-p
22.7 µs
6.2 Vp-p
59.4 ns
5 IC101 %¢ (BCKO)
0 IC201 #¡ (EXTAL)
6.5 Vp-p
474 ns
– 41 –
4.9 Vp-p
124 ns
– MAIN Board (2/2) –
!§ IC401 9 (BCKI)
!¡ IC501 @ª (EXTAL)
6.5 Vp-p
3.1 Vp-p
5.6 Vp-p
22.7 µs
474 ns
100 ns
!™ IC501 &¶ (WRCK)
!¶ IC401 !™ (LRCI)
136 µs
@™ IC601 !£ (MCK)
22.7 µs
!£ IC401 3 (WFCK)
59.4 ns
!• IC401 !£ (WDCI)
@£ IC601 !∞ (XI)
6.9 Vp-p
5.8 Vp-p
11.3 µs
136 µs
!¢ IC401 5 (C4M)
6.3 Vp-p
@¢ IC601 @£ (BCK)
6.2 Vp-p
6.4 Vp-p
474 ns
59.4 ns
!∞ IC401 7 (RFCK)
2.5 Vp-p
59.4 ns
!ª IC401 !§ (XTAI)
119 ns
5.8 Vp-p
6.3 Vp-p
5.8 Vp-p
@º IC401 !¶ (BCK)
@∞ IC601 @¢ (LRCK)
6.2 Vp-p
6.4 Vp-p
136 µs
@¡ IC401 !ª (LRCK)
474 ns
– 42 –
5.6 Vp-p
22.7 µs
• IC Block Diagrams
– RF Board –
RF O
35
34
33 32
PD 2
I-V AMP
PD 1
I-V AMP
PD
AMP
LD
AMP
VCC
31 30
29
28
27
CP
FOK
RF M
36
CC2
RFTC
37
CC1
LD
38
CB
PD
39
RF I
PD1
CXA1992BR
PD2
RF SUMMING
AMP
FOCUS OK
COMPARATOR
LASER
POWER
CONTROL
DEFECT
AMP
TEI 47
ATSC
WINDOW
COMPARATOR
TZC 49
TZC
COMPARATOR
MIRR
PS1 – PS4
DFCTO
E-F BALANCE
WINDOW
COMPARATOR
TG1 – TG2
ATSC
IIL
↓
TTL
26 SENS2
25 SENS1
24 C. OUT
TTL
↓
IIL
23
22
21
20
19
IIC DATA REGISTER, INPUT SHIFT REGISTER,
ADDRESS DECODER, SENSE SELECTOR,
OUTPUT DECODER
FS1 – FS4
BALL
ATSC 48
LPC
LDON
FOL
VEE
LPFI 46
FOH
TGL
BALH
IFB1 – IFB6
BAL1 – BAL4
TOG1 – TOG4
BAL1 – BAL4
EI 43
VEE 44
TEO 45
TGH
TRACKING GAIN
WINDOW
COMPARATOR
TGFL
VCC
18 VCC
VCC
ISET
TM6
17 ISET
16 SL O
15 SL M
TM1
DFCT
TRACKING PHASE
COMPENSATION
TG1
+
–
TDFCT 50
TM5
VCC
14 SL P
TM2
VEE
CENTER
VOLTAGE
GENERATOR
VC 51
FZC
COMPARATOR
FZC 52
VCC
TM7
TM4
VCC
VEE
FOCUS PHASE
COMPENSATION
FS1
CHARGE UP
+
–
FS2
FS4
DFCT
XRST
DATA
XLT
CLK
LOCK
FZC
E 42
E I-V
AMP
TZC
F I-V
AMP
TOG1 – TOG4
F 41
FOCUS BIAS
WINDOW
COMPARATOR
FOCUS ERROR
AMP
LPCL
PEAK/BOTTOM
HOLD
VEE
IIL
↓
TTL
CC1
FE
40
BIAS
MIRR
COMPARATOR
DFCT1
PEAK/BOTTOM
HOLD
TM1 – TM7
IFB1 – IFB6
TGFL
IC11
FSET
TM3
TG2
– 43 –
10
11
12
13
TA M
TA O
VEE
9
FSET
8
TG2
FGD
7
TGU
FDFCT
6
SRCH
FEI
5
FE M
4
FLB
3
FE O
2
FEO
VEE
1
IC52
BA6287F
OUT1 1
8 GND
VM 2
7 OUT2
DRIVER
DRIVER
TSD
VCC 3
6 VREF
CONTROL LOGIC
POWER
SAVE
FIN 4
5 RIN
– MAIN Board –
WFCK
TES5
EMPH
DOUT
C4M
FSTT
XTSL
MNT0
MNT1
MNT3
XROF
C2PO
RFCK
GFS
XPCK
XUGF
GTOP
VDD
VSS
TES4
BCK
TES3
PCMD
TES9
CXD2530Q
80 79 78 77 76 75 74 73 72
71 70 69 68
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
TES6
VDD
VSS
EXCK
SBSO
SCOR
50 LRCK
49 WDCK
ERROR
CORRECTOR
EFM
DEMODULATOR
16K RAM
D/A
INTERFACE
DIGITAL OUT
SUB CODE
PROCESSOR
ASYMMETRY
CORRECTOR
DIGITAL
PLL
OSC
CLOCK
GENERATOR
TIMING
LOGIC
SERVO
AUTO
SEQUENCER
CPU
INTERFACE
DIGITAL CLV
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
XLTO
CLKO
SPOA
SPOB
SPOC
SPOD
XLON
FOK
VDD
VSS
MON
MDP
MDS
LOCK
PWMI
1 2 3 4 5 6
SQCK
SQSO
SENS
DATA
XLAT
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VDD
VSS
LMUT
RMUT
TES2
CKOUT
NC
VSS
VDD
NC
TES7
NC
VSS
XVDD
XTAI
XTAO
XVSS
VSS
NC
TES8
NC
VDD
VSS
NC
NC
XRST
CLOK
SEIN
CNIN
DATO
IC101
– 44 –
48
47
46
45
44
43
42
41
40
ASYE
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
39
38
37
36
FILO
PCO
VCTL
V16M
35
34
33
32
31
VCKI
VPCO1
VPCO2
TES1
TES0
IC202
AT24C16N-10SI-TR
IC301
BA6287F
OUT1 1
START
STOP
LOGIC
SERIAL EN
CONTROL
LOGIC
H.V. PUMP/TIMING
COMP
R/W
DATA RECOVERY
DATA WORD
ADDR/COUNTER
7 OUT2
DRIVER
7 TST
DRIVER
TSD
LOAD INC
X DEC
A0 1
A1 2
A2 3
VM 2
8 VCC
LOAD
DEVICE
ADDRESS
COMPARATOR
8 GND
6 SDL
E2PROM
VCC 3
5 SDA
6 VREF
CONTROL LOGIC
GND 4
Y DEC
SERIAL MUX
POWER
SAVE
DOUT/ACK
LOGIC
DIN
FIN 4
5 RIN
DOUT
1
2
3
4
5
6
7
BUS ON OUT
BUS ON IN
GND
BUS CLK
VREF
BUS DATA
BUS RESET
RESET
SWITCH
XWIH
AM4
AM3
AM2
AM1
AM0
VDD
XQOK
51 50 49 48 47 46 45 44 43
42
41
40 39 38 37 36 35 34 33
52
53
54
55
56
57
58
59
CPU I/F
32
31
30
29
28
27
26
25
24
23
22
ADDRESS MONITOR
WRITE
BASE
COUNTER
DRAM
I/F
VWA
READ
BASE
COUNTER
D3
D0
D1
XWE
XRAS
A9
VDD
A0
A1
A2
A3
SELECTOR
TIMING
GEN.
GSCR 60
DATA
LINKING
CONTROL
SCOR 61
DSP
I/F
DAC
I/F
NC 62
NC 63
NC 64
1 2 3 4 5 6 7 8
9 10 11 12 13 14 15
16
17 18 19
BCK
DATA
LRCK
8
A4
A5
A6
A7
A8
XOE
XCAS
D2
9
XTAI
10
OSCE
RESET
11
VSS
DATA IN
12
BCKI
VSS
DATI
LRCI
WDCI
TEST
XTAO
DATA OUT
13
XEMP
SDTO
XSOE
SCK
SDTI
XLT
XRDE
XWRE
SPSL
CLK OUT
14
CXD2522Q
GRST
XRST
WFCK
DIN
C4M
XROI
RFCK
GTOP
LINK OFF
IC401
BUS ON
BA8272F-E2
VCC
IC302
– 45 –
21 C176
DIGITAL
OUT
20 DOUT
DATA INPUT
BUFFER
CLOCK
GENERATOR
1
5
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
IC601
KM62256DLG-7LT
28 VCC
TC9464FN-EL
24 23 22
21
20
19
18
17
16
15
14 13
LRCK
IC502
REFRESH
ADDRESS
COUNTER
GNDX
A9
A0
A1
A2
A3
VCC
PREADDRESS
BUFFER DECODER
MODE
CONTROL
BOARD
BIAS
GENERATOR
XI
4
ROW
DECODER
XO
RAS
4M BIT
MEMORY
CELL
MCK
COLUMN SENSE AMP
DECODER I/O GATE
23 CAS
22 OE
VDX
CLOCK
GENERATOR
2
DATA OUTPUT
BUFFER
(BS)
LA
WRITE
CLOCK
GENERATOR
(EMP)
SH
3
(SM)
ATT
WE
26 VSS
25 DQ4
24 DQ3
HS
1
2
DATA
DQ1
DQ2
MSM514400D-60TS-K
BCK
IC402
27 WE
DIGITAL FILTER CIRCUIT
ATTENUATOR OPERATIONAL CIRCUIT
22 OE
21 A10
I/O8
I/O7
I/O6
I/O5
I/O4
GND 14
– 46 –
OUTPUT
CIRCUIT
ANALOG
FILTER
ANALOG
FILTER
2
3 4
5
6
7
8
9
10 11 12
ZD
1
VDA
19
18
17
16
15
OUTPUT
CIRCUIT
LO
I/O BUFFER
TEST
CIRCUIT
20 CE
GNDA
BUFFER
I/O GATE
COLUMN
DECODER
VR
LEVEL
SHIFT
BUFFER
DEEMPHASIS FILTER CIRCUIT
D-∆ MODULATION CIRCUIT
GNDA
LEVEL
SHIFT
TIMING
GENERATOR
GNDD
MEMORY
MATRIX
512X512
RO
I/O1 11
I/O2 12
I/O3 13
ROW
DECODER
VDA
6
7
8
9
10
BUFFER
OSC
P/S
A4
A3
A2
A1
A0
LEVEL
SHIFT
MICROCOMPUTER
INTERFACE
CIRCUIT
INTERFACE
CIRCUIT
T1
1
2
3
4
5
A13
A8
A9
A11
VDD
A14
A12
A7
A6
A5
26
25
24
23
7-13.
IC PIN FUNCTION DESCRIPTION
• MAIN BOARD IC201 CXP84332-210Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Function
1 to 3
—
O
Not used (open)
4
CH.F
O
Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)
“L” active *1
5
CH.R
O
Motor drive signal (save direction) output to the chucking motor drive (IC52)
“L” active *1
6
LOAD2
I
Chucking end detect switch (SW11) input terminal
“L”: When completion of the disc chucking operation
7
LOAD1
I
Save end detect switch (SW12) input terminal
“L”: When completion of the disc chucking operation
8
SENS2
I
Internal status signal (sense signal) input from the CXA1992BR (IC11)
9
LIM.SW
I
Sled limit in detect switch (SW1) input terminal
“L”: When the optical pick-up is inner position
10
EE.INIT
I
Initialize signal input for the EEPROM (IC202) “H”: format Fixed at “L” in this set
11
EE.CLK
O
Serial data transfer clock signal output to the EEPROM (IC202)
12
EE.DATA
I/O
Two-way data bus with the EEPROM (IC202)
13 to 19
—
O
Not used (open)
20
SINGLE
I
Setting terminal for the single disc/multiple discs mode
“L”: single mode, “H”: multiple discs mode (fixed at “H”)
21
XRST
O
System reset signal output to the CXA1992BR (IC11), CXD2530Q (IC101) and CXD2522Q
(IC401) “L”: reset
22
FOK
I
Focus OK signal input from the CXA1992BR (IC11) “L”: NG, “H”: OK
23
SENS
I
Internal status signal (sense signal) input from the CXD2530Q (IC101)
24
GFS
I
Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK
25
GRSRT
O
Reset signal output to the CXD2522Q (IC401) “L”: reset
26
XQOK
O
Subcode Q OK pulse signal output to the CXD2522Q (IC401) “L” active
27
SDTI
I
ESP status signal input from the CXD2522Q (IC401)
28
XSOE
O
ESP status read enable signal output to the CXD2522Q (IC401) “L” active
29
ESPXLT
O
ESP latch pulse signal output to the CXD2522Q (IC401) “L” active
30
RST
I
System reset signal input from the SONY bus interface (IC302) and reset signal generator
(IC304) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
31
EXTAL
I
Main system clock input terminal (8 MHz)
32
XTAL
O
Main system clock output terminal (8 MHz)
33
VSS
—
Ground terminal
34
TX
O
Sub system clock output terminal Not used (open)
35
TEX
I
Sub system clock input terminal Not used (fixed at “L”)
36
AVSS
—
37
AVREF
I
Reference voltage (+5V) input terminal (for A/D converter)
38
MCK
I
Input of signal for the fine adjustment (linear position sensor adjustment; RV201) of elevator
position (A/D input)
39
EHS
I
Elevator height position detect input from the RV202 (elevator height sensor) (A/D input)
40
MODEL
I
Setting terminal for the destination (fixed at “H” in this set)
41
XRDE
O
D-RAM read enable signal output to the CXD2522Q (IC401) “L” active
42
XWRE
O
D-RAM write enable signal output to the CXD2522Q (IC401) “L” active
43
A.MUTE
O
Audio line muting on/off control signal output terminal “H”: muting on
44
EMP
O
Emphasis mode output to the D/A converter (IC601) “H”: emphasis on
45
ML
O
Fast speed dubbing control signal output to the D/A converter (IC601) “L”: fast speed
46
GRSCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2522Q (IC401)
Ground terminal (for A/D converter)
– 47 –
Pin No.
Pin Name
I/O
47
D/A.RESET
O
Reset signal output terminal “L”: reset Not used (open)
Function
48
SCK
I
Serial data transfer clock signal input from the SONY bus interface (IC302)
49
SI
I
Serial data input from the SONY bus interface (IC302)
50
SO
O
Serial data output to the SONY bus interface (IC302)
51
SCLK
O
Subcode Q data reading clock signal output to the CXD2530Q (IC101)
52
SUBQ
I
Subcode Q data input from the CXD2530Q (IC101)
53
—
O
Not used (open)
54
C.OUT
I
Track number count signal input from the CXA1992BR (IC11)
55
BUS.ON
I
Bus on/off control signal input from the SONY bus interface (IC302) “H”: bus on
56
—
I
Not used (open)
57
MGLK
I
Magazine eject operation completion detect switch (SW201) input “L”: eject completed
58
ELV.F
O
Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)
“L” active *2
59
—
O
Not used (open)
60
MAG.SW
I
Magazine in/out detect switch (SW202) input “L”: magazine detected
61
BU.CHK
I
Battery detection signal input terminal “H”: battery on
62
W.UP
I
Bus on or eject switch (SW301) input terminal “H”: bus on or eject switch pushing
63
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
64
EJECT
I
Eject switch (SW301) input terminal “H” active
65
CD.CLK
O
Serial data transfer clock signal output to the CXD2530Q (IC101) and CXD2522Q (IC401)
66
CD.XLT
O
Serial data latch pulse signal output to the CXD2530Q (IC101)
67
CD.DATA
O
Serial data output to the CXD2530Q (IC101) and CXD2522Q (IC401)
68
CD.ON
O
D/A converter and servo section power supply on/off control signal output “H”: power on
69
ELV.ON
O
Mechanism deck section power supply on/off control signal output “H”: power on
70
ELV.R
O
Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)
“L” active *2
71
—
O
Not used (open)
72
VDD
—
Power supply terminal (+5V)
73
NC (VDD)
—
74
BUSY
I
Busy monitor input from the CD text decoder (IC501) “L”: busy status
75
RESET
O
Reset signal output to the CD text decoder (IC501) “L”: reset
Connected to the power supply (+5V)
76
REQ
I
Data request signal input from the CD text decoder (IC501) “L” active
77
CCCLK
O
Command clock signal output to the CD text decoder (IC501)
78
CSO
O
Command data output to the CD text decoder (IC501)
79
CSI
I
Command data input from the CD text decoder (IC501)
80
—
I
Not used (open)
*1 chucking motor (M103) control
STOP
LOAD
CHUCKING
SAVE
BRAKE
CH.F (pin 4)
“H”
“L”
“H”
“L”
CH.R (pin 5)
“H”
“H”
“L”
“L”
Mode
Terminal
*2 elevator motor (M104) control
Mode
Terminal
STOP
ELEVATOR ELEVATOR
UP
DOWN
BRAKE
ELV.F (pin %•)
“H”
“L”
“H”
“L”
ELV.R (pin &º)
“H”
“H”
“L”
“L”
– 48 –
• MAIN BOARD IC501 CXP83413-049Q (CD TEXT DECODER)
Pin No.
Pin Name
I/O
Function
1, 2
NC
O
Not used (open)
3
NC
I
Not used (fixed at “L”)
4
REQ
O
Request signal output to the system controller (IC201) “L” active
5
CCLK
I
Serial data transfer clock signal input from the system controller (IC201)
6
CSI
I
Serial data input from the system controller (IC201)
7
CSO
O
Serial data output to the system controller (IC201)
8
SCLK
O
Clock signal output for subcode data reading to the CXD2530Q (IC101)
9
SSI
I
Subcode data input from the CXD2530Q (IC101)
10
NC
O
Not used (open)
11 to 18
ADD0 to ADD7
O
Address signal output to the S-RAM (IC502)
19
NC
I
Not used (fixed at “L”)
20 to 27 DATA0 to DATA7
I/O
Two-way data bus with the S-RAM (IC502)
28
RST
I
System reset signal input from the system controller (IC201), SONY bus interface (IC302) and
reset signal generator (IC304) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
29
EXTAL
I
System clock input terminal (10 MHz)
30
XTAL
O
System clock output terminal (10 MHz)
31
VSS
—
Ground terminal
32 to 55
NC
O
Not used (open)
56
BUSY
O
Busy signal output to the system controller (IC201) “L”: busy status
57 to 61
NC
O
Not used (open)
62
CE
O
Chip enable signal output to the S-RAM (IC502) “L” active
63
WE
O
Data write enable signal output to the S-RAM (IC502) “L” active
64 to 69
ADD8 to ADD13
O
Address signal output to the S-RAM (IC502)
70
VDD
—
Power supply terminal (+5V)
71
NC
O
Not used (open)
72
NC
I
Not used (fixed at “L”)
73
NC
I
Not used (fixed at “H”)
74
ADD14
O
Address signal output to the S-RAM (IC502)
75
NC
O
Not used (open)
76
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)
77
WFCK
I
Write frame clock (7.35 kHz) signal input from the CXD2530Q (IC101)
78
BUCK
I
Backup power supply detection signal input terminal (used also to reset standby)
79, 80
NC
I
Not used (fixed at “L”)
– 49 –