Lecture 8 Overview
• Differential Amplifier
– Applications
– Large Signal Input-Output Characteristic
– Preview Symmetry Analysis: "Half Circuit”
– Active (Mirror) Load
– Text: Sec. 3.8 pp. 142-146
ECG: Electrocardiogram
• Display electrical activity
of heart muscle
• Shape of waveform
related to health of heart
ECG: Electrocardiogram
•
•
•
•
Shape of waveform related to health of heart
Amplitude: mV range
Problem: Can’t contact VH directly
Access only to voltage waveform on surface:
Voltage waveform on surface
• 60Hz inteference: body acts as 60 Hz antenna!
• How to recover signal?
Frequency domain
Signal of interest: information 1 Hz - 100 Hz
Can't filter
Frequency domain
Signal of interest: information 1 Hz - 100 Hz
Can't filter
Frequency domain
Signal of interest: information 1 Hz - 100 Hz
Can't filter
Alternative approach
• VS1 = 60Hz
+ Desired Signal
• Second electrode
far from heart
• VS2 = 60Hz
Subtract Waveforms
VS1 = 60Hz + Desired Signal
VS2 = 60Hz
VS1 - VS2= Desired Signal (60Hz subtracted out)
Differential Amplifier Function
•
•
•
•
•
Desired signal is small (mV range)
Required function: Vout = AV(diff)[VS1 - VS2]
AV(diff): "Differential Gain"
Difference amplified
Common mode rejected (subtracted out)
Op-Amp
• Differential input
• Single-ended
(ground referenced) output
• Function: Vout = A0[V+ - V-]
• A0: "Open Loop Gain"
Circuit: Differential Amplifier (Resistive Load)
• "Source-Coupled Pair"
Analysis strategy
• Large-signal
– DC Bias
– Input-output
characteristic
• Small-signal gain
VDD
DC bias: Current
KCL at source: IS1 + IS2 = IBIAS
DC bias: Current
• KCL at source:
IS1 + IS2 = IBIAS
• For MOSFET:
Gate IG = 0 (oxide)
Substrate IB = 0
(reverse bias junction)
Source,drain currents equal: IS = ID
KCL Result
• ID1 + ID2 = IBIAS
• MOSFET pair
"splits" bias current
• Total must equal IBIAS
• Split determined
by VGS1, VGS2
• Current source bias: VS will be whatever
necessary to make correct VGS values
VGS values
• KVL path
V+ - VGS1 + VGS2 = VV+ - V- = VGS1 - VGS2
1
424
3 14243
DIFF
INPUT
DVGS
Build up V-I characteristic
• Focus on ID1, ID2
• Assume active region
(always check Vout, VGD)
Start: V+ = V-
• V+ - V- = 0 fi VGS1 = VGS2
Start: V+ = V• V+ - V- = 0 fi
VGS1 = VGS2
• M1, M2 active
• Identical devices
fi Identical conditions
VGS1 = VGS2 fi
Identical behavior fi ID1 = ID2
• KCL: ID1 + ID2 = IBIAS
ID1 = ID2 = IBIAS / 2
Differential pair "balanced"
Build up V-I plot: V+ = V-
ID1 = ID2 = IBIAS / 2
Common mode rejection
• Terminology: "Common mode"
Same voltage applied to both inputs
• Same VG fi Same VGS fi Same ID
• Output split of IBIAS unchanged:
Common mode rejected
Current split depends only on difference
Large differential input: V+ >> V-
Increase V+ >> V-
Large differential input: V+ >> V• Increase V+ >> V• V+ - V- = VGS1 - VGS2
• VGS1 increases,
VGS2 decreases
• Eventually VGS2 < Vtn
fi ID2 = 0 (M2 cutoff)
M1 gets all the current: ID1 = IBIAS
Build up V-I plot: V+ >> V-
ID1 = IBIAS
ID2 = 0
Large differential input: V- >> V+
Increase V- >> V+
Large differential input: V- >> V+
• Increase V- >> V+
• V+ - V- = VGS1 - VGS2
• VGS2 increases,
VGS1 decreases
• Eventually VGS1 < Vtn
fi ID1 = 0 (M1 cutoff)
M1 gets all the current: ID2 = IBIAS
Build up V-I plot: V- >> V+
ID1 = 0
ID2 = IBIAS
Finish: "Connect the dots"
• General shape for any differential pair:
MOSFET, BJT, JFET, ...
• Specifics depend on bias, technology, etc.
"Current Steering"
• Differential input fi ∆VGS
fi controls current "split"
• Common mode input
fi IBIAS unchanged (current source)
Voltage Output
KVL paths:
VO1 = VDD - ID1RD
VO2 = VDD - ID2RD
Voltage Output
VO1 = VDD - ID1RD
VO2 = VDD - ID2RD
Differential Voltage Output: VOD = VO1 - VO2
Differential Voltage Output
• Large signal:
Limits ±IBIASRD
Differential Voltage Output
• Slope of plot at operating point (origin):
Small signal differential gain av(diff)
Differential Gain
• Need to improve fi need to be quantitative
• Analytic tool:
Bartlett's Bisection Theorem
• Applies for symmetrical circuits
• Simplifies analysis:
Allows splitting of circuit into separate halves
Symmetry Analysis: Preview Result
• Each half "looks like" common source amplifier
• small signal differential gain
av(diff)=-gm1RD
• gm1 is transconductance of M1 (or M2: same!)
Bartlett's Bisection Theorem
• Two completely symmetrical circuits
a, b, c are connected points of symmetry
Common mode: Symmetric excitation
• If V1 = V2 = VCM (same input to both circuits)
• No current at connected points of symmetry
• Imagine mirror reversal: Ia = -Ia fi Ia = 0
Common mode: Symmetric excitation
• We can open all leads between connected points
of symmetry without affecting circuit operation
• Applies for any circuit (linear or nonlinear)
Differential mode: Antisymmetric excitation
If V1 = -V2 : “See-Saw”:
Fixed voltage at connected points of symmetry
Differential mode: Antisymmetric excitation
• All leads between connected points of
symmetry can be tied to small signal ground
without affecting circuit operation
• Requires linearity
Bartlett's Bisection Theorem
• Applies to symmetric circuits
• Common mode (symmetric) excitation
– Open connected points of symmetry
• Differential (antisymmetric) excitation
– Connected points of symmetry tied to signal
ground
– Requires linearity
Any two signals!
Can be expressed as sum of
common mode, differential mode:
Any two signals!
• Define:
• Can verify:
V1 + V2
VCM =
2
Vdm = V1 - V2
Vdm
V1 = VCM +
2
V
V 2 = VCM - dm
2
Half circuit analysis technique
1) Represent inputs in terms of Vdm, Vcm
2) Redraw circuit to emphasize symmetry
3) Use superposition to find output:
– DC bias: V1, V2 = 0 (all inputs suppressed)
– CM Response: keep vCM , set vdm = 0
– DM response: keep vdm , set vCM = 0
– Add results for total output
• Split circuit using bisection theorem:
– Analyze each half separately
1) Represent inputs in terms of Vdm, Vcm
2) Redraw to show symmetry
• IBIAS equivalent: two IBIAS/2 in parallel
DC bias: V1, V2 = 0 (all signal inputs suppressed)
I
VO1(DC ) = VDD - BIAS RD
2
I
VO2(DC) = VDD - BIAS RD
2
• Symmetric excitation:
open connected points of symmetry
Common Mode Response: vdm = 0
• Open connected points of symmetry
Note "supernode": id = 0
Vo1(cm ) = -id RD = 0
Vo2 (cm) = 0
Differential mode response: vcm = 0
• Connected points of symmetry to signal ground
Small signal model of half-circuit
vdm
Vo1(dm ) = -g m RD
123
2
{
OUTPUT
INPUT
-v dm
Vo2 (dm) = -g m RD
1
424
3
23
12
OUTPUT
• Common source amplifier!
• Note: gm1 = gm2 = gm
INPUT
Summary: Output “parts”
• DC bias
I BIAS
VO1(DC ) = VDD RD
2
• Common
mode
Vo1(cm) = 0
• Differential
mode
-gm RD
Vo1(dm ) =
v dm
2
IBIAS
VO2(DC) = VDD RD
2
Vo2(cm) = 0
gm RD
Vo 2(dm) =
vdm
2
Summary: Total output sum of components
I BIAS
-gm RD
VO1 = VDD RD + {0 +
vdm
2243
14422443 CM 14
DCBIAS
DIFFERENTIAL
MODE
I BIAS
gm RD
VO2 = VDD RD + {0 +
vdm
2243
14422443 CM
14
DCBIAS
DIFFERENTIAL
MODE
Differential gain
DIFFERENTIAL
OUTPUT
644
47444
8
Vo1(dm) - Vo2(dm)
av(diff ) =
vdm
{
DIFFERENTIAL
INPUT
v
v
-g m RD dm - gm RD dm
2
2
av(diff ) =
v dm
av(diff ) = -g m RD
• Same as common source amplfier
• Still low for resistive load!
Lab Exercise
• IBIAS = 250µA, RD = 20kΩ
• DCbias
I
250mA
VO1(DC ) = VDD - BIAS RD = +5V 20kW = +2.5V
2
2
• Small signal: gm ≈ 400µA/V
gm1RD ≈ (400µA/V)(20kΩ) = 8
Need to increase for op-amp!
Drain Currents
Mirror load
Mirror load
ID1 - I D2 = gm vdm
Mirror load
• Gain increased
• Similar to result
for common
source, active load
Lecture 8 Summary
• Differential Amplifier
– "Build up" Large Signal Input-Output
Characteristic
– Key: M1, M2 identical
– Differential Input controls ”split" of IBIAS
– Common mode input rejected
• Symmetry Analysis: "Half Circuit"
– Bartlett's Bisection Theorem
• Mirror Load
– Increased gain (active load)
– Single ended output without 1/2 factor loss
(mirror)