1
π
T.T.N. Tran, C.C. Boon , M.A. Do, and K.S. Yeo

Abstract — A novel CMOS low noise amplifier (LNA) with a new input matching topology is proposed. The input matching design is based on the capacitive feedback in conjunction with a
π -match network. Only one inductor is used for the input frequency to 50 Ω . The input impedance of this LNA is derived to be:
1
(1) matching. The π -match network introduces an additional degree of design freedom and allows the LNA to achieve higher gain.
Designing for the 2.4 GHz ISM band, the proposed LNA achieves a measured gain of 21.7 dB with an
S
11
of -12dB while consuming
-12dBm.
where is the operating frequency, only 0.6 mW. The noise figure (NF) is 5.0 dB and the IIP3 is
C
1
and are the parasitic gate-source capacitance and the transconductance of transistor
M
1 respectively.
Index Terms
— LNA, low power, high gain, front-end
I.
I NTRODUCTION
T
HIS paper presents the design of an LNA for the IEEE
802.15.4 standard. In this standard, the LNA NF is not a critical performance parameter [1]. Therefore, the NF requirement can be relaxed to allow optimization on other design parameters such as gain, power consumption and chip area. Popular LNA topologies are the inductive sourcedegeneration common-source LNA (L-CSLNA), the commongate LNA (CGLNA), and the resistive feedback LNA
(RFLNA). The L-CSLNA is the most commonly used topology for narrow-band applications due to its ease of input matching, high gain and low noise. However, at least two inductors are needed for input matching which results in a large chip area required. This paper proposed a novel LNA scheme which reduced the number of inductor needed for input matching when compared to the L-CSLNA. The input matching is realized by the capacitive feedback scheme and π match network. Higher gain and more degree of design freedom are achieved with the use of the π -match network.
The LNA was designed using the IBM 0.13µm RF CMOS
Process Design Kit (PDK). The letter is organized as follows.
The principle of operation is presented in Section II. The detailed LNA design is shown in Section III. Its performance and comparisons with state-of-the-art LNAs are discussed in
Section IV. Finally, the paper is concluded in Section V.
Figure 1. (a) Inductive source-degeneration CSLNA (b) Capacitive feedback LNA
Figure 2. Equivalent small signal circuit of the capacitive feedback
LNA to
At resonance frequency, the input impedance,
_
, equals
/ and the transistor’s transconductance, , is effectively boosted to
_
where
_
is:
1
_
(2)
II.
P RINCIPLE OF OPERATION
A.
Inductive source-degeneration common-source LNA
The L-CSLNA seen in Fig. 1(a) uses inductive source degeneration to match the input impedance at resonance
/ and is the resonance frequency. This is the key to the
L-CSLNA’s high gain and low NF. However, these benefits come at a cost of large chip area because two inductors are needed at the gate and source of the input device. The NF of this LNA at matching condition is:

2
_
1
1
(3)
In (3), is the loss of inductor , is the gate resistance of transistor M
1,
and are the transistor M
1
‘s drain current noise and input source voltage noise respectively .
When compared to the inductive source degeneration
CSLNA, this capacitive feedback LNA requires less number of inductor for input matching. But this benefit comes with a tradeoff of higher NF which can be observed from equations
(3) and (7).
B.
Capacitive feedback CSLNA
The LNA introduced in [2] uses the parasitic gate-drain capacitance, C
2
, and output capacitance, C
L
, of the input
MOSFET to form the capacitive feedback matching network.
Its schematic is shown in Fig. 1(b) where only one inductor was used to realize the input matching. Based on its small signal circuit in Fig.2, the input network of this LNA can be converted to a series RLC matching network including of L g
,
C f
and R f
R
X
. The value of C f
and R f
can be derived from C
X
by parallel to series RC conversion, where C
X and R
X and are:
1/
1/
1/
(4)
C.
Proposed capacitive feedback CSLNA with π -match network
As seen from equations (2) and (6), the input network‘s quality factors of the two LNAs discussed above are limited by the 50 Ω matching condition. To achieve a good input matching, and / must be matched to 50 Ω . This will restrict the choosing of limit the gains of these two LNAs.
_
and
_ _
, therefore
The proposed LNA adds a parallel capacitor, C g
, preceding the gate inductor to create a π -match network. Fig.3 shows the small signal circuit for input impedance calculation of the proposed LNA. R f
and C f
are formed by the capacitive feedback mechanism as described in session II.B. Inductor L g can be divided into two smaller parts: and . These two inductors will resonate with C g and C impedance at resonance frequency is: f
respectively. The input
1/
1/
(5)
_
1/ (8)
The quality factor of this input matching network is:
1 is:
The quality factor of the proposed input matching network
_ _
(6)
_
/ (9) as:
The NF at matching condition of this LNA can be derived
_ _
1
4
(7)
Capacitor C g
adds an additional degree of freedom to the
LNA design. The effective quality factor is no longer limited by the input matching condition. Therefore, the proposed LNA will be able to achieve much higher gain when compared to the L-CSLNA and the capacitive feedback LNA. Fig.4 shows the S
21
and S
11
responses of the proposed LNA and the L-
CSLNA at the same power consumption level and output load condition. The LNAs were designed to have the same input matching at the frequency of interest. The proposed LNA clearly shows a much better gain performance. The gain of our
LNA is 4dB higher than of the L-CSLNA. The simulation results well agree with the theoretical analysis. The NF at matching condition of the proposed LNA is:
Figure 3. Equivalent small signal circuit of the proposed LNA
1
4
(10)
By comparing equations (7) and (10), it is observed that if
is smaller than , the proposed LNA could achieved a better noise performance when compared to the capacitive feedback LNA.
Figure 4. S21 and S11 responses of the proposed LNA and the inductive source degeneration LNA
To clarify the theory, an LNA was designed and fabricated using the IBM 0.13µm RF CMOS technology. Its full schematic is shown in Fig. 5(a). All inductors are on chip.
Inductors will resonate with the total capacitance at the drain node of transistor M
Capacitors C b
1b
at the frequency of interest.
are bypass capacitor. Inductors and capacitor

3
C g are designed to satisfy the matching condition as analyzed in session II.C. The second stage of this LNA is an output buffer. An output buffer was designed to match the output port to the 50 Ω load of the measuring equipment. The loading effect of the buffer is determined to be about the same as the mixer loading effect on the LNA stage.
III.
M EASUREMENT RESULTS
The LNA’s layout is shown in Fig. 5(b). The total area including the output buffer and pads is 0.74x0.84mm
2 . Fig.6 shows the voltage gain, S
11
and S
22
of the proposed LNA. The
LNA’s voltage gain at 2.4Ghz is 21.7 dB. The LNA has good input and output matching. The value is better than -12dB and the value is better than -16dB at 2.4GHz. The corresponding NF is 5.0dB as shown in Fig. 7. The IIP3 of the
LNA is -12dBm. The core LNA draws 0.6mA from a 1.0V voltage supply. Total power consumption is only 0.6mW. The comparisons of this LNA with published literatures are summarized in Table I. The LNAs in [6]-[8] have better NF but consume much more power than ours. Moreover, such low NF is not necessary for our application [1]. The performance of [4] is quite comparable with ours. However, this LNA used large resistive load to achieve high gain.
Therefore, it can’t operate at low supply voltage such as 1V.
The LNA in [8] shows a tradeoff between gain and linearity.
Its IIP3 is higher but the power consumption is much higher and the gain is much lower than ours. Based on the FOMs calculated in Table I, our LNA has the best FOM1 and acceptable FOM2 .
Freq (GHz)
Gain (dB)
NF (dB)
S
11
(dB)
IIP3 (dBm)
FOM1*
FOM2**
*: 1
**: 2
21.7
5.0
-12
-12
13.52
1.52
/
Figure 6. Voltage gain, S
11
and S
22
2.4
21.4 13 25 10.1
5.2 3.6 2.62 2.9
3
-11 n/a n/a 4
10.33 1.07 5.36 -1.61
-0.67 n/a n/a 2.34
1
/ 1
IV.
C ONCLUSION
An ultra-low power LNA with new input matching topology was presented. The design makes use of the capacitive feedback and the π -match network to realize the
Figure 7. NF
R EFERENCES input matching. The design method was explained and the
LNA was designed. Number of inductors used was reduced providing very high gain, good input matching and moderate
NF.
[1] A. V. Do, C.C. Boon, M.A. Do and K.S. Yeo, A. Cabuk, “A and higher gain was achieved when compared to the
L-CSLNA. The proposed LNA consumes only 0.48mW while
Subthreshold Low-Noise-Amplifier Optimized for Ultra-Low-Power
Applications in the ISM Band”, IEEE Trans. Microwave Theory and
Tech., Vol. 56, No. 2, pp. 286-292, Feb-2008.
[2] Y.W. Chung and F.R. Shahroury, “A Low-Voltage CMOS LNA Design
Utilizing the Technique of Capacitive Feedback Matching Network”, in
IEEE International Conference on Electronics, Circuits and Systems, pp. 78 - 81, Dec. 2006 .
Figure 5. (a) Schematic of the proposed LNA (b) Chip micrograph
[3] J. Borremans, P. Wambacq, C. Soens, Y. Rolain and M. Kuijk, “Low-
Area Active-Feedback Low-Noise Amplifier Design in Scaled Digital
CMOS “,IEEE J. Solid-State Circuits, vol.43, pp. 2422 – 2433, 2008.
[4] J.S. Walling, S. Shekhar and D.J. Allstot, “A gm-Boosted Current-
Reuse LNA in 0.18
μ m CMOS “, in IEEE RFIC Symposium, Honolulu, pp. 613-616, Jul.2007.
[5] T.T.N. Tran, C.C. Boon, M.A. Do, K.S. Yeo, " Reciprocal Noise
Canceling Low Power UWB LNA", in ISOCC '09 International SoC
Design Conference , Busan, Nov.2009.
[6] M. E. Kaamouchi, M. S. Moussa, P. Delatte, G. Wybo, A. Bens, J. P.
Raskin, and J. J. Vanhoenacker," 2.4-GHz Fully Integrated ESD-
Protected Low-Noise Amplifier in 130-nm PD SOI CMOS
Technology", IEEE Transactions on Microwave Theory and Techniques, vol. 55, no.12, pp. 2822-2831, Dec. 2007.
TABBLE I
Parameters This
Technology (µm)
Power (mW)
Vdd (V)
.
P ERFORMANCE COMPARISONS
0.13
0.6
1
0.18 0.13 0.18 0.18
[7] S. Mou, J. G. Ma, K. S. Yeo, and M. A. Do," A modified architecture used for input matching in CMOS low-noise amplifiers", IEEE
Transactions on Circuits and Systems II: Express Briefs, vol. 52, no.11, pp. 784- 788, Nov. 2005.
1.13 6.5 15 11.7 [8] L. H. Lu, H. H. Hsieh, and Y. S. Wang," A compact 2.4/5.2-GHz CMOS
1.8 1.2 1.5 1.8 dual-band low-noise amplifier", IEEE Microwave and Wireless
Components Letters, vol. 15, no.10, pp. 685- 687, Oct. 2005.