FLOATING-GATE CMOS DIFFERENTIAL ANALOG INVERTER FOR ULTRA
LOW-VOLTAGE APPLICATIONS
Y NGVAR B ERG1 , S NORRE AUNET2 , Ø IVIND N ÆSS1
AND
M ATS H ØVIN1
1
2
Department of Informatics, University of Oslo, Blindern, N-0316 Oslo Norway Email: yngvarb@ifi.uio.no
Norwegian University of Science and Technology, Department of Physical Electronics, O.S. Bragstads pl 2, N-7034 Trondheim, Norway
ABSTRACT
Ip = Ids(pM OS)
In this paper we present ultra low-voltage (ULV) floating-gate (FG)
CMOS differential analog inverters. The analog inverters may operate with a supply voltage below 1V with programmable current
levels. The current level or rather the effective threshold voltage in
FG-circuits can be programmed to appropriate values for different
applications. The analog inverters presented in this paper may be
used in ULV transconductance amplifiers. The effects of power
supply noise are thoroughly discussed. Simulated data (spice) is
provided.
=
m
Y
Ibec
exp{
i=1
1
(Vdd /2 − Vi )ki },
nUt
where Ibec is the programmed equilibrium current.
Ci
Ip
V1
Vm
Ci
Ci
Cr
V1
Vout
Vout
Cr
Vm
In
1. INTRODUCTION
Ci
A wide range of ultra low-voltage UV-programmable FG CMOS
circuits (FGUVMOS) both analog and digital have been proposed
[1, 2]. These circuits require a initialization phase called programming. The current levels or effective threshold voltages of all transistors are matched in a reversed biasing condition while exposed
to UV-light [3]. We use UV-activated conductances [4], temporarely connecting the floating gates to the supply lines, Vdd and
Vss , thus no additional programming circuitry is required.
The analog inverters presented in this paper may be used in
analog circuits, such as ULV amplifiers and multipliers. We are going to operate the analog inverters with supply voltages below 1V
while maintaining a significant current level required for a number
of ULV applications.
In section 2 the FGUVMOS transistor is briefly described and
the differential to singleended signal converter is presented. In section 3 the fully differential analog inverter is presented and finally
the single to differential signal converter is described. In this paper
we focus on the effect of power supply noise. The data presented in
this paper is somewhat unconventional. However, we believe the
and power supply noise neutralization capabilities inherent in the
differential analog inverters presented in this paper are promising.
2. FGUVMOS CIRCUITS
For a multiple input FGUVMOS transistor each input has by design an effective coupling capacitance, Ci , to the floating-gate.
The input signal (control gate) is attenuated with a factor ki =
Ci /CT , where CT is the total load capacitance seen from the gate.
ki are called the capacitive division factor for input i.
The m-input floating-gate transistor currents are given by
In = Ids(nM OS)
=
Ibec
m
Y
i=1
exp{
1
(Vi − Vdd /2)ki }
nUt
Figure 1: Floating gate additive analoge inverter, and (b) additive
analog inverter symbol.
The additive analog inverter[5] is shown in figure 1.P
We have
m
that Ip = In and Vout = {(A(m/2) + 1)/2}Vdd − A j=1 Vj ,
where A = ki /kr . If m = 1 and ki = kr we get a pure analog inverter where Vout = Vdd − Vin . We introduce an analog inversion
∗
notation for the voltage mode circuits, that is Vin
≡ Vdd − Vin . If
we define the value 0 to be Vdd /2 we can represent both negative
and postive values. The output then becomes Vout = −AVin . The
symmetric voltage mode circuits use both Vdd and Vss as refrences
and any supply noise present will clearly affect the output voltage.
In order to overcome the severe problem of power supply noise we
will introduce a differential approach.
Assume that we have a differential input signal represented as
Vin = Vin+ − Vin− . Our first approach is to convert a differential
input signal to a single-ended output signal. The circuit providing
this conversion is shown in figure 2. The capacitive division factors for the single input inverter is called ki+ and kr1 for the input
and feedback capacitors respectively. ki− , kix and kr denotes the
capacitive division factors for the double input inverter. The transistors currents in the double input analog inverter in figure 2 can
Vin-
Vout
Vin+
Vx
Figure 2: Differential input to single-endeed signal converter.
be expressed as
Vx
Vin+
Ip
In
=
=
ki− Vdd
kix Vdd
Ibec exp{
(
(
− Vin− )} exp{
− Vx )} ·
nUt 2
nUt 2
kr Vdd
(
− Vout)}
exp{
nUt 2
ki− Vin− − Vdd
kix Vx − Vdd
Ibec exp{
(
(
)} exp{
)} ·
nUt
2
nUt
2
kr Vout − Vdd
(
)}
exp{
nUt
2
In order to obtain a gain of -1 in the single input inverter we
have that ki+ = kr1 and Vx = Vdd − Vin+ . Furthermore, we
k ki+
= ki− . The transistor
assume that ki− = ki+ and thus ix
kr1
currents in the double input analog inverter are given by
Ip
=
In
=
ki−
kr Vdd
(Vin+ − Vin− )} exp{
(
− Vout )}
nUt
nUt 2
kr
Vdd
ki−
(Vin− − Vin+ )} exp{
(Vout −
)}
Ibec exp{
nUt
nUt
2
Ibec exp{
kr = ki
kr = 2ki
VoutVy
Vinkr = 2ki
kr = ki
Figure 3: Differential input and output inverter.
We can express the transistor currents assuming power supply
noise:
′
Ip
′
If we neglect the power supply noise problem we may use the
following capacitive division factors and obtain the output voltage
of the differential analog inverter:
ki−
=
Vx
=
Vout
=
Vout
=
1
kr2
2
Vdd − Vin+
1
Vdd − (Vin− + Vx )
2
1
1
Vdd + (Vin+ − Vin− ),
2
2
=
In
=
=
1
∆V } ·
nUt
ki−
1
(ki− (∆Vin+ − ∆Vin− ) −
∆V )}
exp{
nUt
2kr1
1
ki−
In exp{
(ki− (∆Vin− − ∆Vin− ) +
∆V )}
nUt
2kr1
Ip exp{
′
We can express the new output voltage Vout by solving In′ = Ip′ :
k
′
Vout
(1)
ki− and kr are the capacitive division factors of the double input
analog inverter.
If kr = 2ki we map the input signal range [−Vdd , Vdd ] to
[0, Vdd ] output signal range. A useful definition of the value 0 for
the ouput single-ended signal is Vdd /2.
The differential input circuit shown in figure 2 performs a linear conversion from a differential input Vin ∈ [−Vdd , Vdd ] to a
single-ended output Vout ∈ [0, Vdd ]. The output can be expressed
as Vout = 1/2(Vin+ − Vin− ) + Vdd /2. If we consider the DC
level of the differential input we notice an interesting characteristic. Assume that Vin+ = Vin− = x, we have that Vout = Vdd /2
for all x ∈ [0, Vdd ]. The differential to single-ended circuit will
convert the DC level to Vdd /2, which will prevent the output to
be stuck at either Vss or Vdd , and ensure that the transistors operate in the saturated region for input signals < Vdd − 100mV and
> 100mV , indepentently of the input DC level.
We can model the effect of power supply noise by assuming
′
a change in the power supply voltage Vdd
= Vdd + ∆V . If the
input is an internal signal it may be affected by the power supply
noise, we can model the power supply noise effect on the input by
imposing a change in the input voltage; 0 ≥ ∆Vin ≤ b∆V . The
effect of power supply noise in the single input inverter is given by
∆Vx
Vout+
1
∆V − ∆Vin+
2kr1
(2)
1 − ki−
Vdd
ki−
r1
(Vi+ − Vi− ) +
+
∆V
2
kr
2
ki−
(∆Vi+ − ∆Vi− )
+
kr
=
Thus the noise on the output is given by
∆Vout
=
1−
ki−
kr1
2
∆V +
ki−
(∆Vi+ − ∆Vi− )
kr
We may assume that the noise on the inputs are equal, that is
∆Vi+ = ∆Vi− = ∆Vin . Furthermore, if we apply ki− = kr1 we
have that ∆Vout = 0∀∆V and ∀∆Vin .
In order to obtain a gain equal to -1, we have that kr1 = ki+
and kr = kix + ki− . Furthermore we have that the sum of the
capacitive division factors associated to each floating-gate is equal
to or less than 1, that is ki+ + kr1 ≤ 1 and ki− + kix + kr ≤ 1.
Clearly the values kr1 = 1/4, kix = ki+ = ki− = 1/4 and
kr = 1/2 satisfy these requirements. We use small capacitors in
the single input inverter, that is k+ + kr1 = the intrinsic MOS
capacitors of the transistor connected to the floating gate, which
actually makes the single input inverter even more susceptable to
power supply noise. We need to apply larger capacitors, thus neglecting the intrincic MOS capacitors, in the double input inverter
in order to meet the requirement kr = 1/2. The accuracy of the
analog FG inverters depends on capacitor matching. Small MOS
capacitors (poly1-poly2) exhibit mismatch in the range of 1%-4%
[6] and this mismatch may appear as a gain error in the analog
inverters.
We can elaborate further on the differential to single-endeed
inverter in order to avoid problems when the output approaches
the rails due to one of the transistors entering the linear region. By
out
allowing a reduced gain, that is | ∆V
| = A < 1, we limit the
∆Vin
0.8
0.8
0.7
Vdd
Vin+
Vout-
0.6
Vdd
Vin-
0.7
Vin+
VinVout+
Vout-
Vout+
0.6
Vy
Vx
0.5
Vx
Vy
0.4
V
V
0.5
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
0.1
0.2
0.3
0.4
Vin+ (V)
0.5
0.6
0.7
0.8
Figure 4: Effects of power supply noise on the differential analog
inverter. Vin− = Vdd − Vin+ .
0
0
0.1
0.2
0.3
0.4
Vin+ (V)
0.5
0.6
0.7
0.8
Figure 5: Effects of power supply noise on the differential analog inverter with capacitive division factors presented in section 2.
Vin− = Vdd − Vin+ .
swing on Vx and Vout . Assuming subthreshold operation, the linear region for the transistors is given by ≈ 4UT . Thus by imposing
the following requirements we can avoid the rails:
0.8
0.7
Vx, Vy , Vin+ = Vin- = 0.2V
=
=
Vdd − 4UT
Vdd
Vdd − 4UT
,
Vdd
0.6
0.5
V
ki+
kr1
ki+ + kix
kr
0.4
Vx, Vy , Vin+ = Vin- = 0.4V
Vout+, Vout-
0.3
T
thus A = VddV−4U
. The relationship between the feedback
dd
A
capacitors can bexpressed as kr1 = ( A+1
)kr .
Vx, Vy , Vin+ = Vin- = 0.6V
0.2
0.1
3. DIFFERENTIAL ANALOG INVERTER
By combining two differential to single endeed signal converters
we obtain the differential input and output inverter shown in figure
3. The output can be expressed as
Vout+
=
Vout−
=
(Vout+ − Vout− )
=
0
0.72
0.74
0.76
0.78
0.8
0.82
Vdd (V)
0.84
0.86
0.88
0.9
Figure 6: The output DC level is converted to Vdd /2 for all input
DC levels.
1
1
Vdd − (Vin+ − Vin− )
2
2
1
1
Vdd − (Vin− − Vin+ )
2
2
(Vin− − Vin+ ).
0.8
Vdd
0.6
0.4
[V]
0.2
If we interchange Vin+ and Vin− the circuit operates as a identity circuit or a follower. Note however, that the input DC level is
always converted to Vdd /2 at the output.
The effect of power supply noise on Vx , Vy , Vout+ and Vout−
is shown in figure 4. Note that Vout+ and Vout− are affected by the
noise while the differential output Vout+ - Vout− is not affected by
the noise. If we apply the capasitive division factors presented in
section 2 we can avoid power supply noise affecting Vout+ and
Vout− as shown in figure 5. For a change in the power supply
voltage of ±80mV (±10%) we obtain a variation on Vout+ and
Vout− equal to ±2mV (2.5% of the power supply noise). Note
that the effect of the power supply noise is increased for Vx and
Vy compared to figure 4.
The output voltages Vout+ and Vout− and DC level is Vdd /2
for all input levels as shown in figure 6.
0
0.2
0.4
Vout+ - VoutVy - Vx
0.6
0.8
0.8
0.6
0.4
0.2
0
0.2
Vin+ - Vin- [V]
0.4
0.6
0.8
Figure 7: The differential output of the analog inverter with and
without the power supply noise neutralization. Bold lines are for
the capacitive division factors presented in section 2, and dashed
lines represents data shown in figure 4.
7
x 10 -3
Vx
Vin
6
Vout+
max 1MHz
kr = ki
= 1/4
kr = 2ki = 1/2
Deviation (V)
5
4
VoutVy
3
mean 1MHz
kr = 2ki = 1/2
2
kr = ki
max DC
mean DC
1
0 0
10
10 2
10 4
= 1/4
Figure 10: Single to differential signal converter.
10 6
10 8
10 10
Frequency noise (Hz)
∆Vy
Figure 8: Simulated deviation from an ideal transient response for
the differential analog inverter operating at 1Hz (dc) and 1M Hz.
Max and mean values are shown.
Vout+
Vx
kr = ki
kr = 2ki
Vin
=
2∆V − ∆Vout−
1
∆Vout+ = ∆V − (∆Vx + ∆Vout− )
2
1
∆Vout− = ∆V − (∆Vin + ∆Vy )
2
By combining these equations, assuming that ∆Vin = 0, we
derive
Vout
Vout-
∆Vx
∆Vout+
=
=
∆Vy = 2∆V
∆Vout− = 0
(3)
kr = 2ki
4. CONCLUSION
Figure 9: Single to differential signal converter.
Although we can observe the power supply noise on Vx , Vy ,
Vout+ and Vout− the differential output will not be affected significantly by the noise as shown in figure 7. The deviation from
an ideal transient response (no supply noise) for different supply
noise (80mV ) frequencies are shown in figure 8
For completeness we include the mapping from a single signal
to a differential signal. The differential output circuit is shown in
figure 9. We have that
Vout−
=
Vout+
=
(Vout+ − Vout− )
=
=
(Vout+ + Vout− )
=
3
1
Vdd − Vin
4
2
1
(Vdd − Vin ) −
2
3
1
Vdd − Vin −
4
2
1
Vdd − Vin
2
Vdd .
3
Vdd
4
3
1
Vdd + (Vdd − Vin )
4
2
The circuit convert a nondifferential signal Vin ∈ [0, Vdd ] to a
differential signal Vout ∈ [−Vdd /2, Vdd /2]. This circuit, however,
is susceptable to power supply noise. The circuit is assymmetric
and we need to redesign the nondifferential to differential signal
converter to provide the differential signals required on-chip.
We can use the differential input and differential output analog
inverter in figure 3 to provide the required single ended to differetial signal converter as shown in figure 10. We have for a single
input analog inverter that ∆Vout = 2k1r ∆V − ∆Vin .
∆Vx
=
2∆V − ∆Vin
We have presented novel differential analog inverters. The effect
of power supply noise is discussed. Single signal to differential
signal analog inverters, a fully differential analog inverter and a
differential to single-ended analog inverter have been presented.
5. REFERENCES
[1] Y. Berg, D.T. Wisland and T.S. Lande, “Ultra LowVoltage/Low-Power Digital Floating-Gate Circuits”, In IEEE
Transactions on circuits and systems - II, Analog and Digital
Signal Processing, VOL. 46, No. 7, July 1999.
[2] Y. Berg, Ø. Næss and M. Høvin, “Symmetrical ultralowvoltage amplifier with variable gain and linearity”, Proceedings of the 2000 IEEE International Symposium on Circuits
and Systems (ISCAS), Geneva 2000.
[3] Y. Berg and T.S. Lande, “Area Efficient Circuit Tuning with
Floating-gate Techniques”, Proceedings of the 1999 IEEE
International Symposium on Circuits and Systems (ISCAS),
Orlando 1999.
[4] R.G. Benson, and D.A. Kerns, “UV-Activated Conductances
Allow For Multiple Scale Learning”, IEEE Transactions on
Neural Networks, vol. 4, no. 3, may 1993.
[5] Y. Berg, T.S. Lande and Ø Næss, “Ultra-Low-Voltage
Floating-Gate Transconductance Amplifiers”, To appear in
In IEEE Transactions on circuits and systems - II, Analog
and Digital Signal Processing, VOL. 48, No. 1, January
2001.
[6] B. Minch “Floating-Gate Techniques For Assessing Mismatch”, Proceedings of the 2000 IEEE International Symposium on Circuits and Systems (ISCAS), Geneva 2000.