THE UNIVERSITY OF MANCHESTER
Highly Sensitive Nano Tesla Quantum
Well Hall Effect Integrated Circuits using
GaAs-InGaAs-AlGaAs 2DEG
A thesis submitted to The University of Manchester for the degree of
Doctor of Philosophy
In the faculty of Engineering and Physical Sciences
2015
Mohammadreza Sadeghi
School of Electrical and Electronic Engineering
1
Institute:
Candidate:
Degree:
Title:
Date:
School of EEE, the University of Manchester
Mohammadreza Sadeghi
Doctor of Philosophy (PhD)
Highly Sensitive Nano Tesla Quantum Well Hall Effect Integrated Circuits
using GaAs-InGaAs-AlGaAs 2DEG
February 2015
Abstract
Hall Effect integrated circuits are used in a wide range of applications to measure the strength
and/or direction of magnetic fields. These sensors play an increasingly significant role in the
fields of automation, medical treatment and detection thanks largely to the enormous
development of information technologies and electronic industries. Commercial Hall Effect
ICs available in the market are all based on silicon technology. These ICs have the advantages
of low cost and compatibility with CMOS technology, but suffer from poor sensitivity and
detectability, high power consumption and low operating frequency bandwidths.
The objective of this work was to develop and fabricate the first fully monolithic GaAsInGaAs-AlGaAs 2-Dimensional Electron Gas (2DEG) Hall Effect integrated circuits whose
performance enhances pre-existing technologies. To fulfil this objective, initially 2 µm gate
length pHEMTs and 60/20 µm (L/W) Greek cross Hall Effect sensors were fabricated on
optimised GaAs-In.18Ga.82 As-Al.35Ga.65As 2DEG structures (XMBE303) suitable for both
sensor and integrated circuit designs. The pseudomorphic high electron mobility transistors
(pHEMTs) produced state-of-the-art output conductance, providing high intrinsic gain of 405,
current cut-off frequency of 4.8 GHz and a low negative threshold voltage of -0.4 V which
assisted in designing single supply ICs with high sensitivity and wide dynamic range. These
pHEMTs were then accurately modelled for use in the design and simulation of integrated
circuits. The corresponding Hall sensor showed a current sensitivity of 0.4 mV/mA.mT and a
maximum magnetic DC offset of 0.35 mT at 1 V.
DC digital (unipolar) and DC linear Hall Effect integrated circuits were then designed,
simulated, fabricated and fully characterised. The DC linear Hall Effect IC provided an overall
sensitivity of 8 mV/mT and a power consumption as low as 6.35 mW which, in comparison
with commercial Si DC linear Hall ICs, is at least a factor of 2 more power efficient. The DC
digital (unipolar) Hall Effect IC demonstrated a switching sensitivity of 6 mT which was at
least ~50% more sensitive compared to existing commercial unipolar Si Hall ICs. In addition,
a novel low-power GaAs-InGaAs-AlGaAs 2DEG AC linear Hall Effect integrated circuit with
unprecedented sensitivity and wide dynamic range was designed, simulated, fabricated and
characterised. This IC provided a sensitivity of 533 nV/nT, minimum field detectability of 177
nT (in a 10 Hz bandwidth) at frequencies from 500 Hz up to 200 kHz, consuming only 10.4
mW of power from a single 5 V of supply. In comparison to commercial Si linear Hall ICs,
this IC provides an order of magnitude larger sensitivity, a factor of 4 higher detectability, 20
times wider bandwidth and over 20% lower power consumption (10.4 mW vs. 12.5 mW).
These represent the first reported monolithic integrated circuits using a CMOS-like technology
but in GaAs 2DEG technology and are extremely promising as complements, if not
alternatives, to CMOS Si devices in high performance applications (such as high temperatures
operations (>150 °C) and radiation hardened environment in the nuclear industry).
2
DECLARATION
No portion of the work referred to in the thesis has been submitted in support of an
application for another degree or qualification of this or any other university or other institute
of learning.
COPYRIGHT STATEMENTS

The author of this dissertation (including any appendices to this dissertation) owns
any copyright in it (the “Copyright”) and he has given The University of Manchester
the right to use such Copyright for any administrative, promotional, educational and
teaching purposes.

Copies of this dissertation, either in full or in extracts, may be made only in accordance
with regulations of the John Rylands University Library of Manchester. Details of these
regulations may be obtained from the Librarian. This page must form part of any such
copies.

The ownership of any patents, designs, trademarks and any and all other intellectual
property rights except for the Copyright(the “Intellectual Property Rights”) and any
reproductions of copyright works, for example graphs and tables (“Reproductions”),
which may be described in this dissertation, may not be owned by the author and may
owned by third parties. Such Intellectual Property Rights and Reproductions cannot and
must not be made available for use without the prior written permission of the owner(s)
of the relevant Intellectual Property Rights and Reproductions.
 Further information on the conditions under which disclosure, publication and
exploitation of this dissertation, the Copyright and any Intellectual Property Rights and
Reproductions described in it may take place is available from the Head of School of
Electrical and Electronic Engineering.
3
ACKNOWLEDGEMENTS
Praise to God for giving me the most caring family as well as health, energy, motivation,
patience and guiding me throughout my PhD.
I would like to give the deepest gratitude and appreciations to my supervisor Professor
Mohamed Missous for his fantastic support and great guidance during this PhD. I am very
proud to have worked with such a knowledgeable, experienced, supportive, encouraging and
well known scholar.
Secondly, I would like to thank our experimental officer, Dr. James Sexton for his continuous
effort in maintaining the cleanroom facilities at the highest standards and for all his professional
and helpful advices, support and assistances. Furthermore, I would like to thank the Head of
EEE School, Professor Tony Brown and the head of SISP group, Professor Krikor Ozanyan
for their great support and all the staff in the SISP and M&N groups, in particular Dr Yan Lai,
Mr Malachy Mcgowan and Mr. John Bailey, for their useful discussions, friendliness and
helpful advices.
Finally, I would like to give the heartiest thanks to my parents for their enormous support, great
understanding and sacrifices throughout my PhD. Without their support, this work would have
been incomplete.
4
DEDICATION
This thesis is dedicated to
my caring parents,
my loving grandparents (RIP)
and my kind twin sisters.
5
Table of Contents
1
2
Introduction ................................................................................................................. 21
1.1
Overview of the research ....................................................................................... 21
1.2
Aims and objectives .............................................................................................. 22
1.3
Achievements and contributions of this research project........................................ 22
1.4
Thesis outline ........................................................................................................ 23
Literature Review ........................................................................................................ 25
2.1
Introduction to III-V compound semiconductor devices ........................................ 25
2.2
Homojunctions and Heterojunctions ...................................................................... 26
2.3
Lattice constant and lattice matched materials ....................................................... 26
2.4
Band discontinuity ................................................................................................ 28
2.5
Quantum well and formation of 2DEG .................................................................. 28
2.6
Bulk and -doped layers ........................................................................................ 29
2.7
Metal to semiconductor interfaces ......................................................................... 30
2.7.1
Schottky contact............................................................................................. 31
2.7.2
Ohmic contact ................................................................................................ 32
2.8
2.8.1
High Electron Mobility Transistor (HEMT) ................................................... 33
2.8.2
Pseudomorphic High Electron Mobility Transistor (pHEMT) ........................ 34
2.8.3
HEMT/pHEMT theory of operation ............................................................... 35
2.9
3
High-speed transistors ........................................................................................... 32
Summary .............................................................................................................. 38
Magnetism and Magnetic Sensors................................................................................ 39
3.1
Introduction .......................................................................................................... 39
3.2
Magnetic Field Generation .................................................................................... 39
3.3
Magnetic sensors................................................................................................... 40
3.3.1
Search coils .................................................................................................... 40
6
4
3.3.2
Fluxgate magnetometer .................................................................................. 41
3.3.3
SQUID sensors .............................................................................................. 42
3.3.4
Magnetoresistance magnetometers ................................................................. 43
3.3.5
Fibres-optic magnetometers ........................................................................... 45
3.3.6
Hall Effect sensor........................................................................................... 46
3.4
Magnetic sensors comparisons and applications .................................................... 54
3.5
Summary .............................................................................................................. 56
Material Characterisation, Fabrication and Modelling .................................................. 57
4.1
Hall Effect integrated circuit process flow ............................................................. 57
4.2
Material Characterisation ...................................................................................... 60
4.2.1
Double Crystal X-ray Diffraction (DCXRD) .................................................. 60
4.2.2
Photoluminescence (PL) ................................................................................ 62
4.2.3
Hall Effect ..................................................................................................... 63
4.2.4
Transmission Line Measurement (TLM) ........................................................ 64
4.3
XMBE#303 structure and material characterisation results .................................... 68
4.4
Fabrication of pHEMTs, Hall sensor and the integrated circuits ............................ 69
4.5
PHEMTs Post Fabrication Measurements ............................................................. 71
4.5.1
DC measurements .......................................................................................... 71
4.1.1
RF characteristics ........................................................................................... 75
4.6
Transistor DC and RF modelling ........................................................................... 76
4.6.1
Linear modelling ............................................................................................ 76
4.1.2
Non-linear modelling ..................................................................................... 77
4.7
Hall Effect sensor characterisations ....................................................................... 79
4.7.1
4.8
5
Offset reduction technique ............................................................................. 80
Summary .............................................................................................................. 82
DC digital (Unipolar)/Linear GaAs 2DEG Hall Effect Integrated Circuits ................... 83
5.1
Introduction .......................................................................................................... 83
7
5.2
5.2.1
Integrated GaAs current source ...................................................................... 84
5.2.2
Integrated GaAs differential amplifier ............................................................ 87
5.2.3
Integrated GaAs comparator........................................................................... 91
5.2.4
Integrated GaAs level shifter .......................................................................... 95
5.2.5
Integrated GaAs source follower .................................................................... 97
5.3
Mask design ........................................................................................................ 101
5.4
Magnetic measurements and analysis .................................................................. 103
5.4.1
GaAs DC linear Hall Effect integrated circuit .............................................. 103
5.4.2
GaAs DC digital (unipolar) Hall Effect integrated circuit ............................. 106
5.5
6
Summary ............................................................................................................ 110
AC Linear Hall Effect Magnetometers using discrete 2DEG Hall sensors .................. 111
6.1
Introduction ........................................................................................................ 111
6.2
AC linear Hall Effect Magnetometer ................................................................... 111
6.2.1
Epitaxial profile of P2A Hall Effect sensor................................................... 112
6.2.2
50 Hz Hall Effect Magnetometers ................................................................ 113
6.2.3
33 kHz Hall Effect Magnetometer ................................................................ 119
6.2.4
Wide band (100 kHz) Hall Effect Magnetometer.......................................... 128
6.3
7
The DC digital (unipolar) Hall Effect sub-circuits ................................................. 84
Summary ............................................................................................................ 132
AC Linear Integrated Hall Effect Circuit ................................................................... 133
7.1
Introduction ........................................................................................................ 133
7.2
The Linear Hall Effect IC top-level design .......................................................... 133
7.2.1
The current source design, simulation and testing results .............................. 134
7.2.2
The differential amplifier design, simulation and testing results ................... 135
7.2.3
The integration of the linear Hall Effect circuits ........................................... 138
7.2.4
Linear Hall Effect integrated circuit magnetic testing and characterisation ... 140
7.3
Summary ............................................................................................................ 144
8
8
Conclusions and Future work .................................................................................... 145
8.1
Conclusion and summary of the thesis................................................................. 145
8.2
Future work ........................................................................................................ 147
Appendix A Scattering Parameters and Parameter Extraction ........................................... 149
A.1
High Frequency Measurements ........................................................................... 149
A.1.1
Scattering parameters ................................................................................... 149
A.1.2
fT and fmax Measurements.............................................................................. 151
Final word count: 37,564
9
List of Figures
Figure 2.1 – Heterojunction band structure .......................................................................... 26
Figure 2.2 – Heterojunction band diagram .......................................................................... 27
Figure 2.3 – Energy band diagram of a Heterojunction after contact ................................... 28
Figure 2.4 – Formation of Quantum well in GaAs/AlGaAs heterojunction .......................... 29
Figure 2.5 – Energy band diagram (a) δ-doped AlGaAs/GaAs heterostructure (b) Bulk-doped
AlGaAs/GaAs heterostructure ............................................................................................ 30
Figure 2.6 – Schematic band diagram of a metal and semiconductor (a) in isolated n-type
semiconductor adjacent to metal, and (b) in contact after thermal equilibrium .................... 31
Figure 2.7 – Band diagram of a metal-semiconductor interface: (a) before contact and (b) after
contact ................................................................................................................................ 32
Figure 2.8 – General HEMT structure with ∂-doping ........................................................... 33
Figure 2.9 – GaAs-Al.35Ga.65As-In.18Ga.82As pHEMT structure and band diagram ........ 35
Figure 2.10 – Ideal I-V characteristics of a HEMT .............................................................. 37
Figure 3.1 – Relationship between the magnetic field intensity of “H” and the current “i” with
the specific Radius of “r” .................................................................................................... 39
Figure 3.2 – Search coils when detecting metallic objects [37] ............................................ 40
Figure 3.3 – Illustration of the operating principles of fluxgate magnetometers. The output
signal becomes modulated by driving the soft magnetic core into and out of saturation. The
shaded regions indicate the regions of operation [37] .......................................................... 41
Figure 3.4 – The configuration of a SQUID [37] ................................................................. 42
Figure 3.5 – Set and reset operation of anisotropic magnetoresist sensor [37] ...................... 43
Figure 3.6 – Orientation of the magnetization of the ferromagnetic layers in a GMR spin valve
for different external fields H. (a) H = 0, the magnetization of the free ferromagnetic layer is
perpendicular to the magnetization of pinned ferromagnet, R = R(0). (b) Low resistant state, H
parallel to the magnetization of the pinned ferromagnet, R < R(0) [37] ................................ 44
Figure 3.7 – Output voltage versus the field for a spin valve GMR from NVE [37] ............. 44
Figure 3.8 – (a) Measured dc output solid lined and voltage noise vs. bias field of an NVE
AAH002 sensor, (b) Sensitivity solid lined and detectivity of NVE AAH002 vs. applied
magnetic field [52] .............................................................................................................. 45
Figure 3.9 – Fibre-optic prototype design [37] ..................................................................... 46
Figure 3.10 – The configuration of a Hall Effect sensor ....................................................... 47
10
Figure 3.11 – Noise spectral density at room temperature at various input bias currents from 0
to 1 mA in 5 steps for a 40 µm wide Greek cross Hall sensor (GaAs/AlGaAs) [67] ............. 52
Figure 3.12 – Noise equivalent magnetic field at room temperature at various input bias
currents from 0 to 1 mA in 5 steps for a 40 µm wide Greek cross Hall sensor (GaAs/AlGaAs)
[67] ..................................................................................................................................... 53
Figure 3.13 – Lowest room temperature noise equivalent magnetic field spectra for
GaAs/AlGaAs Greek cross Hall sensors of difference sizes, from 0.8 µm to 40 µm wide [67]
........................................................................................................................................... 54
Figure 3.14 – Comparison of magnetic field sensors in terms of magnetic sensitivity .......... 55
Figure 4.1 – The Complete work flow for the development of Hall Effect integrated circuits
........................................................................................................................................... 59
Figure 4.2 – Schematic of double crystal X-ray diffract meter ............................................ 61
Figure 4.3 – Typical experimental set-up for PL [73] .......................................................... 62
Figure 4.4 – Recombination mechanism in semiconductors [73] ......................................... 63
Figure 4.5 – Van der Pauw structure.................................................................................... 64
Figure 4.6 – Schematic diagram of a semiconductor material with ohmic contact pads [73] 65
Figure 4.7 – Planar ohmic contact structure [73].................................................................. 65
Figure 4.8 – An example of a plot of total resistance as a function of TLM pad spacing [73]66
Figure 4.9 – The fabrication steps of pHEMTs .................................................................... 69
Figure 4.10 – A fabricated 222_2×100 µm pHEMT ............................................................ 70
Figure 4.11 – The fabrication steps of Hall Effect sensors ................................................... 70
Figure 4.12 – An image of a 2×200 µm pHEMT after the annealing process with AuGe ratio
of 4 (a) and 5 (b) at the annealing temperature of 420 °C ..................................................... 72
Figure 4.13 – The normalised Schottky forward and reverse characteristics for a 2×50 µm
pHEMT ............................................................................................................................... 73
Figure 4.14 – The normalised threshold Voltage of the Fabricated XMBE303 2×50 µm
(normalised) pHEMT for VDS from 1 V to 2V (steps of 0.5 V) ............................................ 74
Figure 4.15 – Transconductance (gm) of 2×50 µm width device at VDS sweep from 1 V to 2 V
(steps of 0.5 V) and VGS sweep from -0.6 V to 0.6 V, note the very small change in gm as VDS
is changed from 1V to 2V ................................................................................................... 74
Figure 4.16 – DC IDS vs. VDS characteristic of a 2×50 µm device where VGS is swept from -0.8
V to 0.2 V ........................................................................................................................... 75
Figure 4.17 – Cut off frequency and maximum frequency at Gm maximum and V DS = 1 V . 76
11
Figure 4.18 – The schematic cross-section diagram of a pHEMT (a) and the linear small-signal
equivalent circuit of pHEMT (b) ......................................................................................... 77
Figure 4.19 – DC modelling (IV curve) for a 2 µm length, 1×50 µm width device as V GS is
swept from -0.8 V to 0.2 V .................................................................................................. 78
Figure 4.20 – RF modelling (S parameters) in the frequency range from 40 MHz to 40 GHz
........................................................................................................................................... 78
Figure 4.21 – The full model of the XMBE303 222_2×50 µm pHEMT extracted from ADS79
Figure 4.22 – Top view of the XMBE303 Greek cross Hall sensor ...................................... 79
Figure 4.23 – The connection configuration of a parallel Hall sensor (a), proposed design in
this work (b)........................................................................................................................ 81
Figure 4.24 – Offset results of XMBE303 parallel and single Hall sensors at 1 V across each
device ................................................................................................................................. 81
Figure 5.1 – The block diagram configuration of the Hall IC circuits ................................... 84
Figure 5.2 – The configuration of the GaAs integrated current source circuit in the simulation
(a) [] and after fabrication (b) – Dimension = 670 × 770 µm2 .............................................. 85
Figure 5.3 – The configuration of the differential amplifier circuit ...................................... 87
Figure 5.4 – The simulated output of the differential amplifier for 16 mV of ΔV in ............... 89
Figure 5.5 – The mask layout (a) and fabricated version (b) of the integrated GaAs differential
amplifier circuit – Dimension = 880 × 630 µm2 ................................................................... 89
Figure 5.6 – Measurement Vs simulation results of the integrated DC differential amplifier
circuit .................................................................................................................................. 90
Figure 5.7 – The configuration of the comparator circuit in simulation ................................ 92
Figure 5.8 – The simulated output of the comparator for a reference voltage of 1 V and input
sweep of 0.5 to 1.5 V .......................................................................................................... 93
Figure 5.9 – The mask layout (a) and fabricated version (b) of the GaAs integrated comparator
circuit – Dimension = 580 × 575 µm2 .................................................................................. 94
Figure 5.10 – Performance of the Integrated GaAs comparator circuits ............................... 95
Figure 5.11 – The circuit diagram of the level shifter........................................................... 96
Figure 5.12 – The output of the level shifter integrated circuit in simulation for the input range
of 2.9 V to 3.1 V ................................................................................................................. 97
Figure 5.13 – The layout of the source follower................................................................... 98
Figure 5.14 – The performance of the integrated GaAs source follower in simulation ......... 99
Figure 5.15 – The mask layout (a) and fabricated version (b) of the GaAs integrated source
follower circuit – Dimension = 1 × 0.415 mm2 .................................................................. 100
12
Figure 5.16 – The performance of the integrated source follower circuits and comparison with
the simulation results......................................................................................................... 100
Figure 5.17 – Configuration of the entire 2DEG GaAs-InGaAs-AlGaAs DC digital Hall Effect
IC...................................................................................................................................... 101
Figure 5.18 – The mask layers of the GaAs 2DEG digital Hall Effect IC ........................... 103
Figure 5.19 – The DC linear Hall Effect IC after fabrication ............................................. 104
Figure 5.20 – The full measurement setup to perform DC magnetic field measurements on the
ICs .................................................................................................................................... 104
Figure 5.21 – The output of the DC linear Hall Effect integrated circuit ............................ 105
Figure 5.22 – DC digital (unipolar) Hall Effect integrated circuit (testing mask)................ 107
Figure 5.23 – The performance of the DC digital integrated sub circuits ............................ 108
Figure 5.24 – The final fabricated DC digital Hall Effect IC using the final mask .............. 109
Figure 6.1 – Clamp-on Ammeter (a), the internal circuitry block diagram of the Ammeter (b)
[-]...................................................................................................................................... 112
Figure 6.2 – The top level design of the Portable Hall Effect 50 Hz Magnetometer ........... 114
Figure 6.3 – Circuit diagram of the 50 Hz Hall Effect Magnetometer simulated in Multisim
[116] ................................................................................................................................. 115
Figure 6.4 – Bode plot of the 50 Hz Hall Effect magnetometer .......................................... 115
Figure 6.5 – The test setup configuration of 50 Hz Hall Effect magnetometer ................... 116
Figure 6.6 – The AC current (rms) versus the displayed voltage from the 50 Hz Hall Effect
magnetometer ................................................................................................................... 116
Figure 6.7 – The magnetometer with an inductive coil (a), the 50 Hz Hall Effect magnetometer
using P2A Hall sensor (b).................................................................................................. 117
Figure 6.8 – 50 Hz Linear Hall Effect Magnetometer detecting 50 Hz magnetic field from
currents flowing in a conductor ......................................................................................... 118
Figure 6.9 – Top level design of the 33 kHz magnetometer ............................................... 119
Figure 6.10 – Circuit Diagram of the 33 kHz Hall Effect Magnetometer designed in Multisim
[116] ................................................................................................................................. 120
Figure 6.11 – The Bode plot of the 33 kHz Hall Effect Magnetometer simulated in Multisim
[116] ................................................................................................................................. 121
Figure 6.12 – The PCB layout of the 33 kHz Hall Effect Magnetometer laid out in Altium [126]
......................................................................................................................................... 122
Figure 6.13 – 33 kHz Magnetometer PCB arm shielded with Nanocrystalline foil ............. 122
Figure 6.14 – 33 kHz Magnetometer PCB in Steel box and shielded ................................. 123
13
Figure 6.15 – Magnetic field generated using a Helmholtz Coil ........................................ 124
Figure 6.16 – The full Testing Setup for measurements ..................................................... 124
Figure 6.17 – Noise Simulation of the 33 kHz Hall Effect Magnetometer performed in Multisim
[116] ................................................................................................................................. 126
Figure 6.18 – Enhancement versus the separation of a Ferrite to the Hall sensor in detection of
magnetic field [130] .......................................................................................................... 127
Figure 6.19 – Adding the Ferrites on wither sides of the P2A Hall Sensor ......................... 128
Figure 6.20 – Top level design of the wide band Hall Effect magnetometer ....................... 129
Figure 6.21 – Circuit diagram of the wide band Hall Effect magnetometer designed in Multisim
[116] ................................................................................................................................. 129
Figure 6.22 – Bode plot of the wide band Hall Effect Magnetometer simulated in Multisim
[116] ................................................................................................................................. 130
Figure 6.23 – Measured versus calculated results for the wide band Hall Effect circuit ...... 131
Figure 6.24 – Minimum detectable field measurements on the wide band Hall Effect circuit,
(measurement BW = 10 Hz) .............................................................................................. 131
Figure 7.1 – The top level design of the AC linear Hall Effect integrated circuit ................ 133
Figure 7.2 – The configuration of the Current Source Circuit in simulation (a), on the mask (b)
and after fabrication (c) – Dimension: 650 × 750 µm2 ....................................................... 134
Figure 7.3 – The configuration of the differential amplifier circuit .................................... 136
Figure 7.4 – Differential amplifier Bode plot obtained from simulation ............................. 137
Figure 7.5 – Configuration of the differential amplifier circuit (a) on the mask and (b) after
fabrication – Dimension: 525 × 720 µm2 ........................................................................... 137
Figure 7.6 – The mask layers of the GaAs 2DEG AC linear Hall Effect IC........................ 139
Figure 7.7 – Linear Hall integrated circuit layout .............................................................. 140
Figure 7.8 – Measured and calculated output at B = 250 nT .............................................. 141
Figure 7.9 – Linear Hall IC Output at magnetic fields of 2 µT, 1 µT, 0.5 µT and 0.25 µT for
the frequency range of 50 Hz to 200 kHz .......................................................................... 142
Figure 7.10 – Minimum detectable field by the Linear Hall Effect IC in the frequency range of
50 Hz to 200 kHz at S/N of 2 in a measurement bandwidth of 10 Hz ................................. 142
Figure 7.11 – Comparison of the GaAs 2DEG linear Hall IC with linear Hall ICs made by
Allegro, Honeywell and Melexis in terms of Minimum detectable field as a function of
frequency at S/N of 2 in a 10 Hz measurement bandwidth ................................................. 143
Figure A.1 – A “two-port” network characterised by relationships between the input and output
signals ............................................................................................................................... 149
14
Figure A.2 – A “two-port” connected by transmission lines to a source and load showing the
incident and reflected signals that occur ............................................................................ 150
Figure A.3 – Extrapolation of U and H21 to provide fT and fmax [73] .................................. 153
15
List of Tables
Table 3.1 – Advantages and disadvantages of the most commonly used magnetometers ...... 55
Table 4.1 – Structure of epitaxial wafer XMBE303 ............................................................. 68
Table 4.2 – Hall Effect measurement results for XMBE303 structure .................................. 68
Table 4.3 – The final extrinsic parameters for XMBE303 and the 222_2×50 device ............ 77
Table 4.4 – The final intrinsic parameters for XMBE303 and the 222_2×50 device ............. 77
Table 4.5 – XMBE303 Hall sensor characteristics ............................................................... 80
Table 5.1 – Characteristics of the GaAs integrated current source circuit ............................. 87
Table 5.2 – Summary of voltage comparator related circuit performance in different material
systems ............................................................................................................................... 91
Table 5.3 – Comparison between the 2DEG GaAs DC linear Hall Effect IC and the silicon DC
linear ICs made by Allegro, Melexis and Honeywell ......................................................... 106
Table 5.4 – The total sensitivity of the DC linear Hall Effect IC Vs the generated current to the
Hall sensor ........................................................................................................................ 106
Table 6.1 – The Epitaxial layer profile of P2A Hall Effect sensor ...................................... 113
Table 6.2 – Characteristics of the P2A Hall sensor ............................................................ 113
Table 6.3 - Measured and Expected Results....................................................................... 125
Table 7.1 – Characteristics of the integrated GaAs-InGaAs-AlGaAs (XMBE303) differential
amplifier ........................................................................................................................... 138
Table 7.2 – Summary of the GaAs-InGaAs-AlGaAs linear Hall IC characteristics ............ 143
Table 7.3 – Linear Silicon Hall Effect ICs (Honeywell, Allegro and Melexis) and comparison
with the GaAs 2DEG Hall IC ............................................................................................ 144
16
LIST OF ABBREVIATIONS
2DEG
2 Dimensional Electron Gas
ADS
Advanced Design System
AlGaAs
Aluminium Gallium Arsenide
BJT
Bipolar Junction Transistor
CMOS
Complementary Metal Oxide Semiconductor
DC
Direct Current
EEE
Electrical and Electronic Engineering
FET
Field Effect Transistor
GaAs
Gallium Arsenide
Ge
Germanium
GMR
Giant Magnetoresistance
HBT
Heterojunction Bipolar Transistor
HEMT
High Electron Mobility Transistor
IC
Integrated Circuit
InGaAs
Indium Gallium Arsenide
MBE
Molecular Beam Epitaxy
MESFET
Metal Semiconductor Field Effect Transistor
MOCVD
Metal Organic Chemical Vapour Deposition
MOSFET
Metal Oxide Semiconductor Field Effect Transistor
NMOS
n-type channel MOS
pHEMT
pseudomorphic High Electron Mobility Transistor
QW
Quantum Well
RT
Room Temperature
S-parameter
Scattering parameter
Si
Silicon
Si3N4
Silicon Dioxide
SQUID
superconducting quantum interference devices
CF4
Tetrafluoromethane
TLM
Transfer Length Method
VNA
Vector Network Analyser
17
LIST OF PUBLICATIONS

M. Sadeghi and M. Missous, “A NanoTesla Quantum Hall Effect Integrated Circuit using
InGaAs-AlGaAs-GaAs 2DEG”, UK Semiconductors 2012, University of Sheffield, UK.

M. Sadeghi, C. Liang and M. Missous, “A NanoTesla Quantum Hall Effect Integrated
Circuit using InGaAs-AlGaAs-GaAs 2DEG”, UK Semiconductors 2013, University of
Sheffield, UK.

M. Sadeghi, C. Liang and M. Missous, “Nano Tesla Quantum Well Hall Effect Integrated
Circuits using InGaAs-AlGaAs-GaAs 2DEG”, HETECH 2013, University of Glasgow,
UK, Conference Proceeding, 9th September 2013.

M. Sadeghi, J. Sexton and M. Missous, “InGaAs-AlGaAs-GaAs Nano Tesla Quantum
Well Hall Effect Integrated Circuits”, Postgraduate Poster Conference and Industrial
Advisory Group Meeting, University of Manchester, Nov 2013.

M. Sadeghi, J. Sexton, C. Liang and M. Missous, “Highly sensitive nano Tesla Quantum
Well Hall Effect Integrated Circuit using GaAs-InGaAs-AlGaAs 2DEG”, IEEE sensors
journal, November 2014, DOI: 10.1109/JSEN.2014.2368074.

M. Sadeghi and M. Missous, “Highly Sensitive InGaAs-AlGaAs-GaAs 2DEG Quantum
Well Hall Effect Integrated Circuits”, European Conference on Non-Destructive Testing
(ECNDT) 2014, Prague Czech Republic.

E. Ahmad, M. Sadeghi, J. Sexton and M. Missous, “3D physical modelling of High
mobility 2DEG Quantum Well Hall Effect Linear arrays sensors for nano Tesla metrology
applications”, Semiconductor and Integrated Opto-Electronics (SIOE) Conference, Cardiff
University 2014.

M. Sadeghi, J. Sexton, C. Liang and M. Missous, “Wide band, Ultra sensitive Quantum
Well Hall Effect Integrated Circuits using InGaAs-AlGaAs-GaAs 2DEG”, UK
Semiconductors 2014, University of Sheffield, UK.
18

M. Sadeghi and M. Missous, “Development of the low power and highly sensitive GaAs
2DEG DC linear/unipolar Hall Effect integrated circuits”, BINDT 2014, the Palace Hotel,
Manchester, UK, Conference Proceeding, 9th September 2014.

M. Sadeghi, J. Sexton and M. Missous, “Design and development of highly sensitive
GaAs-InGaAs-AlGaAs 2DEG DC Unipolar Hall Effect integrated circuit”, Submitted to
Sensors and Actuators A.
19
LIST OF AWARDS AND PRIZES

1st Prize in Low Carbon & Environment Competition, The University of Manchester, 2011

1st Prize at EPSRC ICT Pioneers in The Category of Connected World, 2012

Finalist at IET Innovation Award in The Category of Electronics, 2012

2nd Prize at IET Present Around The World, Manchester, 2012

1st Prize at PhD Poster Competition, The University Of Manchester, 2013
20
1
Introduction
1.1 Overview of the research
In recent years, the market trend in magnetic sensing has been towards developing sensors with
high sensitivity and reliability, low power consumption, reduced dimensions, large signal-tonoise ratios and low temperature dependence of key parameters, together with reduced cost.
Among all magnetic field sensors, Hall Effect sensors fulfil most, but not all of these criteria.
Hall Effect integrated circuits are widely used in such diverse applications as automation,
medical, electronic and electrical industries [1]. Commercial integrated Hall devices are
fabricated using silicon CMOS which has limited sensitivity but benefits greatly from
integrated electronics. This has created a large market where CMOS is dominant. However,
ASAHI produces Hall ICs using combination of III-V and CMOS. The Hall Effect ICs can be
divided into two categories (DC and AC) depending upon whether static of time varying fields
are to be detected.
Si DC digital (unipolar) Hall Effect integrated circuits are presently widely employed in
automotive and consumer industries and practically almost every application in consumer
electronics where DC magnetic sensing and magnetic switching is required [1]. In these
applications, a Hall sensor is used as part of a larger circuit in order to detect low DC magnetic
fields and to provide a digital output to verify the detection of the magnetic field. These ICs
(unlike bipolar Hall ICs) only operate (or are sensitive) to one pole of a magnet (either south
of north). By integrating the sensing element onto the same silicon chip as its control logic and
interface circuitry, companies such as Melexis, Honeywell and Allegro have produced unipolar
Hall ICs with different degrees of intelligence to suit a vast array of applications. These silicon
ICs have the advantages of low cost and small dimensions [2-5], but suffer from poor
sensitivity and relatively high power consumption. At present, the most sensitive commercial
Si unipolar Hall integrated circuits are made by Melexis (US5782), Honeywell (SS345PT) and
Allegro (A1101) [6-8] with switching sensitivity of 12 mT, 18 mT and 10 mT respectively.
AC linear Hall Effect integrated circuits on the other hand are employed in applications such
as position sensing and contactless current sensing. They are used to detect AC magnetic fields
and produce an output which is proportional (linear) to the strength of the detected magnetic
field. Short comings of theses ICs include low magnetic field sensitivity, limited operating
frequency range and high power consumption. At present, the most sensitive commercial Si
linear Hall integrated circuits are made by Allegro (A1324), Melexis (MLX90242) and
21
Honeywell (SS39ET). These have sensitivities of 50 mV/mT, 39 mV/mT and 14 mV/mT
respectively and are capable of detecting magnetic fields as low as 864 nT, 6500 nT and 652
nT respectively. These ICs also have a maximum cut off frequency of 10 kHz and a minimum
power consumption of 12.5 mW from a 5 V supply (MLX90242) [9-11].
1.2 Aims and objectives
To improve the performance of integrated Hall devices, especially in terms of sensitivity and
operating frequency, lower detectivity and power consumption, the aim of this work was to
develop a new type of Hall integrated circuits, based on GaAs-InGaAs-AlGaAs, which utilises
a two Dimensional Electron Gas (2DEG) system with high electron mobility and moderate
sheet carrier densities. This should permit both magnetic and circuit functionalities to be
produced in a similar manner to CMOS Hall ICs. The objectives of this work were to:

Design and grow a 2DEG GaAs-In.18Ga.82 As-Al.35Ga.65As pHEMT structure using the
Molecular Beam Epitaxy (MBE) technique

Design and fabricate Hall Effect sensors on the pre-grown structure and perform full
measurements and characterisations

Design and fabricate pseudomorphic High Electron Mobility Transistors (pHEMTs) on the
same structure and perform full DC and RF measurements

Perform DC and RF modelling on the fabricated and measured pHEMTs using Agilent
Advanced Design System (ADS) [12]

Design, simulate and mask lay out for both DC and AC Hall integrated circuits

Fabricate the DC and AC Hall integrated circuits using the designed mask and conduct all
the required measurements on individual components, sub-circuits and integrated circuits

Bond and package the ICs to perform complete magnetic and electrical measurements and
characterisations.
1.3 Achievements and contributions of this research project
Due to the inherently poor silicon Hall sensor material properties, devices made of III–V
semiconductors have attracted a great deal of interest by virtue of their high electron mobility
combined with moderate sheet carrier densities, low temperature dependences of the output
Hall voltage and large signal-to-noise ratios (S/N) [13-17]. However, the majority of this work
to date has been concerned with single Hall elements with no publications on fully integrated
Hall Effect circuit using the III–V semiconductors reported apart from [18-19]. In these
22
publications a hybrid circuit was produced using ion implanted GaAs for which the
performances were less than ideal due to the difficulties of the technologies used at the time.
In this work, all circuit elements required for successful integration have been developed in an
effort to design and fabricate the first Hall Effect integrated circuits based on 2DEG III-V
technology. These Hall Effect ICs are based on the GaAs-In.18Ga.82 As-Al.35Ga.65 As system,
which is a relatively mature technology, enabling accurate modelling and simulation of
transistors for the development of Process Development Kits (PDK).
The key achievements and contributions from this research project are:

An AC linear Hall Effect magnetometer was developed that was capable of measuring 50
Hz current flow in domestic environments non-intrusively. This is the first demonstration
of such a contact-less current meter using a Hall Effect sensor. At higher frequencies, this
magnetometer was also capable of measuring currents, non-intrusively, that were two
orders of magnitude smaller than standard clamp ammeters were capable of measuring (100
µA vs. 10 mA).

The first 2DEG GaAs-In.18Ga.82As-Al.35Ga.65As DC linear and digital (unipolar) Hall Effect
integrated circuits were successfully designed, simulated, fabricated, tested and developed.
The DC linear Hall IC enhanced the current technology in terms of power consumption,
and the DC unipolar Hall IC provided the highest switching sensitivity at the lowest power
consumption amongst all other commercial silicon DC unipolar ICs.

A 2DEG GaAs-In.18Ga.82 As-Al.35Ga.65As AC linear Hall Effect integrated circuit was
developed for the first time. This IC provided unprecedented sensitivities enhancing the
current technology by an order of magnitude. In addition, the AC linear IC dissipated less
power than commercial Si Hall ICs (by at least 20%) and improved their bandwidths by
almost 20 times (from 10 kHz to 200 kHz).
1.4 Thesis outline
Chapter 2 describes the relevant literature review of the basic concepts of III-V compound
semiconductors. Important factors that form the High Electron Mobility Transistors (HEMTs)
such as heterojunctions and heterostructures, Quantum wells, -doped and bulk doped layers,
and schottky and Ohmic contacts are then described. At the end of this chapter, the structures,
behaviours, and operating principles of the HEMT and pHEMT devices are discussed in details.
23
Chapter 3 describes magnetism and magnetic field. This is followed by a description of the
most common magnetic sensing methods. The underlying physical principles governing their
operation are then discussed and the most recent results achieved highlighted. To conclude the
chapter, these magnetic sensors are compared to the III-V 2DEG Hall Effect sensors.
Chapter 4 presents the epitaxial layer of the 2DEG GaAs-In.18Ga.82As-Al.35Ga.65 As that has
been grown and used in this work. The development process and fabrication steps of the Hall
Effect integrated circuits are discussed in details. This is followed by DC and RF measurements
of the pHEMT and Hall Effect sensor characteristics. This chapter concludes with a summary
of the steps undertaken for transistor modelling and a description of the final pHEMT model
obtained.
Chapter 5 introduces the design of sub-circuits which form the entire GaAs 2DEG DC Hall
Effect integrated circuits and describes their layout and performances and a comparison with
commercial Si DC unipolar and linear Hall Effect integrated circuits is made. The final circuit
designs of the DC unipolar and linear integrated circuits, their magnetic testing results are
illustrated and explained in detail.
Chapter 6 provides a concise treatment of the AC Hall Effect magnetic meters. Then, three
AC linear (Non-integrated) Hall Effect magnetometers designed and developed using a
previously packaged 2DEG GaAs-InGaAs-AlGaAs Hall Effect sensor, denoted as the P2A, are
presented and their performances are discussed in detail.
Chapter 7 describes the design, simulation, fabrication and testing results of the AC linear
Hall Effect integrated circuits. It also compares the performance of this IC with the Si
commercial AC linear Hall ICs.
Chapter 8 Summarises and concludes the work undertaken in this thesis and proposes further
works that can be undertaken to further enhance these new class of GaAs Hall effect integrated
circuits.
24
2
Literature Review
2.1 Introduction to III-V compound semiconductor devices
Semiconductor electronics have been the most remarkable industry of the 20 th century and
remains so in the 21st Century. Many researchers, around the world have been working towards
improving the performance of these semiconductor devices over the past 6 decades. As a result,
semiconductor devices are becoming smaller, more power efficient, faster and more
sophisticated. As the performances of these devices are improving, their effects on our daily
lives become more and more visible. Electronics, or more precisely microelectronics, is now
all pervasive, so it is hard to imagine any human activity or endeavour that does not make use
of it.
In 1947, the first semiconductor transistor, called, the point contact transistor was invented by
William Shockley. This transistor was based on a Germanium (Ge) Bipolar Junction Transistor
(BJT) structure [20]. Germanium BJT was dominant in the semiconductor market until the
early 1960s, when silicon (Si), the basis of modern semiconductor electronics, took over due
to its better thermal stability and, more importantly, its ease and low cost of manufacturing
[21]. Silicon is the most commonly used semiconductor material in current electronic devices
such as Hall Effect integrated circuits. Another imperative property of Si is the formation of a
uniform native oxide, Silicon Dioxide (SiO2), which led to the invention of the Metal Oxide
Semiconductor Field Effect Transistor (MOSFET). Complementary MOSFETS (P-type and
N-type) are employed in most digital and analogue integrated circuits to form circuits such as
amplifiers, analogue-to-digital converters, comparators and Schmitt triggers, etc. Despite these
advantages of Si, its low intrinsic mobility has resulted in other materials being considered in
order to achieve higher speed, lower power consumption, lower noise and higher operating
frequency. III-V materials are the main candidates to replace Si in these applications owing to
their significantly higher intrinsic mobility. The true potential of III-V materials was only
demonstrated when the ability to grow high-quality materials and abrupt (monolayer) interfaces
was developed. This was achieved using the two commonly used growth methods, namely
Molecular Beam Epitaxy (MBE) and Metal Organic Chemical Vapour Deposition (MOCVD).
The grown structures could then be fabricated into suitable devices using similar processing
techniques to Si technology such as lithography and etching [22]. Since 1980s, III-V compound
materials such as Gallium Arsenide (GaAs) and Indium Gallium Arsenide (InGaAs) have been
25
used in wireless and satellite communications, traffic radar and many other military and civilian
applications as well as in optoelectronics.
This chapter highlights the properties, operational principles and performance of III-V devices
and also discusses several important parameters of III-V compound semiconductor transistors.
2.2 Homojunctions and Heterojunctions
Homojunction is a term used when two similar semiconductors are brought into contact with
each other. Homojunctions are mostly used in Silicon based devices such as diodes which
consist of the same material (Silicon) but with different dopants (p and n-type) on each side of
the device.
Heterojunctions are made from two semiconductors with dissimilar crystal structures which
have a common contact or interface with each other. In a heterojunction, the two materials have
different band gaps, and as their Fermi level will align with each other to establish
chemical/thermal equilibrium, band discontinuity in both conduction and valence bands occur
(∆Ec and ∆Ev). This is illustrated in Figure 2.1.
EConduction
ΔEC
High band gap
material
EFermi
Small band
gap material
ΔEV
EValence
Figure 2.1 – Heterojunction band structure
These heterojunctions are combined with each other using techniques such as Molecular Beam
Epitaxy (MBE) to make a Heterostructure.
2.3 Lattice constant and lattice matched materials
In Heterojunctions, if the two materials have the same or very close lattice constant, then their
interface atoms will be perfectly matched and the material thickness limits will not be an issue.
On the contrary, if the two materials have different lattice constants, depending on the
difference and thickness of the growth layers, dislocations might occur at the atomic level scale
26
between the junctions. The critical thickness of the top layer can be determined from Equation
2.1.
aS
2
Where, ε (strain) is determined from Equation 2.2.
hc 

aL  aS
aS
(2.1) [23]
(2.2) [23]
Where hC is the critical thickness, ɛ is the strain between the 2 layers, aL is the lattice constant
of the top layer, aS is the lattice constant of the substrate layer.
Figure 2.2 shows the relationship between the band gap and the lattice constant of common IIIV and II-VI group compound.
Figure 2.2 – Heterojunction band diagram [24]
As shown in Figure 2.2, materials such as GaAs and AlAs have been used in many
heterostructures, since they have very similar lattice constants.
27
2.4 Band discontinuity
The key aspect of heterojunctions is the formation of energy discontinuities, which determines
the carrier transport properties and operation of Heterostructures like HEMT based devices.
When two materials with different band gaps are brought together, discontinuities in the
valence and conduction bands occur at the interface of the two materials. This is shown in
Figure 2.3.
Figure 2.3 – Energy band diagram of a Heterojunction after contact [25]
In this diagram, EC, EF and EV are the conduction band, Fermi and valence band energy levels
for material A (low band gap) and B (high band gap) respectively. Χ A and ΧB are the electron
affinity (which is the electron energy from the bottom of the conduction band to the vacuum
level). ΔEC and ΔEV are the difference in conduction bands and valence bands between material
B and A respectively.
2.5 Quantum well and formation of 2DEG
A Quantum well consists of a thin layer of a narrower-gap semiconductor (i.e. GaAs)
sandwiched between two identical larger band-gap materials (i.e. AlGaAs). The GaAs layer is
called a Quantum well and the AlGaAs layers are called barriers. Once these three layers are
grown on the top of each other, discontinuities in the conduction and valence band edges occur
at the heterojunction interfaces, and quantum wells are generated for both electrons and holes.
With the MBE technique, the quantum well can be grown to be as thin as 1 to 10 nm which is
smaller than electron mean free path or the De Broglie Wavelength [26]. This means the
trapped electrons in the quantum well can only move in two dimensions, and only in parallel
with the barrier layers [27], movement along the growth direction being forbidden. Therefore,
the free carriers confined within this region are called a 2-dimensional electron gas (2DEG).
28
Carriers in the quantum well can be supplied by dopant in the wider band-gap layers. As shown
in Figure 2.4, the energy level of donors in the supply layer is higher than the Fermi energy
level (EF). This means that electrons can freely move into the QW. Furthermore, the lowest
quantised energy level (E0) is lower than EF which forces electrons to be trapped inside the
Schottky
contact
QW.
Doped supply
(wide band)
Undoped
spacer layer
(wide band)
i.e. AlGaAs
Channel (narrow band) i.e.
GaAs
Figure 2.4 – Formation of Quantum well in GaAs/AlGaAs heterojunction
2.6 Bulk and -doped layers
The discussions previously concentrated on the bulk doping of the AlGaAs supply layer. The
main issue with bulk doping, is that the high doping level under the metal contact increases the
leakage of the schottky contact, which then degrades the device performance. To overcome
this issue, a technique called delta-doping (δ-doping), also referred to as planar, pulse, atomic
layer, or spike doping is introduced [28].
In the δ-doping technique, the doping is usually concentrated in a very thin region of the supply
layer (3 to 4 mono-layers thick) with a very high doping density (typically > 2×1012 cm-2).
Figure 2.5 shows the band diagrams of the δ-doped and homogeneously doped structure for
GaAs/AlxGa(1-x)As material system. For the δ-doped structure energy quantization, denoted as
E 0 , occurs in a quantum well generated by the built-in electrostatic potential difference in the
supply layer. Size quantization in the bulk-doped structure is much smaller and is therefore
29
neglected. If no parallel conduction occurs in the AlxGa(1-x)As layers, then the Fermi level is at
the bottom or below the bottom of the conduction band in the AlxGa(1-x)As, that is EF ≤ E 0 and
EF ≤ EC for the δ-doped and bulk-doped hetero-structure respectively [28].
(a)
(b)
Figure 2.5 – Energy band diagram (a) δ-doped AlGaAs/GaAs heterostructure (b) Bulk-doped
AlGaAs/GaAs heterostructure [29]
The 2DEG concentration in δ-doped heterostructure is higher compared to homogeneously
doped heterostructure for the same spacer layer thickness. This is mainly due to the following
two reasons:
1. The effective conduction band discontinuity is enhanced ( E0  Ec ) due to size
quantisation. In this case, electrons are more likely to transfer to the GaAs layer since the
difference in energy between the lowest states in the two semiconductors is enhanced by
E 0 .
2. The absence of depletion layer potential drop due to the localisation of donor impurities in
the δ-doped layer [28].
2.7 Metal to semiconductor interfaces
In order to bias the transistor, metal contacts are deposited onto the top semiconductor layers
(mostly cap and supply layers). The metal-semiconductor interfaces can form two types of
contacts: Schottky or Ohmic. These two contacts play very important roles in the performance
of the device, and are discussed in this section.
30
2.7.1 Schottky contact
Figure 2.6 shows the band diagram of both metal and semiconductor before and after contact.
Vacuum Level
Vacuum Level
qm
qФs
qχ
qФm
qФs
EC
qФB
EF
Eg
++
++
-- -- Eg
--
EV
qχ
qVbi
EC
qVn
EF
EV
Xdep
Metal
(a)
Metal
Semiconductor
(b)
Semiconductor
Figure 2.6 – Schematic band diagram of a metal and semiconductor (a) in isolated n-type
semiconductor adjacent to metal, and (b) in contact after thermal equilibrium [30]
When a metal is deposited onto the semiconductor, a Schottky contact is formed if the
semiconductor is lightly doped or un-doped and the metal work function (Φ m) is greater than
the semiconductor work function (Φs).
In Figure 2.6, B is the contact barrier height, m is the metal work function and s is the
semiconductor work function. The two Fermi energy levels will align with each other when
the two materials are in contact and thermal equilibrium is established. The flow of electrons
creates a depletion region (X) in the semiconductor close to the junction and results in energy
band bending. The band bending forms a barrier height B, and built-in voltage potential Vbi
that limits further diffusion of electrons from semiconductor to metal. The barrier height B
can be determined using Equation 2.3.
 B  m  
(2.3)
When a forward voltage is applied to the schottky contact, the effective barrier (B –V) and the
depletion region (X) become smaller. In this case, the electrons can easily tunnel through the
thin barrier which results in a large current flow to the metal. When a reverse voltage is applied,
(B –V) and the depletion region (X) become larger which then further restrict the flow of
current into the metal.
31
2.7.2 Ohmic contact
Ohmic refers to a contact that has a linear current voltage characteristic in both directions of
current flow. The purpose of an ohmic contact is to provide a path to the outside world without
disturbing the device characteristics. The ohmic contact resistance (RC) plays an important role
in device performance. In the case of an ohmic contact to an n-type semiconductor, the metal
work-function Фm must be smaller than the work-function of the semiconductor Фs. In
addition, heavily doped semiconductors improve the “ohmicity” of the contact. The
semiconductor-metal interface before and after ohmic contact is depicted in Figure 2.7.
(a)
(b)
Figure 2.7 – Band diagram of a metal-semiconductor interface: (a) before contact and (b)
after contact [31]
2.8 High-speed transistors
In the previous sections, the properties of semiconductor materials such as GaAs, AlGaAs and
InGaAs which are used to develop the III-V transistors were described.
Despite the dramatic reduction in gate length size of MOSFETs, Si technology still cannot
fulfil the demands in terms of speed due to its low electron mobility (electron saturation
velocity). The cut-off frequency of micron-sized MOSFETs is only in the range of 1 to 3 GHz
[32]. On the contrary, III-V materials have much higher carrier mobility (and electron
saturation velocities) due to their reduced effective masses. As a result, Metal Semiconductor
Field Effect Transistors (MESFETs) based on III-V materials produced in the 1970s provided
much higher current, gain and much lower noise. Compared to the MOSFET, the MESFET is
a bulk type device where a high-speed material like GaAs is used as the substrate.
Although, the speed and noise performance of the MESFETs were limited by the presence of
dopant atoms in the highly-doped transport channel, their performance was enhanced when
compared to silicon devices such as MOSFETs. The atoms, which supplied the necessary
charge carriers, also contributed to electron scattering due to random collisions with the ionized
impurity donors used to generate them in the same region [33]. In 1977, a structure called the
32
High Electron Mobility Transistor (HEMT) was invented. This device was designed to resolve
this contradiction [33]. Similar to most semiconductor materials, N-type MESFETs and
HEMTs are mostly used, compared to p-type as their hole mobility is relatively poor compared
to their electron mobility. The structure and characteristics of HEMTs are described in the
following sections.
2.8.1 High Electron Mobility Transistor (HEMT)
A typical AlGaAs-GaAs High Electron Mobility Transistor (HEMT) structure is shown in
Figure 2.8.
Figure 2.8 – General HEMT structure with ∂-doping
Source and drain are placed on the cap layer (GaAs) and annealed to diffuse dopants (normally
Germanium) to the channel. The gate can either be deposited onto the (undoped) Cap or supply
layer, depending upon the doping of the cap layer. This would then have Schottky behaviour.
The distance between the gate and channel is crucial in determining the threshold voltage (VT)
and transconductance (gm) of the device. The active layer of the structure is formed in-between
an undoped low band gap material and a doped high-band gap material (AlGaAs and GaAs).
In HEMTs, electrons are capable of flowing from the supply layer to the channel through the
thin spacer layer. They are then trapped in the triangular quantum well formed at the interface,
and unable to cross the barrier back into the supply layer, forming a 2DEG. The high band gap
spacer layer (AlGaAs) reduces the residual coulomb interaction between donors and electrons.
This will further increase the carrier mobility but decrease the carrier concentration. Therefore,
the thickness of the spacer layer is always a trade-off as far as conductivity is concerned.
33
Finally, the buffer layer is used to isolate any defects from the substrate surface and also to decouple it from the 2DEG.
In the model described above, the 2DEG carrier concentration is independent of dopant
concentration in the supply layer. Thus, in contrast to any other kind of semiconductor devices,
the carrier concentration and mobility can be optimised separately, and the product of the two
values determines the current and the transconductance of transistors.
2.8.2 Pseudomorphic High Electron Mobility Transistor (pHEMT)
A typical structure of a GaAs-AlGaAs-InGaAs pHEMT structure and its band diagram are
depicted in Figure 2.9.
34
Figure 2.9 – GaAs-Al.35Ga.65 As-In.18Ga.82As pHEMT structure and band diagram
As shown in Figure 2.9, the only difference between the HEMT and pHEMT is the use of
InxGa(1-x)As in the channel instead of GaAs, where x and 1-x denote the compound ratio
between InAs and GaAs. This also provides the flexibility in energy band optimisation and
energy band difference (ΔEG). Pseudomorphic High Electron Mobility Transistor (pHEMT)
utilises the concept of strained heterojunction to improve the carrier transport in the channel
(2DEG). The larger conduction band discontinuity obtained in pHEMT structure permits the
trapping of more carriers inside the quantum well thus increasing the carrier concentration
within the 2DEG. Furthermore, the effective mass of In xGa(1-x)As is less than GaAs,
introducing higher electron mobility and enhanced carrier transport properties.
2.8.3 HEMT/pHEMT theory of operation
In describing the transistor operation, two important terms, the pinch-off voltage (VP) and the
threshold voltage (VT), need to be discussed. The pinch off voltage (VP) in a delta doped HEMT
is the voltage at which all the electrons are transferred from the delta layer to the channel (or
alternatively the voltage at which the delta layer is completely depleted). This can be
determined from Equation 2.4.
qn S d *
VP 
2 0 S
35
(2.4)
Where q is electron charge, NS is delta carrier density, d * is distance between the gate metal
and the delta layer, ε0 is dielectric of vacuum and εs is the dielectric constant of the supply
region (large-band gap region).
The threshold voltage of a HEMT is the voltage at which the device turns/switches on. The
threshold voltage for a depletion mode HEMTs is negative, whereas for enhancement mode
HEMTs it is positive. The threshold voltage is determined from Equation 2.5.
VT  b 
EC
 VP
q
(2.5)
Where Φb is the barrier height formed between the gate metal and the supply layer and VP is the
pinch off voltage.
Gate voltages higher than VT induce charge carriers in the channel that are modulated by V GS.
The 2DEG sheet carrier density can be obtained using Gauss’s law and Poisson’s equation as
follows [34].
(
nS 
 0 S
d1  d 2  d 3
)[VGS  VT  VDS ( y )]
(2.6)
q
Where d1 is the supply (and cap if gate is placed on the cap) layer thickness, d 2 is the spacer
thickness and d3 is the thickness of the channel. As it can be seen from (2.6), the carrier density
is increased the closer the 2DEG is in proximity to the gate.
The High Electron Mobility Transistor operates in any of the three following regions:
1. Pinch off mode, when VGS<VT. In this case, the transistor is off and theoretically no current
flows from drain to source.
2. Linear mode, when VGS>VT and VDS< VGS - VT. In this mode, the transistor is on and the
current from drain to source is dependent on both VGS and VDS.
3. Saturation mode, when VGS>VT and VDS ≥ VGS - VT. In this region, the transistor is on, and
theoretically, the drain source current would only be dependent on V GS.
Figure 2.10 shows typical IDS versus VDS and for the VGS range from -2.5 V to 0 V in six steps.
The three operating regions discussed above are also identified on this graph.
36
Pinch off
Figure 2.10 – Ideal I-V characteristics of a HEMT [35]
The drain source current in the linear region is determined by:
I DS 
W
nCi (Vgs  VT )Vds
Lg
(2.7)
Where, W is the gate width, Lg is the gate length, µn is the carrier mobility in the 2DEG and Ci
is the Capacitance of the channel.
The drain source current in the saturation region is given by:
I DS 
W
nCi (Vgs  VT )2
Lg
(2.8)
The transconductance of HEMTs (gm) is defined as the change in IDS in response to the change
in VGS for a given VDS.
gm 
I DS
VGS
(2.9)
The output conductance of HEMTs (g0) is defined as the change in IDS in response to the change
in VDS for a given VGS.
g0 
I DS
VDS
37
(2.10)
The transconductance, gm and the output conductance g0 in the saturation region can be
determined from Equation 2.11 and 2.12.
2 I DS
(VGS  VT )
(2.11)

I DS
(1  VDS )
(2.12)
gm 
g0 
The ideal case would be to maximise g m and minimize g0 as much as possible. The intrinsic
gain of a HEMT is expressed in the following manner:
G
gm
g0
(2.13)
The intrinsic gain (G) of the transistor is important in the design of linear amplifiers.
The cut-off frequency (fT), also called the unity gain frequency, is defined as how fast an
electron can travel within a distance (L g).
fT 
gm
v
 s
2C gs 2Lg
(2.14)
Where Cgs is the input gate capacitance and vs is the electron saturation velocity.
When the amplification is at maximum (current gain is unity), the maximum frequency of
oscillation is reached and is given by:
f max 
fT
(2.15)
2 (( R g  Rs ) g 0 )  f T (2R g C gd )
Note that (fT), is independent of parasitics whereas fmax is not.
2.9 Summary
This chapter described the physics and device operations of the HEMT/pHEMT structures. It
discussed several important factors of the HEMT structures and how each contributes to the
superior characteristics of the device. The chapter concludes by enumerating several important
parameters that define the DC and RF performance of the pHEMTs.
38
3
Magnetism and Magnetic Sensors
3.1 Introduction
2DEG Hall sensors have been a key development at the University of Manchester since 1990.
This chapter introduces the basic concepts of magnetic field generation and also the various
technologies developed to accurately measure these fields. Each technology has limitations and
these will be discussed at length in this chapter.
3.2 Magnetic Field Generation
Magnetism has originally been associated with the ancient world with the “tractive force that
exists between two bodies” [36]. When a magnet is placed near (not in contact) an iron, the
magnet attracts the iron; this action-at-a-distance is caused by the magnetic field. A magnetic
field is produced by a permanent magnet or as a result of current flowing (moving electric
charges) through a conductor. The flux density (B) describes the intensity of the magnet field
at a particular point in space, and is used to measure the magnetic field. The unit of flux density
is the Tesla or Gauss (10-4 Tesla) and is accurately measured in Weber/m2 since it is a flux
density.
The magnetic field intensity or strength H can be defined in terms of the electric current i
generating it. Equation 3.1 shows the relationship between the magnetic field intensity H and
the current i in a conductor. The magnetic field intensity is given by Ampere’s law:
H
(3.1)
i
2r
The direction of
current (i)
Radius (r)
Magnetic field
intensity (H)
Figure 3.1 – Relationship between the magnetic field intensity of “H” and the current “i”
with the specific Radius of “r”
39
The magnetic induction B is the fundamental magnetic field vector, which produces the force
experienced by a moving charge. The force F is directed perpendicular to both the velocity of
the moving charge V, and the magnetic field vector B.



(3.2)
F  qV  B
Where q is the electrical charge of the particle and the expression V×B is the vector cross
product. 1 Tesla is the intensity of a magnetic field that would cause a charge of 1 Coulomb
travelling at a speed of 1 meter per second to experience a force of 1 Newton.
3.3 Magnetic sensors
Magnetic sensors are widely used in monitoring speed, motion, position, current, magnetic
tags, etc. The most common technologies used for magnetic field sensing are described in the
following sections.
3.3.1 Search coils
Search coils operate based on Faraday’s law of induction. If a magnetic flux through a coil
changes with time, a voltage proportional to the rate of change of the flux is generated between
its leads. In order to increase the overall sensitivity of the coils, a ferromagnetic material with
high permeability is normally inserted inside the coil. These high permeability materials have
a great ability to form a magnetic field within them and would intensify the detectability of
field. The signal detected by a search coil magnetometer depends on the permeability of the
core material, the area of the coil, the number of turns and the rate of change of magnetic flux
through the coil [37]. Coils are typically capable of detecting magnetic fields as low as 20 fT
with no upper limit to their sensitivity range. The capacitance created by the inter-winding of
the coil limits the frequency response of this magnetometer. Their useful frequency range is
from 1 Hz to 1 MHz, the upper limit is dependant of the ratio of the coil’s inductance to its
resistance [37]. Figure 3.2 illustrates how a search coil is used to detect metallic objects.
Search coil
Metallic object
Figure 3.2 – Search coils when detecting metallic objects [37]
40
The approach shown in Figure 3.2 uses a single coil in the sensor and the remainder of the
electronics are connected remotely. This approach is normally employed in aerospace and
industrial electronics, where high reliability sensing can be afforded such as on aircraft door
checks or for indicating the position of slats and landing gear [37]. Note that the search coil
magnetometer cannot detect DC or static fields.
3.3.2 Fluxgate magnetometer
The fluxgate magnetometer is made from two coils, a drive and a sense coil wounded over a
ferromagnetic material. It utilises magnetic induction along with the fact that all ferromagnetic
materials saturate at high fields [38]. The configuration of the fluxgate magnetometers and their
saturation and hysteresis loops can be seen in Figure 3.3.
Sense
Drive
Sense
Drive
Out of saturation
In saturation
Figure 3.3 – Illustration of the operating principles of fluxgate magnetometers. The output
signal becomes modulated by driving the soft magnetic core into and out of saturation. The
shaded regions indicate the regions of operation [37]
As the core becomes saturated, it begins to resist the increase in magnetic field, thus making it
more difficult for any additional magnetic field to pass through the core. When the core is out
of the saturation, the external magnetic field is more attracted to the core. The sensitivity of
this magnetometer depends on the shape of the hysteresis curve. For maximum sensitivity, the
magnetic field-magnetic induction (B-H) curve should be square, as this produces the highest
induced electromotive force (emf) for a given value of the magnetic field [37]. The fluxgate is
capable of detecting magnetic fields as low as 10 pT to 10 mT at frequencies up to 10 kHz. The
frequency response of this sensor is limited by the excitation field and the response time of the
ferromagnetic material. The main disadvantages of the fluxgate magnetometers are bulky
dimensions (as large as search coils) and high power consumption, dissipating five times more
power than search coils. The main advantage of the fluxgates over coils is their capability to
measure DC current fields.
41
3.3.3 SQUID sensors
The most sensitive magnetometer in measuring magnetic fields at low frequencies (below 1
Hz) is the Superconducting Quantum Interference Device (SQUID) [39-40], shown in Figure
3.4.
Superconducting
ring with point
contact junction
Readout
Superconducting
pick-up coil
B
Figure 3.4 – The configuration of a SQUID [37]
The significant sensitivity of SQUID magnetometers is based on the fact that when certain
materials are cooled below a critical temperature, a superconductor is formed and thus its
resistance is eliminated. If a line of magnetic flux passes through a ring made of
superconducting material, a current is created in the ring which would continue flowing
continuously, without any disturbances. In a SQUID, the periodic variations are exploited to
measure the current in the superconducting ring and thus ambient magnetic field [37].
Typically, the ring is inductively coupled to a radio-frequency circuit that generates a known
field and also operates as the detector output. Therefore, changes in the ring current vary the
resonant frequency of the circuit and thus, the output signal changes periodically as the field
varies. Then, by counting the peaks and valleys of the output, the measured field can be
determined. The device has three superconducting components; the SQUID ring itself, the
radio-frequency coil, and the large antenna loop all of which must be cooled to a
superconducting state. The sensitivity of the SQUIDs is limited by the magnetic field noise,
which is around 10 fT for commercial DC SQUIDs. This magnetometer itself is small, but
since there is a need for liquid helium (4 K) or liquid nitrogen (77 K) coolant, the overall
instrument is quite bulky and heavy. The power consumption of this sensor is in the order of
several watts which is mostly consumed by the radio frequency circuit.
The high sensitivity of SQUIDs allow them to be used in medical applications [41], astronomy
[42] and geological surveys [43].
42
3.3.4 Magnetoresistance magnetometers
Magnetoresistance magnetometers [44] use a change in resistance induced by an external
magnetic field. The sensors are only energised by constant current and the output voltage is a
direct measurement of the magnetic field. This simplistic design reduces overall system cost,
but at the expense of an output DC offset [45]. However, techniques such as the MEMS flux
concentrators [46] can be employed to eliminate this disadvantage but this increases the cost.
The two main types of magnetoresistance sensors are discussed in the following sections.
3.3.4.1 Anisotropic magnetoresistance sensors (AMR)
Anisotropic materials such as Permalloy (an alloy containing approximately 80% nickel and
20% iron) [37], can be used as an AMR sensor. Permalloy, with the magnetoresistance change
of less than 4% [47], is the most common material for AMR sensors. This is mainly because
of its large magnetoresistance and compatibility with silicon integrated circuits. The resistance
of such materials depends on the angle between the magnetisation and direction of current flow
[48]. In a field, the magnetization rotates toward the direction of the magnetic field and the
angle is dependent on the magnitude of the external magnetic field. The resistance of Permalloy
decreases as the direction of magnetization rotates away from the direction in which the current
flows and is lowest when the magnetization is perpendicular to the direction of current flow
[37]. Figure 3.5 illustrates how the AMR sensors operate.
Reset
Set
Figure 3.5 – Set and reset operation of anisotropic magnetoresist sensor [37]
By subtracting the output voltage when the sensor is in the reset mode from the voltage reading
in the set mode (see Figure 3.5), the inherent resistance and its noise is cancelled and the result
represents twice the output for the applied field measurement. The AMR sensors are light,
small, require 0.1 to 0.5 mW of power and can operate at temperatures between 55 oC to 200oC.
For limited bandwidth they are capable of detecting magnetic fields as low as 100 PT. They
have a wide frequency range from DC to nearly 1 GHz [37].
43
3.3.4.2 Giant magnetoresistance sensors (GMR)
GMR is a four layer structure that consists of two thin ferromagnets separated by a conductor.
The fourth layer is an antiferromagnet to inhibit the rotation and pin the magnetisation of one
of the ferromagnetic layers [37]. The pinned ferromagnet is called the hard ferromagnet and
the unpinned ferromagnet is called the soft ferromagnet [49]. In this structure, called spin valve,
larger changes in magnetoresistance are observed [50-51]. Figure 3.6 illustrates the operation
steps of a GMR spin valve structure.
Zero external H field
External H field
(a)
(b)
Figure 3.6 – Orientation of the magnetization of the ferromagnetic layers in a GMR spin
valve for different external fields H. (a) H = 0, the magnetization of the free ferromagnetic
layer is perpendicular to the magnetization of pinned ferromagnet, R = R(0). (b) Low
resistant state, H parallel to the magnetization of the pinned ferromagnet, R < R(0) [37]
Output voltage (V)
Figure 3.7 shows a plot of the voltage output from a GMR spin valve versus applied field.
Magnetic field (Oe)
Figure 3.7 – Output voltage versus the field for a spin valve GMR from NVE [37]
44
As is apparent from Figure 3.7, one main disadvantage of GMR sensor is that it saturates at
relatively low fields (~3mT in the example in Figure 17). Figure 3.8 (a) shows the measured
output voltage and voltage noise at various frequencies versus applied magnetic field of a
(NVE) AAH002 GMR sensor [52]. It can clearly be seen that the sensor starts saturating at
fields above 0.5 mT and the voltage noise increases when the sensitivity is high for smaller
fields, indicating that a magnetic noise component is present. The GMR sensors also have
hysteresis in their sensitivity and thus field detectability for positive and negative magnetic
fields. The non-linearity and hysteresis can clearly be observed from Figure 3.8 (b).
(a)
(b)
Figure 3.8 – (a) Measured dc output solid lined and voltage noise vs. bias field of an NVE
AAH002 sensor, (b) Sensitivity solid lined and detectivity of NVE AAH002 vs. applied
magnetic field [52]
Present GMR sensors can be used to detect fields as small as ~10 nT at 1 Hz to as large as
approximately a few milli-Tesla.
3.3.5 Fibres-optic magnetometers
The fibre-optic magnetometer consists of two glass fibres that are arranged to form a MachZehnder interferometer. As shown in Figure 3.9, the laser light passes through a beam splitter
into the two fibres, travels along the length of the fibres, is recombined, and arrives at a photodetector at the end of each fibre [37].
45
Figure 3.9 – Fibre-optic prototype design [37]
One of the fibres is covered with a magnetostrictive material. The dimension of the
magnetoresistive material changes dependant on the direction and magnitude of its
magnetisation. Thus, when the magnetoresistive material is exposed to an external field, the
length of the fiber changes. Because of the change in the length of the fibre, the light travelling
through the fibre arrives at the detector out of phase compared with the reference fibre. The
interference of the two light beams causes the light level at the photo-detector to change by an
amount dependent on the phase difference.
This device is very sensitive to the orientation of the field lines and could be employed to
measure the curvature of the field lines as well as the strength of the field. The fibre-optic
magnetometer, with dimension of around 1×4 inch2, is capable of detecting magnetic fields
from 10 pT to 1 mT at frequencies up to 60 kHz [37].
3.3.6 Hall Effect sensor
The Hall Effect sensor is a low cost magnetic sensor with small dimensions which is widely
used in a variety of applications. The Hall Effect phenomenon was first discovered by Edwin
Hall in 1879. According to his discovery, an electron moving through a magnetic field
experiences a force, known as the Lorentz force, that is perpendicular both to its direction of
motion and to the direction of the field. It is the response to this force that creates the Hall
voltage. The configuration of a Hall Effect sensor is depicted in Figure 3.10.
46
Figure 3.10 – The configuration of a Hall Effect sensor
One important factor that determines the sensitivity of the Hall Effect sensor is the material.
High mobility materials provide higher sensitivities. This is because, the faster the electrons
are moving, the stronger the force they experience and therefore the greater the Hall voltage
produced. Most of the commercial Hall devices are based on silicon whose main advantages
are their low cost, small dimension and light weight. More sensitive Hall sensors can be made
from III-V semiconductors which have higher mobilities and therefore higher sensitivities.
Silicon Hall Effect sensors have the sensitivity range of 1 mT to 100 mT whereas the III-V
Hall element extends the lower limit to 100 nT. The III-V Hall Effect sensors currently
available are capable of measuring both DC and AC (up to 1 MHz) of magnetic fields. Their
power requirements are also between 0.1 W and 0.2 W and they can operate at temperatures
from -40 °C to 200 °C (the maximum temperature limit for Si Hall sensor is ~150 °C).
A Hall Effect sensor’s output voltage can be determined from Equation 3.3.
VH  G
RH IB
d
(3.3)
Where VH is the Hall voltage; I is the total biasing current; B is the magnetic field; d is the
thickness of conductor, G is the geometrical factor and RH is the Hall coefficient (RH = 1/ne).
For an extrinsic semiconductor, the Hall voltage can be expressed in terms of the bias voltage
[53].
VH   H
w
GVB
l
(3.4)
Where H is the Hall mobility of the charge carriers; l and w are the length and width of the
Hall device, respectively. The absolute sensitivity SA of the magnetic sensor is defined as:
47
SA 
VH
w
  H GV
B
l
(3.5)
Supply-current-related sensitivity is defined by:
SI 
S A 1 VH

I
I B
(3.6)

V H IS I B
(3.7)
By substituting the Hall voltage VH in Equation 3.6:
R
SI  G H
d
(3.8)
If the plate is strongly extrinsic, RH is given by:
RH 
rH
qnd
(3.9)
Where q is the elementary charge, n is the charge carrier density of the carrier electrons; and
Equation 3.8 attains the form:
 SI  G
rH
qnd
(3.10)
In low doped, small doping gradient layers, the nd product should be replaced by the surface
charge carrier density Ns. Then, SI becomes:
 SI  G
rH
qN S
(3.11)
Where, the product qNS equals the charge carrier due to free electrons per unit area.
In addition, Popovic et al. [54] showed that the performances of Hall magnetic sensors depend
on improvements of the following non-ideal characteristics:

The long-term stability of all characteristics, but in particular of sensitivity and offset.

Noise is a limiting factor in low-level magnetic measurements, such as in current sensing.
Usually, 1/f noise is the most severe. 1/f noise may be decreased by several orders of
magnitude if perfect materials and buried structures are used.

The temperature cross-sensitivity of a Hall device is an undesirable sensitivity of its
characteristics, such as magnetic sensitivity, to temperature.
48
3.3.6.1 AlGaAs-GaAs-InGaAs 2DEG Hall Effect sensor
The AlGaAs-GaAs-InGaAs 2DEG is one of the most sensitive types of Hall Effect sensors
mainly due to its very high mobility. Sileo et al. [55] proposed a new approach to fabricate an
integrated three-axis Hall sensor. A 2DEG AlGaAs-InGaAs-GaAs multilayered structure was
developed which showed excellent linearity versus the magnetic field with an absolute
sensitivity as high as 0.03 V/T at 0.6 V bias voltage. Lee et al. [56] fabricated a quantum-well
Hall devices based on Si-delta-doped Al0.25Ga0.75As/In0.25Ga0.75As/GaAs pHEMT materials
grown by the low-pressure Metal Organic Chemical Vapour Deposition (MOCVD) method. A
Si -doped GaAs layer was developed for the first time in the Hall device to reduce the thermal
variation of electron concentrations and to enhance its temperature characteristics. A high
electron mobility of 8100 cm2 V−1 s−1 with a sheet carrier density of 1.5  1012 cm2 was
obtained at room temperature. The minimum detectable magnetic fields of 60 nT at 1 kHz and
110 nT at 100 Hz and one of the best temperature coefficients of 0.015% K−1 were obtained.
Del Medico et al. [57] described the optimisation of the growth of pseudomorphic
In0.75Ga0.25As/In0.52Al0.48As heterostructures by Molecular Beam Epitaxy (MBE) to introduce
new types of magnetic sensors using the properties of a 2DEG and the benefit of strain in
pseudomorphic channels. A low sheet electron density of 9.84  1011 cm2, a high mobility of
13000 cm2 V−1 s−1 at room temperature, and a sensitivity of 580 V A−1 T−1 with a temperature
coefficient of 550 ppm °C−1 between 80 °C and 85 °C were obtained. High signal-to-noise
ratios corresponding to minimal detectable fields of 350 nT Hz1/2 at 100 Hz and 120 nT Hz1/2
at 1 kHz were also measured. V. Mosser et al. [58] reported a low cost 2DEG GaAs-AlGaAsInGaAs Hall Effect sensor with large sensitivity of 750 V/A/T showing mean offset value of
0.35 mT. M. Haned and M. Missous [59] reported two Greek cross Hall structures, denoted as
P2A and P15A, using AlGaAs-InGaAs-GaAs materials and having resolutions of 1 µT at DC
and 100 nT at higher frequencies. P2A and P15A Hall sensors have current sensitivity of 200
and 1000 V/AT respectively and can operate at temperatures from -100 oC to +180 oC.
3.3.6.2 Noise of the Hall Effect sensor
Noise is an unwanted signal that is considered to be one of the main limiting factors in all
semiconductor devices such as Hall Effect sensors. In addition to the sensitivity, noise
determines the smallest magnetic field that can be detected. Total noise can be described as the
sum of three main types, namely thermal, 1/f and generation-recombination noises.
SNV(f) = SVT(f) + SVα(f) + SVGR(f)
49
(3.12)
Where, SVT(f) is the thermal noise, SVα(f) is the 1/f noise and SVGR(f) is the generationrecombination (GR) noise spectral densities.
Thermal noise exists in semiconductors mainly due to the random carrier motions, regardless
of any applied voltage/current. Thermal noise is observed as a frequency independent plateau
at high frequencies [68]. This is determined from:
S2V, noise = 4.kB.T.R
(3.13)
Where, kB is the Boltzmann’s constant, T is the absolute temperature and R is the resistance of
the Hall device.
1/f or flicker noise is inversely proportional to the frequency and is present due to conductance
fluctuations. It is well established that the fluctuations causing the 1/f noise originate from [6061]:
1. Fluctuations in the number of free charge carriers
2. Fluctuations in the mobility
Both of which depends on the crystalline quality of the semiconductor. Equation 3.14 was
proposed for 1/f noise by Hooge [60].
S R ,noise
R
2

SV ,noise
V
2

S I ,noise
I
2


(3.14)
fN
Where S is the noise spectral density, R, V and I are the Hall device resistance, applied voltage
and current respectively. N is the number of carriers, f is the frequency of operation and α is
the Hooge parameter [60], which is in the order of 10-9 to 10-3, depending on material, crystal
quality, scattering mechanism determining the mobility and processing technology [60, 62-67].
Scattering mechanism in a semiconductor device can be divided into lattice scattering and
impurity scattering. According to Matthiessen’s rule, the resultant measured mobility is given
by:
1
meas

1
latt

1
imp
(3.15)
Where, µlatt and µimp are the measure of mobility based on lattice and impurity scattering.
Fluctuations in mobility can be expressed as
50
(
1
 meas
1
)  (
 latt
)  (
1
 imp
)
(3.16)
In the case of doped quantum wells or doped bulk materials, ionised purity scattering
dominates.
2




  meas   latt   meas   imp
 
  latt 
 imp 
2
 meas
(3.17)
Thus, assuming that the conductivity fluctuations are caused by the fluctuations in the number
of carriers, the following situations can be met [60, 68]:
1. α is proportional to the number of generation-recombination centres creating the 1/f
spectrum and not scattering electrons: αmeas ≈ 1/µmeas.
2. α is proportional to the number of centres scattering electrons
3. α is proportional to the number of centres scattering electrons, but µmeas ≈ µlatt: αmeas is
proportional to k/ µmeas, where k >> 1. [68]
Generation recombination noise exists due to the random variations in the number of carriers.
This may be the cause of generation and recombination processes between the bands and
centres in the band gap. In the case of compound and heterostructures, this type of noise is
normally presented as superimposed on 1/f noise, due to the lattice defects. The noise spectral
density of generation-recombination noise is given by [69]
Sg _r  
Bi
1  (2f i ) 2
(3.18)
Where Bi is the amplitude and f is the frequency. The characteristic time constant T i can be
defined as the capture Tc and emission Te time constants [68]:
1


1
e

1
(3.19)
c
From the total noise spectral density, the magnetic field detection limit (DL) of a Hall sensor
can be determined [70].
 f 2 S NV ( f )
DL   
df
f 1 ( IS ) 2
I




1/ 2
f2
   BN2 ( f )df 
 f1

1/ 2
BN, called the noise equivalent magnetic field, can be determined from Equation 3.21.
51
(3.20)
BN  S 1NV/ 2 I 1 S I1
(3.21)
If bandwidth of measurements (Δf) lies in a frequency range where thermal noise dominates,
then BNT is inversely proportional to the bias current I. Thus, the detection limit (DL) can be
decreased by increasing current. However, when Δf lies in a frequency range where 1/f and/or
GR noise are dominant, BI is independent of I. Therefore, in order to enhance the Hall sensor
performance in terms of low field detectability, one should measure the Hall output in a narrow
bandwidth in the thermal region and at as high bias currents as possible. This, of course, will
have limitations such as higher power consumption and increase in the 1/f noise which could
gain importance at higher frequencies. In order to reduce the 1/f noise, α should be kept as
small as possible, thus the charge carriers in the active area should not be too small [67]. The
result of the bias current on the total noise has been studied and discussed in [67]. In this
experiment, the total spectral density for a GaAs/AlGaAs 40 µm wide Greek cross Hall sensor,
at various bias currents (From 0 to 1 mA in 5 steps) was measured. As shown in Figure 3.11,
when the bias current is zero, only the white thermal noise is observed, with a small 1/f noise
generated from the measurement setup. The effect of 1/f and GR noise can clearly be observed,
when the bias current is increased.
Figure 3.11 – Noise spectral density at room temperature at various input bias currents from
0 to 1 mA in 5 steps for a 40 µm wide Greek cross Hall sensor (GaAs/AlGaAs) [67]
Figure 3.12 shows the noise equivalent magnetic field of the same device.
52
Figure 3.12 – Noise equivalent magnetic field at room temperature at various input bias
currents from 0 to 1 mA in 5 steps for a 40 µm wide Greek cross Hall sensor (GaAs/AlGaAs)
[67]
As can be seen in Figure 3.12, where the 1/f noise and GR noise are dominant, increasing
current doesn’t improve the Hall sensor’s performance in terms of DL. For this particular
device the smallest field detectable at 100 kHz is ~90 nT at low bias but degrades considerably
to 300 nT at higher bias current pointing to the fact that defects are very dominant and the pure
Johnson noise regime is never reached.
According to [67] and [71], the noise density of the Hall Effect sensor is also affected by the
dimension of the active area in the Hall element. For smaller devices and for the same electric
field across the device, the noise is larger due to the self-heating effect [71]. The lowest noise
equivalent magnetic field spectra for GaAs/AlGaAs Greek cross Hall sensors with width from
0.8 µm to 40 µm are depicted in Figure 3.13. It can be seen that the noise equivalent magnetic
field spectra is significantly lower for larger devices. At 10 kHz the DL ranges from 90 nT to
10 µT. The DL is much worst at lower frequencies
53
Figure 3.13 – Lowest room temperature noise equivalent magnetic field spectra for
GaAs/AlGaAs Greek cross Hall sensors of difference sizes, from 0.8 µm to 40 µm wide [67]
Larger Hall devices perform better in terms of DL. However, the total parasitic capacitance for
these devices is larger (Capacitance is proportional to the Area). This would increase the total
RC time constant resulting in a slower response and a lower upper frequency limit the device
can operate at.
Thus for a specific application, one should consider noise, operating frequency, resolution and
power consumption when designing the geometry of the Hall element.
3.4 Magnetic sensors comparisons and applications
The most commonly used magnetometers were discussed in details previously. Figure 3.14
lists the available magnetic sensors and compares them in terms of sensitivity and magnetic
dynamic range.
54
Figure 3.14 – Comparison of magnetic field sensors in terms of magnetic sensitivity
As can be seen the GaAs-InGaAs-AlGaAs 2DEG (as reported by Haned and Missous [59]) has
the highest dynamic range of all magnetic sensors (~180 dB). This was the starting point of
this work and thesis.
Table 3.1 summarises the advantages and disadvantages of the previously discussed
magnetometers.
Table 3.1 – Advantages and disadvantages of the most commonly used magnetometers
Magnetometer type
Search coils
Advantages
1. High sensitivity
2. Low cost
Fluxgate
1. High sensitivity
2. Low cost
3. Can measure both DC
and AC fields (unlike
coils)
SQUID
1. Ultra high sensitivity
Nuclear Precession
1. High sensitivity
55
Disadvantages
1. Large dimension and
heavy weight
2. Cannot measure DC
fields
1. Large dimension and
heavy weight
2. Limited high operating
frequency (~10 kHz)
3. High power
consumption
4. Saturates at high fields
(~mT)
1. Large dimension and
heavy weight
2. Needs cooling
3. High cost
4. High power
consumption
5. Saturates at high fields
(~µT)
1. Complex system
2. Large dimension
3. High cost
4. Limited high operating
frequency (~60 kHz)
5. Saturates at high fields
(~1 mT)
GMRs
Commercial Si/GaAs Hall
Effect
2DEG GaAs Hall Effect
1.
2.
3.
4.
1.
2.
3.
1.
2.
3.
4.
5.
High sensitivity
Low cost
1. Saturates at high fields
Small dimension
(~1 mT)
Low power
Low cost
Small dimension
1. Moderate sensitivity
Low power
High sensitivity (not as
high as coils, SQUIDs or
fluxgates)
Low cost
Small dimension
Low power
Wide dynamic range
3.5 Summary
In this chapter, magnetism and magnetic field theory were briefly introduced. The most
common magnetic sensing methods were described and the underlying physical principles
governing their operation and the most recent results achieved were highlighted. Finally a
comparative study explained why III-V 2DEG Hall Effect sensors have attracted the most
attention amongst all magnetic sensors in terms of volume/sensitivity ratios.
56
4
Material Characterisation, Fabrication and Modelling
In this work, the high mobility 2DEG pseudomorphic GaAs-InGaAs-AlGaAs heterostructure
was custom engineered to enable co-integration of a High Electron Mobility Transistor
(pHEMTs) and a high sensitivity Hall Effect sensor in order to form the Hall integrated circuits.
Each component was individually fabricated, characterised and modelled so that they can be
used in the design of the ICs.
In the design of commercial Hall Effect ICs, multiple stages of amplifications are normally
used in order to achieve high sensitivities. In this work, the intention was to develop high
intrinsic gain pHEMTs in order to achieve both high-gains and low output conductance, so that
ultra-high sensitivities can be achieved with only a single stage of amplification. This would
reduce the overall size and power consumption of the ICs. Furthermore, in order to simplify
the fabrication process and obtain high yields, a 2 µm gate length pHEMTs were considered
offering ample frequency spectrum for the intended applications. After a successful fabrication
and characterisation, it was then vital to model the pHEMTs and extract all the DC and RF
parameters needed for accurate and functional circuit modelling. The modelling of the
processed pHEMTs was performed using Agilent Advanced Design System (ADS) software
[12].
In addition, the design of the pHEMT structure was adapted to form a Greek cross Hall Effect
sensor. After a successful development of this sensor, it was then fully characterised so that it
can be used in the design of the integrated circuits.
This chapter describes the characteristics of the GaAs-InGaAs-GaAs pHEMT structure that
was accurately engineered and grown to develop the devices and the ICs. A detailed process
flow of the 2DEG GaAs Hall ICs, pHEMTs and Hall sensor measurement techniques and
results of the pHEMTs modelling are described.
4.1 Hall Effect integrated circuit process flow
Figure 4.1 shows the complete GaAs Hall Effect integrated circuit workflow developed at the
University of Manchester. The entire process includes the material growth, Hall Effect
characterisation, fabrication of pHEMTs and Hall sensors, DC and RF measurements on
pHEMTs and Hall sensors, transistor modelling, integrated circuit design and simulation,
fabrication of ICs, bonding and packaging and circuit test and analysis.
57
The process commences with the material growth using Molecular Beam Epitaxy. Material
quality characterisation is then performed on the grown wafer which includes double crystal
X-ray diffraction (DCXRD), photoluminescence (PL) and Hall Effect measurements. Once the
4” wafer was characterised, it is then diced into smaller tiles of 15 mm ×15 mm samples.
Normally one sample is used for each fabrication. PHEMTs and Hall sensors are then
lithographically processed onto a sample (using a mask that is previously generated) and the
completed devices are then characterised using DC and RF measurements. After a successful
fabrication and characterisation, the pHEMTs are then modelled and all the required DC and
RF parameters are extracted in order to create a complete transistor model. This model is then
used to design the integrated circuit. Once the circuit is designed and fully simulated, a mask
is then laid out so that the circuits can be lithographically processed. The workflow continues
with the fabrication of the integrated circuits using the generated mask and measurements and
characterisation of the ICs. Some of the measurements can be conducted on-wafer in the lab,
however in order to conduct complete magnetic measurements, the ICs are bonded and
packaged. The outcome is then a fully characterised GaAs Hall Effect integrated circuit.
All these steps were carried out in house, at the University of Manchester. More details about
each of these steps will be discussed in subsequent sections and chapters.
58
Figure 4.1 – The Complete work flow for the development of Hall Effect integrated circuits
IV (222 Device)
0.06
5
0.05
2
3
4
0.04
IDS (A/mm)
1
0.03
0.02
0.01
0.00
0.0
0.5
1.0
1.5
2.0
VDS (V)
40
Gain (dB)
30
fT
fmax
20
10
0
1E8
1E9
1E10
Frequency (Hz)
Material growth
Material characterisation
9
10
Wafer dicing into smaller pieces
8
Fabrication of pHEMTs
and Hall Effect sensors
DC and RF
measurements
7
0.005
Id_msr
IDS.i, A
0.004
6
0.003
0.002
0.001
-0.000
0.0
Bonding and packaging
Fabrication of integrated
circuits
11
Generation of mask for the
IC
Integrated circuit design
& simulation
0.3
0.5
0.8
1.0
VDS
Vds
1.3
1.5
1.8
12
Testing and characterisation of integrated circuits on wafer
Magnetic measurements on the packaged integrated circuits
59
2.0
DC & RF transistor
modelling
4.2 Material Characterisation
Assessing the integrity of post-grown material is so essential for any given process that a brief
explanation of techniques is necessary. Typical logical requirements for the examination of
each epitaxial structure would include thickness, electrical properties, composition (in the case
of a hetero-epitaxial compound), chemical impurities and physical imperfections such as
dislocations. The extremely small thicknesses in current state of the art devices require
specialist equipment and techniques to probe these thin layers. A combination of nondestructive and simple processing is usually sufficient to fully characterise a given sample. The
most common techniques are Double Crystal X-Ray Diffraction (DCXRD) and
Photoluminescence (PL). These provide information about the structure, composition and
optical performance of layers. Other methods such as Hall Effect or transmission line model
(TLM) give critical electrical characteristics. Once the quality of the grown structure is
approved, it can be processed to make actual devices, lithographically. This section describes
the experimental methods used in this work to accurately characterise the material and the
epitaxial structures.
4.2.1 Double Crystal X-ray Diffraction (DCXRD)
The most useful non-destructive technique for the assessment of epitaxial structures is double
crystal X-ray diffractometry, developed in the 1930s [72]. The principle of the technique shown
in Figure 4.2 consists of the sequential diffraction of X-rays from reference and specimen
crystals. The reference crystal (normally the same material as the substrate) behaves as a
monochromator, and reflects a highly parallel beam of X-rays to probe the sample crystal. As
the sample crystal is rotated (or rocked), variations in intensity with angle result due to the
interference of X-rays reflected from parallel crystal planes within the crystal.
60
Figure 4.2 – Schematic of double crystal X-ray diffract meter [73]
The basis of all diffraction experiments is the Bragg law, which in its simplest form is:
2d sin   n
(4.1)
Where d is the spacing between identical planes,  is the wavelength and  is the diffraction
angle.
If the sample crystal were identical to the reference crystal, Equation 4.1 verifies that maximum
intensity will be obtained at the Bragg angle ( =B=S). However, typical epitaxial structures
often contain various layers, lattice matched or strained on a particular substrate. Any changes
in composition would cause mismatch (tetragonal distortion and therefore alter d). In these
cases, multiple peaks would appear within the rocking curve as Bragg's law is satisfied at
different angles due to the changes in spacing between identical planes. The broadness of these
peaks is mainly affected by the layers thickness, as well as variation in composition. From
theory, an infinitely thick layer will have an infinitely thin peak. However, in the case of real
layers, these will have finite thickness and therefore have finite peak width. In addition, the
peak widths are affected due to deformations in the lattice, non-homogeneous composition or
thermal vibrations within the lattice.
For a single epitaxial layer, the rocking curve provides the following data [74]:
Separation of peaks == > Lattice mismatch and therefore composition
of ternary compounds
61
Ratio of peak area == > Layer thickness
Peak width == > Layer and substrate perfection
Point by point == > Curve sampling uniformity
4.2.2 Photoluminescence (PL)
A second non-destructive technique for the characterisation of semiconductors is
photoluminescence (PL) [75]. Photoluminescence measurements are usually carried out using
an experimental setup shown in Figure 4.3. A sample is energised with an optical source,
typically a laser that has photon energy exceeding the band-gap of the sample under test. This
photo-excitation causes electrons within the material to move into higher permitted energy
states, producing electron holes pairs in the process. Once these electrons relax to their
equilibrium states and recombine with a hole, the excess energy is released, either in the
emission of light (a radiative process) or heat (a non-radiative process).
Figure 4.3 – Typical experimental set-up for PL [73]
The energy of the emitted light (photoluminescence) is directly related to the difference in
energy levels between the two electron states involved in the transition and is given by Planck’s
equation:
E  hv
(4.2)
Where h is Planck’s constant, v is the frequency.
The recombination can occur via several mechanisms, with band-to-band transitions (Figure
4.4) dominating at room-temperature [75]. However, at low temperatures, to typically 4.2 K
62
this is rarely observed. The weak columbic attraction that exists at these extreme temperatures
between oppositely charged electron and holes results in an excited state, with energy slightly
lower than the band-gap [75] (Figure 4.4 (b)) that dominates the characteristics. Impurity bound
transitions (Figure 4.4 (c-e)) can be measured by changing the intensity incident on the sample.
At low intensity, the carriers move to the lower lying states and essentially there is no emission
from higher lying states [76].
Figure 4.4 – Recombination mechanism in semiconductors [73]
The quality of the sample can also be identified using PL. Impurities or lattice imperfections
introduce energy levels, ET within the forbidden energy gap (Figure 4.4 (f)). These generate
defect states [77] that act as a recombination centre that are capable of catching a carrier of one
type and then confining a carrier of opposite type, thereby enabling them to recombine. As
these defects usually emit a phonon, quantifying the amount of radiative recombination can
therefore assess the quality of the material.
4.2.3 Hall Effect
Hall Effect measurement is used to obtain information on carrier type (electron or hole), carrier
concentration, and mobility. The basic principle of Hall Effect and Lorentz force were
discussed in chapter 3.
In a semiconductor, electrons and holes have opposite charges, and thus, move in opposing
directions. The Lorentz force can therefore be seen to act in the same direction for both these
carriers, resulting in an excess surface electrical charge on one side of the semiconductor. The
potential difference between the two sides is the Hall voltage which gives a direct indication
of the total number of charge carriers present. Hence, the doping concentration can be
63
determined, Na, and if the thickness, d is known, the hole mobility, h can be calculated by
evaluating the sheet resistance, Rsh.
h 
1
dN A qRsh
(4.3) [78]
The sheet resistance of the semiconductor can be determined by a technique called the van der
Pauw method [79]. In this work, a structure similar to the one originally devised by van der
Pauw was utilised to measure both resistivity and Hall voltage and is shown in Figure 4.5. In
this configuration, multiple measurements can be taken between opposite pads and averaged
to obtain accurate measurements of carrier concentration and mobility.
Indium Alloyed Contact
Figure 4.5 – Van der Pauw structure
4.2.4 Transmission Line Measurement (TLM)
The final method to accurately assess the ohmic contacts during the device fabrication is the
transmission Line Measurement (TLM). TLM was first developed by Berger [80] and Murrman
and Widmann [81] in 1969.
This technique allows for simultaneous evaluation of materials and fabrication quality, as well
as uniformity testing. The process relies strongly on producing linear IV metal-semiconductor
(ohmic) contacts discussed in Chapter 2.
The TLM uses a test pattern made of differently spaced ohmic contact pads as shown in Figure
4.6. The ohmic contacts are separated by a distance li and the pattern is isolated to confine the
current to flow to the width W. There are two values of sheet resistance of interest, the sheet
resistance of the semiconductor material between the ohmic contacts (Rsh) and the sheet
resistance of the material under the ohmic contact, (Rsk).
64
Figure 4.6 – Schematic diagram of a semiconductor material with ohmic contact pads
[73]
The ohmic contact is located on thin conductive layer with a semi-insulating layer beneath.
This results in current flow parallel to the plane of the metal rather than perpendicular to it
which results in reducing the effective contact area from the true contact area [77]. In these
cases the contact resistance, Rc is defined as the resistance between the metal and an imaginary
plane that is at the edge of and perpendicular to the metallisation (see Figure 4.7). The contact
resistance is thus a function of both the specific contact resistance and the characteristics of the
conducting layer on which the contact is formed.
The transfer length (LT) is related to the lateral distance required for the current to flow into or
out of the ohmic contact. All the current goes through the imaginary plane at the contact’s edge.
Most of this current flows into the metal very near the contact edge and the small remainder
enters the metal contact further from the edge. The distance from the contact edge that it takes
for the current in the semiconductor to reduce to 1/e of its original value is defined as the
transfer length.
Lt
V
Ohmic
Contact
Imaginary
Plane
Figure 4.7 – Planar ohmic contact structure [73]
The resistance between two contact pads consist of the two contact resistances plus the
resistance of the semiconductor layer between the two contacts. The semiconductor resistance
theoretically depends only on the sheet resistance, the width of the contact and the distance
65
between the contacts. Hence, the resistance between two such contacts Ri separated by li is
given by:
Ri  2 Rc 
Rshli
W
(4.4)
Thus assuming the sheet resistance is constant, a plot of measured resistance as a function of
spacing between pads, l should give a straight line as shown in Figure 4.8. The slope of the line
gives
Rsh
, and the intercept with the R-axis gives a value of 2Rc. The intercept with the L axis,
W
is related to the transfer length, LT.
Gradient = Rsh/WR
Gradient =
sh
W
Intercept = 2Rc
Intercept =Lx
Figure 4.8 – An example of a plot of total resistance as a function of TLM pad spacing
[73]
Reeves et al [82] have shown that Rc can be expressed as:
2 Rc 
Therefore:
Ri 
2 Rsk LT
W
2 Rsk LT Rshli

W
W
66
(4.5)
(4.6)
And
c
LT 
Rsk
(4.7)
Where, c is the specific contact resistance.
Thus combining Equations 4.5 and 4.7, gives:
Rc 
 c Rsk
W
(4.8)
The relationship between Lx and LT can be found using Equation 4.9.
Lx 
2 Rsk LT
Rsh
(4.9)
Under simplified TLM, Rsh= Rsk and hence Equation 4.8 becomes:
Rc 
 c Rsh
W
(4.10)
Similarly, Equation 4.9 becomes:
Lx  2LT
(4.11)
In this work, the TLM pattern consisted of a rectangular mesa and six rectangular contact pads.
The mesa dimension were 454×104 m2 with the metal contact pads of 100×50 m2
(corresponding to W and d respectively). The pad spacings were 10 m, 20 m, 30 m, 40 m
and 50 m (corresponding to L1, L2, L3, L4 and L5). A constant current (typically 1 mA) is
forced between two adjacent pads through two probes. Another set of probes are then used to
measure the voltage drop using a digital Multi Meter (DMM) allowing the total resistance
between the pads to be measured. Separate current source and DMM are preferred to a single
ohm-meter because of the relatively low impedance of the ohm meter which may give rise to
inaccuracies. The process is repeated and the total resistance is plotted on a linear graph as a
function of pad spacing.
67
4.3 XMBE#303 structure and material characterisation results
The epitaxial wafers used in these studies were grown in-house using a solid-source Molecular
Beam Epitaxy (SSMBE) in a RIBER V100 system. The epitaxial profile of a typical 4” wafer
(XMBE303) grown on a (100) GaAs semi-insulating substrate is shown in Table 4.1.
Table 4.1 – Structure of epitaxial wafer XMBE303
Layer
Cap
Supply
Spacer
Channel
Buffer
Composition
GaAs
Al0.35Ga0.65As
δ-doping
Al0.35Ga0.65As
In0.18Ga0.82As
GaAs
Thickness (Å)
50
200
50
120
6000
The pseudomorphic high electron mobility transistor (pHEMT) structure consists of a GaAs
buffer layer, a channel/active layer of strained In0.18Ga0.82As cladded by an Al0.35Ga0.65As
spacer and supply layers, a Si delta doped layer and finally a GaAs cap layer. The thicknesses
of the spacer layer and the magnitude of the delta-doped layer control the amount of charge
trapped in the Quantum Well, ns and therefore, the threshold and Transconductance of the
transistor and the sensitivity of the Hall element. In order to achieve a large Transconductance
and cut-off frequency, low noise, high Hall sensitivity and a threshold voltage of close to zero
(For elimination of negative rail from ICs), a careful epitaxial layer design was considered and
a wafer grown to satisfy all the requirements for the design of the Hall Effect ICs.
The full Hall Effect results for XMBE303 structure is shown in Table 4.2.
Table 4.2 – Hall Effect measurement results for XMBE303 structure
Temperature (K)
nH (×1012 cm-2)
µH (cm2/V×S)
nH × µH (×1016 / V×S)
Rsheet (Ω/Sq)
RT (300K)
1.57
6447
0.85
560
The term nH is the channel sheet carrier density and µH is the carrier mobility and the term
nH×µH is an important factor which determines the Transconductance of the transistor.
68
4.4 Fabrication of pHEMTs, Hall sensor and the integrated circuits
After successful growth of the material and completion of the Hall Effect measurements,
pseudomorphic high electron mobility transistors and Hall Effect sensors were fabricated.
Figure 4.9 shows the 6 process steps developed and used to fabricate the pHEMTs.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
Figure 4.9 – The fabrication steps of pHEMTs
The fabrication process was performed using a traditional optical i-line lithography and metal
lift-off. Initially the sample was cleaned using Acetone and IPA in order to remove organic
contamination and particles from wafer surface (Figure 4.9 (a)). The device active layer or
MESA isolation was defined first by wet-etching using the non-selective etchant
Orthophosphoric acid (H3PO4:H2O:H2O2) with a ratio 3:1:50 (Figure 4.9 (b)). A vertical depth
of 160 nm was etched away into the buffer layer.
Thereafter, the Ohmic contacts were formed by the thermal evaporation of AuGe, Ni, followed
by Au, which were then annealed at 420 oC in a furnace for 2-minutes, resulting in contact
resistances (RC) of < 0.15 Ω.mm (Figure 4.9 (c)). Ti/Au was then deposited using thermal
evaporation onto the pre-defined gate regions (Figure 4.9 (d)). The same metallisation scheme
was used for the probing pads (Figure 4.9 (e)) facilitating on-wafer DC and RF measurements.
Then, a 200 nm of Si3N4 was deposited on the sample using Plasma Enhanced Chemical Vapour
Deposition (PECVD) (Figure 4.9 (f)). This was achieved by mixing the gasses Silane,
69
Ammonia and Nitrogen with the ratio of 18:41:100 at 165 oC. Finally, the bridge metals were
deposited using the same process as the Gate and Bond pads Figure 22 (g). Figure 4.10 depicts
a fabricated 2 µm gate length and 2 finger 100 µm gate width pHEMT.
Source
Bridge
Drain
Gate
100 µm
Source
Figure 4.10 – A fabricated 222_2×100 µm pHEMT
The same procedure was carried out to fabricate the Hall Effect sensors and the integrated
circuits. However, in order to fabricate a single Hall sensor, only the Mesa, Ohmic and Bond
pads steps were required. Figure 4.11 shows the step by step fabrication process of a single
Hall Effect sensor.
(b)
(a)
(c)
(d)
Figure 4.11 – The fabrication steps of Hall Effect sensors
70
4.5 PHEMTs Post Fabrication Measurements
Once the pHEMTs have been successfully fabricated using the process steps explained in
section 4.4, DC and RF measurements were conducted on a 222 µm (2 µm gate length, 2 µm
gate-source spacing and 2 µm gate-drain spacing) with the gate width of 100 µm (2 finger 50
µm width). All the required measurements were conducted on the fabricated device, so that it
can be fully characterised and accurately modelled. These measurements are divided into DC
and RF categories. The DC measurements included the Schottky forward and reverse, threshold
voltage, Transconductance and IDS Vs. VDS. RF measurements were performed to determine
the cut-off and maximum frequency of operation of the pHEMT. More details regarding each
of these measurements shall be introduced in the following sections.
4.5.1 DC measurements
DC measurements were carried out at room temperature using a Cascade Ground-SignalGround (GSG) probe station with 100 μm pitch separation and a HP 4142B DC parameter
analyser.
After the Ohmic evaporation using the metals AuGe/Ni/Au (55 nm/12.5 nm/220 nm), the
samples were annealed at 420 oC for 2 minutes in order to diffuse the germanium dopants
towards the channel. This time and temperature was determined via an optimisation study to
achieve the lowest possible contact resistance, RC. A low contact resistance is an important
factor to achieve the predicted Transconductance gain, IV and RF characteristics. After the
process of heat treatment and annealing, TLM were carried out and the measured contact
resistance and 2DEG sheet resistance were 0.15 Ω.mm and 590 Ω/Sq respectively. The
degradation of the sheet resistance compared with the Hall data is due to the contact
metallisation, process variations and experimental errors. 0.15 Ω.mm of contact resistance is
approximately 70% smaller than the RC of 0.61 Ω.mm which was reported by Angeliki
Bouloukou in 2006, for a similar structure (GaAs-AlGaAs-InGaAs) with similar epitaxial
layers and thicknesses [83]. The difference is due the difference in the ratios between AuGe
and Ni thicknesses evaporated for the Ohmic contacts. The ratio of (AuGe/Ni) for the structures
mentioned above was 4.4 (55nm/12.5nm) whereas for the processed structure by Angeliki it
was around 3.8 (50nm/13nm). Note that as this ratio is higher, a better ohmic contact and
therefore, a lower contact resistance (RC) is achieved. However, it has been found that as this
ratio goes above 4.5, the morphology starts degrading. Figure 4.12 shows two images taken
from a 2×200 µm pHEMT with the AuGe/Ni ratio of 4 (a) and 5 (b) after the process of
annealing.
71
(a)
(b)
Figure 4.12 – An image of a 2×200 µm pHEMT after the annealing process with AuGe ratio
of 4 (a) and 5 (b) at the annealing temperature of 420 °C
As shown in Figure 4.12, an excellent Ohmic morphology was achieved after the process of
annealing using the ratio of 4 (AuGe/Ni).
A turn on and breakdown voltages of 0.8 V and -21 V, respectively, at a gate current of ±1
mA/mm were achieved. The high-breakdown is the result of the high band-gap of the supply
layer, which leads to a large Schottky barrier. This characteristic is excellent for designing
circuits with minimal protection. Figure 4.13 shows the Schottky forward and reverse
characteristics of the measured pHEMT. In order to avoid destroying the devices, the Schottky
reverse measurements were conducted up to a voltage of -15 V. Nevertheless, the extrapolated
data beyond the measured values results in an excellent high break down voltage of over -21
V.
72
1E-3
IGS (A/mm)
1E-4
1E-5
1E-6
1E-7
1E-8
-14
-12
-10
-8
-6
-4
-2
0
2
VGS (V)
Figure 4.13 – The normalised Schottky forward and reverse characteristics for a 2×50 µm
pHEMT
From the forward bias curve, the extracted ideality factor () and barrier height (B) were 2.2
and 0.79 eV respectively. These were determined from Equations 4.12 and 4.13, respectively.
n
Vgs
q

kT  ln I gs
(4.12)
Where ΔVGS/ΔlnIGS is the slope of forward bias linear region in natural log scale. A perfect
ideality factor would be equal to 1. An ideality factor of 1 means the electron transport
mechanism is only due to thermionic emission. Thermionic emission is described as the
transport where the electrons gain sufficient activation energy to overcome the barrier formed
in the between the metal and semiconductor in the Schottky contact.
The barrier height can also be extracted from the Schottky forward region using Equation 4.13.
B 
kT SA**T 2
ln(
)
q
IS
(4.13)
Where S is the area of schottky contact in cm-2, A** is the material dependent Richardson
constant (8.7 for GaAs), IS is the saturation current which is the Y-intercept of the linear
extrapolation from the forward bias linear region. Ideally, the larger the barrier height is, the
better the electron confinement and the leakage current and the lower that the noise would
become.
73
The threshold voltage was determined to be approximately -0.4 V from an extrapolation of the
square root of IDS versus VGS graph shown in Figure 4.14. This latter value is ideal for the
design of integrated circuits as the threshold voltage is negative and close to zero, which
eliminates the need for a negative rail in the circuit design.
0.40
0.35
Sqrt (IDS) (A/mm)
0.30
0.25
0.20
0.15
0.10
0.05
0.00
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6
VGS (V)
Figure 4.14 – The normalised threshold Voltage of the Fabricated XMBE303 2×50 µm
(normalised) pHEMT for VDS from 1 V to 2V (steps of 0.5 V)
The normalised maximum transconductance was 162 mS/mm at a Drain-Source voltage of 1
V, as shown in Figure 4.15.
0.16
0.14
Gm (S/mm)
0.12
0.10
0.08
0.06
0.04
0.02
0.00
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
VGS (V)
Figure 4.15 – Transconductance (gm) of 2×50 µm width device at VDS sweep from 1 V to 2
V (steps of 0.5 V) and VGS sweep from -0.6 V to 0.6 V, note the very small change in gm as
VDS is changed from 1V to 2V
74
The high transconductance is useful in designing high gain amplifiers, and can specifically
assist in achieving high overall sensitivities in the Hall integrated circuit. The maximum DrainSource current corresponding to the maximum transconductance and Drain-source voltage of
1 V was as high as 95 mA/mm, as depicted in Figure 4.16.
0.10
0.09
0.08
IDS (A/mm)
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.0
0.5
1.0
1.5
2.0
VDS (V)
Figure 4.16 – DC IDS vs. VDS characteristic of a 2×50 µm device where VGS is swept from 0.8 V to 0.2 V
The output conductance corresponding to the range of 1 V to 2 V Drain-Source voltage and 0.2
V Gate-Source voltage was only 0.4 mS/mm. A low output conductance is vital when pHEMTs
are used in circuits as all the transistors operate in their saturation regions. Due to the extremely
low output conductance, the overall intrinsic gain was as high as 405.
The channel carrier density and the thicknesses of the layers (especially Cap, supply and Spacer
layer) in the XMBE303 structure have been carefully engineered in such a way that high
transconductance and output current is achieved as well as a low output conductance. A
compromise had to be made as all these factors are vital in the design of the integrated circuit
since the design requirement was a low negative threshold voltage (VT).
4.1.1 RF characteristics
To complete the characterisation of the pHEMTs, RF measurements were also performed on
the devices. Microwave S-parameters (briefly discussed in Appendix A) were measured on an
Anritsu 37369A network analyser using on-wafer probing over the frequency range of 40 MHz
to 40 GHz. The current-gain cut-off frequency (ft) and maximum oscillation frequency (fmax) at
the maximum transconductance and Drain-Source voltage of 1 V were 4.8 GHz and 18.2 GHz,
75
respectively, (Figure 4.17). Note that these values are comparable to 0.5 µm gate length NMOS
[84].
40
Gain (dB)
30
fT
fmax
20
10
0
1E8
1E9
1E10
Frequency (Hz)
Figure 4.17 – Cut off frequency and maximum frequency at Gm maximum and VDS = 1 V
High cut-off and maximum frequencies would allow designing integrated circuits with
adequate bandwidths. This specifically aids in enhancing current commercial Hall linear IC
technology whose frequency bandwidth are at most a few 10s of kHz [9-11].
4.6 Transistor DC and RF modelling
Prior to the design of the integrated circuits, transistor modelling was required to extract all the
DC and RF parameters needed for an accurate and functional circuit. The modelling of the
processed pHEMTs was performed using Advanced Design System (ADS) software [12]. The
transistor modelling began with the extraction of linear (small model) parameters based on the
measured DC and RF characteristics of the pHEMT. The Linear parameters are then used in a
large signal model, which includes the nonlinear behaviour of the transistor.
4.6.1 Linear modelling
The linear model consists only of linear elements known as intrinsic and extrinsic elements,
and is based on the measured S-parameters of the device. The physical origin of the
pHEMT/HEMT linear equivalent circuit model and the equivalent circuit model are depicted
in Figure 4.18.
The model can be divided into two parts of Extrinsic elements (bias-independent) and Intrinsic
elements (bias-dependents).
76
(a)
(b)
Figure 4.18 – The schematic cross-section diagram of a pHEMT (a) [85] and the linear
small-signal equivalent circuit of pHEMT (b)
The eight extrinsic elements (Rs, Rd, Rg, Ls, Ld, Lg, Cpd, and Cpg) and seven intrinsic elements
(gm, Ri, τ, gds, Cds, Cgs, and Cgd) in this model are extracted for a 222_2×50 µm device and
presented in Tables Table 4.3 and Table 4.4. Note that the intrinsic modelling was carried out
at the 50%, 85% and 100% of Gmmax (1 V of VDS) in order to cover the entire bias range.
Table 4.3 – The final extrinsic parameters for XMBE303 and the 222_2×50 device
CPG (fF)
CPD (fF)
Rs (Ω)
Rg (Ω)
Rd (Ω)
Ls (pH)
Lg (pH)
Ld (pH)
2.85
6.9
5.6
8.4
30.2
22
306
39
Table 4.4 – The final intrinsic parameters for XMBE303 and the 222_2×50 device
VDS (V)
1V
% of
Gm
Gmmax
(mS)
50%
CGS
CDS
CGD
(pF)
(pF)
(fF)
3000
0.5
0.01
0.03
6.6
2900
0.47
0.01
0.025
3.66
2838
0.48
0.01
0.025
T (psec)
Ri (Ω)
RDS (Ω)
9.74
4.16
7.8
85%
14.35
5.8
100%
17
5.8
4.1.2 Non-linear modelling
An accurate nonlinear or large signal model of a transistor is vital for the design of integrated
circuits. Therefore, there is a continuous effort from circuit designers to produce efficient
nonlinear models [86]. There are several CAD packages available for non-Linear modelling
77
[87], depending upon on the applications. The model used in this work was developed by
Agilent, EE-HEMT model in Advance Design System (ADS) [88]. The EE-HEMT is an
empirical analytic model based on fitting of the measured DC and RF electrical curves of
HEMTs. The extracted parameters from the linear model were used here.
Figure 4.19 and Figure 4.20 illustrate the excellent fit between the simulated and measured
current-voltage (I-V) and RF characteristics of a 1×50 µm pHEMT, respectively.
0.005
Modelled
Measured
Id_msr
IDS (A)A
IDS.i,
0.004
0.003
0.002
0.001
-0.000
0.0
0.3
0.5
0.8
1.0
1.3
VVDS
DS (V)
Vds
1.5
1.8
2.0
20
2
2
0
0
0
-2
-20
-2
-4
-40
-4
-6
-6
-60
-8
-8
-80
-10
0 5 10 15 20 25 30 35 40
0 5 10 15-10
20 25 30 35 40
0 5 10 15 20 25 30 35 40
5 10 15 20 25 30 35 40
freq, GHz Frequency (GHz)
Frequency0(GHz)
freq, GHz
freq, GHz
freq, GHz
S22, S11 (dB)
dB(S2_30(2,2))
dB(S(18,18))
dB(S2_30(1,1))
dB(S(17,17))
S21 (Mod)
S12 (Meas)
S21 (Meas)
S12 (Mod)
dB(S2_30(2,2))
dB(S(18,18))
dB(S2_30(1,1))
dB(S(17,17))
20
0
-20
-40
-60
-80
dB(S15_30(1,2))
dB(S(9,10))
dB(S15_30(2,1))
S12 (dB)
S21,
dB(S(12,11))
dB(S15_30(1,2))
dB(S(9,10))
dB(S15_30(2,1))
dB(S(12,11))
Figure 4.19 – DC modelling (IV curve) for a 2 µm length, 1×50 µm width device as VGS is
swept from -0.8 V to 0.2 V
S22 (Mod)
S11 (Meas)
S22 (Meas)
S11 (Mod)
Figure 4.20 – RF modelling (S parameters) in the frequency range from 40 MHz to 40 GHz
Once an excellent fit was achieved between the modelled and the measured DC and RF curves,
the full model including all the EE-HEMT parameters was extracted. The complete model is
depicted in Figure 4.21.
78
Figure 4.21 – The full model of the XMBE303 222_2×50 µm pHEMT extracted from ADS
This model was used in the design of the Hall Effect integrated circuit.
4.7 Hall Effect sensor characterisations
The Hall Effect sensors were fabricated on the XMBE303 structure discussed previously.
Figure 4.22 illustrates the top view of the Greek cross sensor developed in this work.
Figure 4.22 – Top view of the XMBE303 Greek cross Hall sensor
The fabricated device was fully symmetrical and thus input and output resistance were the same
(~1750 Ω). The fabricated sensor had an (L/W) ratio of 3 with L = 60 µm and a sensitivity of
0.4 mV/mA.mT that was capable of detecting magnetic fields as low as 10 nT (with
amplification of 40 K (~92 dB) using off-chip components). The characteristics of the Hall
sensors are shown in Table 4.5.
79
Table 4.5 – XMBE303 Hall sensor characteristics
Parameters
Dimension (L/W)
Input resistance
Output resistance
Current sensitivity
Current sensitivity drift
over temperature
Resistance drift over
temperature
Power consumption at
Vin = 1 V
Maximum magnetic DC
offset at Vin = 1 V
XMBE303
Hall Sensor
60/20
1750
1750
0.4
-0.08
Units
µm
Ω
Ω
mV/mA.mT
%/°C
0.3
%/°C
0.57
mW
0.35
mT
As shown in Table 4.5, a temperature coefficient of the Hall voltage (TC) of approximately
−0.08 %/°C was achieved from room temperature to approximately 200 °C, which is
comparable to bulk GaAs and an improvement in comparison to similar type of devices [8991]. The Hall sensor was shown to have a maximum magnetic DC offset of 0.35 mT at 1 V of
input bias (measurement were performed on over 50 sensors). This would not be an issue if the
sensor is used as part of an AC Hall integrated circuit as any DC offset can be removed using
a capacitor. However, For DC applications this offset would be considered as a limitation to
the minimum field value that can be measured and thus circuit techniques to cancel would be
needed.
4.7.1 Offset reduction technique
The large offset voltage of the Hall sensor is the principal obstacle when used for low DC field
measurements. This offset also limits the amount of gain in the DC integrated circuit since
these would quickly saturate. The origin of this offset is mainly due to geometrical errors in
mask alignments, mechanical stress and strain, non-uniform temperature distribution and heat
dissipation in the substrate etc [92]. In DC applications, it is not possible to entirely remove
this offset; however, various techniques are employed in order to reduce this offset [93-97].
The technique used in this work is to connect two (closely located) Hall sensors in parallel. In
this technique, the current flows in one Hall sensor in one direction and it flows in the other
Hall sensor in the opposite direction, so assuming their offset voltages are equal in magnitude
(matched pairs) and direction, their output offset voltages compensate for each other. The
80
configuration of the parallel Hall sensors is depicted in Figure 4.23, with test results in Figure
4.24. Since the two devices are connected in parallel, the total resistance is half of a single Hall
sensor and the sensitivity is also halved.
(a)
(b)
Figure 4.23 – The connection configuration of a parallel Hall sensor (a), proposed design in
this work (b)
Figure 4.24 shows the output offset voltage generated from a parallel Hall sensor in comparison
with an offset result of a single Hall sensor, both biased at 1 V.
90
Output offset (µV)
80
70
60
50
Single Hall sensor
Parallel Hall sensor
40
30
20
10
10
20
30
40
50
60
Time (S)
Figure 4.24 – Offset results of XMBE303 parallel and single Hall sensors at 1 V across each
device
81
As shown in Figure 4.24, the offset of the single Hall sensors was approximately 81 µV and
the one generated from parallel Hall sensors was around 21 µV. These are proportional to
approximately 0.35 mT and 0.092 mT of magnetic field, respectively. These measurements
were conducted on 30 parallel and 30 single Hall sensors. The average of the mean offset
voltages using the parallel technique enabled the maximum total offset to be reduced by
approximately 76%. This is mainly due to the fact that the two closely placed Hall sensors on
the wafer have similar values for offset and connecting them in parallel reduces the total offset
extensively.
4.8 Summary
In this chapter, the epitaxial layer of the GaAs/InGaAs/AlGaAs XMBE303 structure was
described. The development process of the Hall Effect integrated circuit, the measurement
techniques and specifically the importance of the transistor (pHEMT) fabrication and
modelling and characterisation of the Hall Effect sensor were discussed in details. Through a
careful growth and band-gap engineering, the fabricated pHEMTs showed a threshold voltage
of ~-0.40 V, overall intrinsic gain of 405 and a current gain cut-off frequency of 4.8 GHz. The
small threshold voltage eliminates the need for a negative rail in the circuit design and assist in
designing sensitive Hall Effect integrated circuits.
The transistor modelling were explained and excellent fits were achieved between the modelled
and measured curves for both DC and RF data leading to a complete model including all the
required parameters for the design of the integrated circuits.
The 2DEG Hall Effect sensor developed and characterised in this work, is shown to have a
current sensitivity of 0.4 mV/mA.mT, input/output resistance of 1750 Ω and a maximum DC
offset of 0.35 mT at 1 V of input voltage. This maximum offset was reduced by 76% when a
parallel Hall sensor technique was employed.
82
5
DC digital (Unipolar)/Linear GaAs 2DEG Hall Effect Integrated
Circuits
5.1 Introduction
DC Hall Effect integrated circuits, presently dominated by silicon technology are widely
employed in automotive and consumer industries and almost wherever DC magnetic sensing
and switching is required. In these applications, a Hall sensor is used as part of a larger circuit
in order to detect low DC magnetic fields and to provide a linear/digital output to verify the
detection of the magnetic field. By integrating the sensing element onto the same silicon chip
as its control logic and interface circuitry, companies such as Melexis, Honeywell and Allegro
have produced sensor chips with different degrees of intelligence to suit a vast array of
applications. These silicon ICs have the advantages of low cost, small dimension and
compatibility with CMOS technology, [98-101] but, suffer from poor sensitivity.
At present, the most sensitive commercial Si DC linear Hall integrated circuits are made by
Allegro (A1324), Melexis (MLX90242) and Honeywell (SS39ET). These have sensitivities of
50 mV/mT, 39 mV/mT and 14 mV/mT and power consumptions of 34.5 mW, 12.5 mW and
30 mW (at 5 V supply) respectively. The most sensitive commercial Si digital (unipolar) Hall
integrated circuits are made by Melexis (US5782), Honeywell (SS345PT) and Allegro (A1101)
[102-104] with switching threshold sensitivity of 12 mT, 18 mT and 10 mT respectively.
In this work, counterpart low power GaAs-InGaAs-AlGaAs (XMBE303) monolithic DC linear
and digital (unipolar) Hall Effect integrated circuits with high sensitivity characteristics have
been fully designed, fabricated, tested and developed. In the development process of these ICs,
firstly, the IC’s overall design was divided into sub-circuits. These sub-circuits were
individually designed and simulated using the modelled transistors and then fabricated and
tested in the clean room. After successful development of these sub-circuits, they were then
combined to form the DC linear and digital (unipolar) Hall Effect ICs. The entire integrated
circuits are based on 2 µm gate length transistors. The design, simulation and performance
results of these circuits and the ICs are detailed in this chapter.
83
5.2 The DC digital (unipolar) Hall Effect sub-circuits
Figure 5.1 shows the block diagram of the 2DEG DC unipolar Hall Effect integrated circuit.
Figure 5.1 – The block diagram configuration of the Hall IC circuits
The DC unipolar Hall Effect integrated circuit was divided into four sub-circuits, consisting of
a current source, a differential amplifier, a comparator and a source follower. The current
source circuit generated a constant current of 500 µA to the Hall sensor. The amplifier
differentiated the two signals generated from the Hall sensor (V+ and V-) and then amplified
the difference using a gain of 40. The comparator circuit switches status based on the
amplifier’s output and the reference voltage. This reference voltage determined the magnetic
field switching point of the integrated circuit. Finally, a source follower was used as the final
stage of the integrated circuit to provide the output of the comparator (either 0 or 1 V) to the
outside world. Note that the digital IC designed in this work is unipolar, meaning that it only
operates (output high or low) when exposed to one of the magnetic poles and all the
comparisons in this chapter have been made with unipolar commercial Hall ICs.
The following sections give a brief discussion about each of the sub-circuits.
5.2.1 Integrated GaAs current source
The current source circuit was designed to generate a constant current of 500 µA to the Hall
sensor. The following points were considered when designing this circuit:
1. The circuit was to have large stability over variations of supply voltage, i.e. ±500 mV
2. ± 0.1 V variation of threshold voltage (worst case) from process to process should have the
least effect possible on the performance of the current source.
84
Figure 5.2 illustrates the configuration of the GaAs integrated current source circuit in the
simulation and after fabrication.
VDD = 5V
D3
I1
D4
D5
R = 6.8
KΩ
VA
IO
D1
D2
Hall
sensor
Vc
VO
P1 (1×100 µm)
V1
P3 (1×100 µm)
P2 (1×100 µm)
(a)
(b)
Figure 5.2 – The configuration of the GaAs integrated current source circuit in the simulation
(a) [105] and after fabrication (b) – Dimension = 670 × 770 µm2
As shown in Figure 5.2, the current source circuit consisted of three pHEMTs with width
dimensions of 100 µm, a semiconductor resistor with a value of 6.8 kΩ and 5 diodes (made of
one Schottky and one ohmic terminals) with a width of 400 µm (D1 to D5). For simplicity, the
semiconductor (2DEG) was used to make the resistors in the integrated circuit. As the sheet
resistance for the fabricated devices (from run to run) was consistent (within ±2%), the obtained
resistor values were also very consistent. These resistor values are determined from their length
to width ratio, with their widths being 10 µm in this work. VC is the voltage dropped across
each diode which in this case was approximately 0.7 V to 0.8 V. Diodes D 1 and D2 were used
in order to maintain P1 in the saturation region. Diodes D1, D2 and D3 were employed here in
order to lower the supply voltage from 5 V to 2.9 V where the pHEMT output conductance
was as low as 0.4 mS/mm.
In the circuit shown in Figure 5.2, the source-gate connected current source pHEMT, P1, is
saturated, because:
VGS  0 , VT  0.4 V  VGS  VT  0.4 V (1)
VDS  VA  V1  2VC  V1  2  (0.7)  V1  1.4 V  VDS  V1  1.4 V (2)
From (1) and (2)  VDS  VGS  VT  P1 is saturated
The drain-gate connected reference pHEMT, P2, is unsaturated, because:
85
VDS  VGS  V1
As VT has a negative value (-0.4 V)  VDS  VGS  VT  P2 is unsaturated
In this circuit, P2 and P3 form a current mirror. Therefore, I O  I1 is realised if P3 is saturated.
As VGS  V1 & VDS  VO
P3 is saturated, if VO  V1  VT .
As VT  0.4 V  VO  V1  0.4 V
V1 was measured (in simulation) to be 0.27 V  P3 is saturated, if VO  (0.27  0.4  0.67) V.
Thus, I O  I1 applies, if VO  0.67 V. In this case VO is:
VO  VDD  3VC  VHall _ Sensor  5  (3  0.7)  ( I  RHall _ Sensor )
 5  2.1  (1mA  1.75K)  1.15V
And hence 1.15 V > 0.67 V.
The reference current I 1 which is equal to I O is expressed in the following manner:
I1  I O  (VDD  2VC  V1 ) / R  (5  1.4  0.27) /(6.8  103 )  0.5mA
The current I 1 , which is equal to I O , becomes almost independent of VT , if V1 is much smaller
than (VDD  2VC ) [105]. This is the case in this design, Since V1  0.27 V and
(VDD  2VC )  5  1.4  3.6 V.
According to [105], this circuit was shown to only have 4% of variation in the generated current
for 0.2 V of changes in the threshold voltage. Furthermore, only 3% reduction in the generated
current was monitored when the temperature was varied from 25 °C to 100 °C. Thus the overall
temperature coefficient was found to be as small as 0.04%/°C [105].
The current source circuit was fabricated and tested over 28 runs and showed excellent stability
with the maximum variation of ±2% from run to run. This was despite the fact that the threshold
voltage of pHEMTs showed ±0.1 V variation (worst case) from run to run.
Since the Hall sensor’s current sensitivity is 0.4 mV/mA.mT and the current to the Hall sensor
in this circuit is 500 µA, the Hall sensor’s overall sensitivity is then 0.2 mV/mT. This produces
an overall power consumption for this circuit of 5 mW (5 V × (IO + I1) = 5 V × 2 × 0.5 mA).
86
The full characteristics of the GaAs-InGaAs-AlGaAs current source integrated circuit are
tabulated in Table 5.1.
Table 5.1 – Characteristics of the GaAs integrated current source circuit
Constant current value
500 µA
Maximum variations monitored over ±0.1 V
±2%
of changes in the threshold voltage
Temperature coefficient [105]
0.04%/°C
Overall power consumption
5 mW
As can be seen in Table 5.1, the outcome of this circuit is a constant current source with
excellent stability over changes of threshold voltage and temperature.
5.2.2 Integrated GaAs differential amplifier
A differential amplifier circuit was designed in order to amplify the signals generated from the
Hall sensor. The configuration of the differential amplifier, consisting of a differential pair (P 1
and P2) and three resistors (R1, R2 and R3), is depicted in Figure 5.3.
ISS
P2 (222_4×100 µm)
P1 (222_4×100µm)
Figure 5.3 – The configuration of the differential amplifier circuit
The differential pair of transistors (P1 and P2) uses a gate width of 400 µm (4 finger × 100 µm)
and resistor values of 12 kΩ (R1 and R2) and 10 kΩ (R3) were selected. The inputs to the circuit
87
were the gates of P1 and P2 and the output of the circuit was taken from the drain of P 1. If no
DC magnetic field is applied, the Hall sensor’s outputs (inputs of the amplifier) both positive
and negative would equally be:
V+ = V- = (0.5 × I × Rin) + VCS
(5.1)
Where VCS is the voltage dropped across the transistor (P3) in the current source circuit
discussed in section 5.2.1. In this case, the current to the Hall sensor (I) is 500 µA, the Hall
sensor’s input resistance (Rin) is 1.75 kΩ and VCS is 1.6 V (from simulation of the current
source circuit). From Equation 5.1, the Hall sensor’s outputs (inputs of the amplifier) DC
voltage, in the absence of a magnetic field, was calculated to be 2.3 V.
Since no negative rail was used in this circuit, the amplifier’s output is the DC voltage midrange between ground and VDD (5 V). The output DC level of the differential amplifier can
thus be determined from Equation 5.2.
Vout  VDD  (( I SS / 2)  R1 )
(5.2)
Where R1 is 12 kΩ, VDD is the supply voltage to the circuit (5 V) and I SS is the total current to
the circuit. The total current of the circuit can be determined from Equation 5.3.
I SS  VDD /(( 2  ( R1 || RP1 ))  R3 )
(5.3)
The gain of the differential amplifier can be calculated from Equation 5.4.
AV | Gm ( P1)  R1 |
(5.4)
Where Gm(P1) is the transconductance of P1.
The differential amplifier circuit was simulated in ADS. In the simulation, two external DC
sources, representing the Hall sensor’s outputs, with DC level of 2.3 V and a voltage sweep of
±8 mV (proportional to ±40 mT of magnetic field since the Hall sensor’s sensitivity is 0.2
mV/mT) were connected to the inputs of the amplifier. Figure 5.4 shows the simulation results
of this circuit for two input DC sweep of 2.3 V to 2.308 V (V+) and 2.3 V to 2.292 V (V-). The
input shown in Figure 5.4 is the difference between the two inputs (V+ - V-).
88
3.9
3.8
Output (V)
3.7
3.6
3.5
3.4
3.3
3.2
3.1
0
2
4
6
8
10
12
14
16
Input (mV)
Figure 5.4 – The simulated output of the differential amplifier for 16 mV of ΔVin
This circuit is shown to have a gain of 40, and power consumption as low as 1.35 mW (270
µA × 5 V). As shown in Figure 5.4, the amplifier’s DC level is 3.18 V for an input of zero
(+2.3 V – 2.3 V).
Following this design and simulation, the differential amplifier circuit was fabricated in the
clean room. The layout of this circuit is depicted in Figure 5.5.
(a)
(b)
Figure 5.5 – The mask layout (a) and fabricated version (b) of the integrated GaAs
differential amplifier circuit – Dimension = 880 × 630 µm2
Measurements were performed on 5 circuits. These circuits were biased in exactly the same
manner as in the simulation (using two external DC sources). The measurement results are
89
depicted in Figure 5.6. This figure also compares the measurement results with the simulation
results.
3.9
3.8
3.7
Output (V)
3.6
3.5
3.4
3.3
Simulation
Measured_circuit 1
Measured_circuit 2
Measured_circuit 3
Measured_circuit 4
Measured_circuit 5
3.2
3.1
3.0
2.9
0
2
4
6
8
10
12
14
16
Input (mV)
Figure 5.6 – Measurement Vs simulation results of the integrated DC differential amplifier
circuit
It is apparent from Figure 5.6 that the measurements results closely follow the simulation with
±2.5% deviation in gain (slope - worst case) with up to 0.26 V of difference between the
measured and simulated output DC level. Furthermore, ± 40 mV of variations on the output
DC level from circuit to circuit can be noticed. This variation is due to growth and/or
fabrication errors. It was important to design a circuit whose output DC level in the absence of
magnetic field (B = 0) stays as constant and consistent as possible from circuit to circuit. This
is vital since the comparator circuit would be switching on the level of this signal. However, ±
40 mV of variation is considered small in this case, where up to 600 mV of variations in DC
output voltage form circuit to circuit was measured when active differential amplifier design
(using transistors instead of resistors) was considered and tested initially. The active differential
amplifier circuit was disregarded for this reason.
The outcome was thus a fully operating GaAs-InGaAs-AlGaAs integrated differential
amplifier circuit with a gain of 40 and a power consumption as low as 1.35 mW.
90
5.2.3 Integrated GaAs comparator
An integrated comparator circuit was designed in order to convert the linear output of the
amplifier to a digital signal. This is simply a differential amplifier with high gain so that a small
difference between the two inputs leads to saturation of the output to one of the power rails
(VDD or ground). The two main factors that are vital in designing comparators are the
bandwidth and the gain. However, in this case, since the application is DC, only the gain was
considered. A larger gain would decrease the comparator’s switching propagation delay and
thus increase the switching speed.
To be best of the author’s knowledge, four designs of comparators based on III-V have been
reported in the literature. These are summarised in Table 5.2.
Table 5.2 – Summary of voltage comparator related circuit performance in different material
systems
Reference
Year
Technology
[106]
1991
GaAs MESFET
[107]
1994
[108]
2004
[109]
2010
This work
2014
AlGaAs/GaAs
HBT
AlGaN-GaN
HEMT
AlGaN-GaN
HEMT
GaAs-InGaAsAlGaAs HEMT
Circuit
Passive load
comparator
2 stage
comparator
Cascode
comparator
Active load
comparator
Active load
comparator
Gain (dB)
9.5
49.5
50
35
(27.1 in DC)
47
As shown in Table 5.2, in [107] and [108], the highest gain comparators with overall gains of
49.5 dB and 50 dB were reported. However, these were achieved using double stages of
amplifications where the power consumption and circuit area are greatly increased. Although,
the comparator circuits reported in [106] and [109] are both single stage circuits, owing to the
use of active loads in [109], almost a multiple of 4 higher gain has been reported. This is
because higher resistance are easier to achieve using active loads than passive loads.
In this work, a single stage active comparator, depicted in Figure 5.7 has been designed and
fabricated.
91
P4 (222_1×10 µm)
P3 (222_1×10 µm)
Output
P1 (222_4×50µm)
P2 (222_4×50 µm)
P5 (222_1×20 µm)
Figure 5.7 – The configuration of the comparator circuit in simulation
This circuit consisted of 5 pHEMTs (Figure 5.7) with P1 and P2 forming a differential pair
having gate widths of 4×50 µm, P3 and P4 forming a saturated pair with gate widths of 1×10
µm and P5 acting as a saturated (active load) with a gate width of 1×20 µm. Two resistors (R1
and R2) with values of 12 kΩ and 3 kΩ were also used as a potential divider in order to set the
reference voltage in this circuit. The obtained reference voltage was 1 V and connected to the
gate of P1. The other input (signal) was connected to the gate of P 2. If the signal (DC) was
larger than 1 V, the comparator’s output would be low and, if the output was less than 1 V,
then, the output would be high. The gain of this comparator circuit can be determined from
Equation 5.5.
AV 
Gm2  RO
2
(5.5)
Where, Gm2 is the transconductance of P2, RO is the parallel drain-source resistance of P2 and
P4 (RDS2 || RDS4). As shown above, the overall gain of the comparator is directly proportional
92
to the transconductance of pHEMT 2 (where the input signal is connected). For this reason
transistors with large gate widths (4 × 50 µm = 200 µm) were chosen for P1 and P2 in order to
achieve a relatively high gain. Furthermore, the overall gain is inversely proportional to the
transconductance of P4. Therefore, only 1 finger, 10 µm width devices were selected for P3 and
P4 .
The reason the reference voltage was set to 1 V is that, at this voltage the differential pair (P 1
and P2) would approximately be operating at the maximum transconductance (G m.max). Thus,
the circuit show the highest gain and switching speed at this voltage.
In the simulation, the input signal was swept from 0.5 V to 1.5 V and the reference voltage was
set to 1 V using R1 and R2. The obtained simulated output is illustrated in Figure 5.8.
5.0
4.5
Output (V)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
Input (V)
Figure 5.8 – The simulated output of the comparator for a reference voltage of 1 V and input
sweep of 0.5 to 1.5 V
As can be seen from Figure 5.8, the integrated GaAs comparator successfully switched at 1 V.
In this case, when the input signal is below 1 V (the reference point), the output stays high
(4.65 V) and when the input is equal or greater than 1 V, the output switches low (1.25 V)
immediately. The high output is VDD – VP4 and the low output is V P2 + VP5. From the
simulation, the GaAs comparator gain was found to be 216 (~47 dB). This is the highest gain
93
reported to date compared to other single stage III-V comparator circuits reported in the
literature [106-109].
The GaAs integrated comparator circuit was subsequently fabricated in the clean room. The
mask layout and fabricated version of this IC are depicted in Figure 5.9.
(a)
(b)
Figure 5.9 – The mask layout (a) and fabricated version (b) of the GaAs integrated
comparator circuit – Dimension = 580 × 575 µm2
In order to perform tests on this circuit, an external voltage sweep from 0.5 V to 1.5 V was
generated to the input of the comparator. The reference input was set to 1 V using the two
integrated resistors (R1 and R2). Figure 5.10 compares the measurement results of two
comparator circuits with the simulation results.
94
5.0
4.5
4.0
Output (V)
3.5
3.0
2.5
2.0
1.5
Simulation
Measured_circuit 1
Measured_circuit 2
1.0
0.5
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
Input (V)
Figure 5.10 – Performance of the Integrated GaAs comparator circuits
As is apparent from Figure 5.10, the measurement results closely follow the simulation results.
Both measured circuits were shown to have the same gain and switching speed as the
simulation with only ±4% deviation. The low state for the measured circuits were
approximately 150 mV lower than what was achieved in the simulation (~1.05 V in the
measurements compared to ~1.2 V in the simulation). This discrepancy is due to the slight
difference between the threshold voltage of the transistors in simulation and fabrication and
the fact that the ground in the measurement setup had a small offset (up to ~20 mV). However,
this should not have any effect on the overall performance of the digital Hall integrated circuit
as this deviation is taken into account in the design of the source follower. The performance of
the source follower shall be discussed in the following section. This GaAs comparator circuit
is also demonstrated to consume power as low as 4.25 mW (850 µA × 5 V).
The outcome of this work was thus a fully operating single stage GaAs-InGaAs-AlGaAs
comparator circuit with an outstanding gain of 216 (47 dB) and a power consumption of 4.25
mW.
5.2.4 Integrated GaAs level shifter
Since the output DC level of the differential amplifier was approximately 3 V and the
comparator circuit was designed to operate at a reference level of around 1 V, a level shifter
95
circuit was designed in order to decrease the amplifier’s output by 2 V. Figure 5.11 shows the
configuration of the level shifter circuit.
Input
P1 (222_1×10 µm)
D1 (100 µm)
D2 (100 µm)
Output
P2 (222_1×10µm)
Figure 5.11 – The circuit diagram of the level shifter
As shown in Figure 5.11, the level shifter circuit consists of two pHEMTs (P1 and P2) with
width dimensions of 1×10 µm and two diodes (D1 and D2) with width of 100 µm. The input is
connected to the gate of P1 and the output taken from the drain of P2. The two pHEMTs operate
as a unity gain buffer and the two diodes reduce the level of the input voltage.
The level shifter circuit was simulated in ADS with an input sweep of 2.9 V to 3.1 V. Figure
5.12 depicts the output generated from this circuit for this input range.
96
1.10
Output (V)
1.05
1.00
0.95
0.90
0.85
2.90
2.95
3.00
3.05
3.10
Input (V)
Figure 5.12 – The output of the level shifter integrated circuit in simulation for the input
range of 2.9 V to 3.1 V
As shown above, the level shifter circuit reduced the input level (linearly) by 2 V
approximately. This circuit would also provide a high impedance and isolation path between
the amplifier and the comparator circuits. The total power consumption of this circuit is 1.29
mW (258 µA × 5 V).
Since the layout and operation of this circuit was very similar to the source follower circuit (the
final stage of the IC), the fabrication and measurements were only conducted on the source
follower circuit. This is discussed in more details in the next section.
5.2.5 Integrated GaAs source follower
A source follower or buffer is a unity gain amplifier which is normally used to provide a high
impedance path between two circuits. In the application of the digital Hall Effect IC, it was
necessary to use a buffer as the final stage because of the two following reasons:
1. To ensure the operation of the comparator remains unaffected when providing a path to
the outside world
2. To reduce the 1 V comparator low voltage to zero using diodes.
Figure 5.13 shows the layout of the source follower circuit.
97
Input
P1 (222_2×200 µm)
D1 (300 µm)
D2 (300 µm)
D3 (300 µm)
Output
P2 (222_1×25µm)
Figure 5.13 – The layout of the source follower
As shown in Figure 5.13, the integrated GaAs source follower circuit consists of two pHEMTs
with width dimensions of 2×200 µm (P1) and 1×25 µm (P2), and three diodes with width of
300 µm (D1, D2 and D3). The input to source follower circuit is the gate of P1 and the output is
taken from the drain of P2.
In simulation, this circuit was tested using input voltage sweep of 0 to 5 V. Figure 5.14
illustrates the test results of the source follower in simulation.
98
2.25
2.00
1.75
Output (V)
1.50
1.25
1.00
0.75
0.50
0.25
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input (V)
Figure 5.14 – The performance of the integrated GaAs source follower in simulation
As can be seen from Figure 5.14, for any input below 2.25 V, the output is approximately zero.
Thus, the 0.2 V variations in the low output of the comparator (between 1 V to 1.2 V) does not
have any noticeable effect on the final output of the digital Hall IC. This circuit will reduce the
comparator’s output voltages (low and high) from 1 V to 0 V and from 4.6 V to approximately
1 V. Figure 5.15 depicts the layout of the GaAs integrated source follower circuit on the mask
(a) and after fabrication (b).
99
(a)
(b)
Figure 5.15 – The mask layout (a) and fabricated version (b) of the GaAs integrated source
follower circuit – Dimension = 1 × 0.415 mm2
Figure 5.16 compares the measurement and simulation results of two experimental source
follower circuits.
2.25
2.00
1.75
Output (V)
1.50
1.25
Simulation
Measurement_circuit 1
Measurement_circuit 2
1.00
0.75
0.50
0.25
0.00
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input (V)
Figure 5.16 – The performance of the integrated source follower circuits and comparison
with the simulation results
100
As shown in Figure 5.16, the measurement data closely agree with the simulation results. The
total power consumption of the source follower circuit is 3.35 mW (670 µA × 5 V).
5.3 Mask design
The details of how each sub-circuits were designed, simulated, fabricated and tested were
highlighted previously. They were all showed to operate successfully and closely following the
simulation predictions. These sub-circuits were then put together to form the first reported DC
digital (unipolar) Hall Effect integrated circuit based on 2DEG GaAs-InGaAs-AlGaAs
technology. The configuration of the entire IC is depicted in Figure 5.17.
Figure 5.17 – Configuration of the entire 2DEG GaAs-InGaAs-AlGaAs DC digital Hall
Effect IC
The GaAs-InGaAs-AlGaAs unipolar Hall Effect IC, shown in Figure 5.17, consisted of 14
transistors, 10 diodes, 6 resistors and the Hall Effect sensor. The graphical representation of
each layer mask is illustrated in Figure 5.18. These layers are the Mesa, Ohmic, gate, bond
pads, via and bridge steps.
101
Mask 1 – Mesa
Mask 2 – Ohmic
Mask 4 – Gate
Mask 3 – Bond-pads
102
Mask 5 – Via
Mask 6 – Bridge (Full IC)
Figure 5.18 – The mask layers of the GaAs 2DEG digital Hall Effect IC
The fabrication process of each layer has previously been discussed in section 4.4. The final
IC with a dimension of 1 × 1.1 mm required only three large pads for ground, output and V DD.
These three pads had sizes of at least 90 µm2 to provide adequate tolerance for bonding.
5.4 Magnetic measurements and analysis
The fabricated 2DEG GaAs-InGaAs-AlGaAs integrated circuit can be considered as two
separate ICs:
1. A DC linear Hall Effect IC comprising of the current source, Hall sensor and the
differential amplifier circuit.
2. A Full DC digital unipolar Hall Effect IC comprising of the current source, Hall sensor,
differential amplifier, level shifter, comparator and the source follower.
Magnetic measurements were performed on both of these ICs and their results are presented
here.
5.4.1 GaAs DC linear Hall Effect integrated circuit
The DC linear Hall Effect IC consists of the current source, with a constant current of 0.5 mA,
a Hall sensor with a current sensitivity of 0.4 mV/mA.mT and a differential amplifier with a
gain of 40. This yields an overall IC sensitivity of 8 mV/mT. The fabricated IC is illustrated in
Figure 5.19.
103
Figure 5.19 – The DC linear Hall Effect IC after fabrication
In order to perform magnetic measurements on this IC, a DC magnetic field of 50 mT was
generated using a coil. A power supply was used to control the magnitude of the coil current
(to generate 50 mT) in-between the poles. The created magnetic field was accurately measured
using a Hirst GM08 Gauss meter [110]. The bonded integrated circuit was placed in the coil,
powered up using a 5 V battery and the output was measured using a DMM. Figure 5.20 depicts
the full setup used to perform magnetic measurements on the DC linear Hall Effect IC.
IC
Hirst magnetic
meter
Coil
DMM
Power supply
Figure 5.20 – The full measurement setup to perform DC magnetic field measurements on
the ICs
104
The field to the coil was turned on and off in intervals of 5 seconds. Figure 5.21 illustrates the
generated output of the IC in this experiment.
3.40
3.35
Amplifier's output (V)
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
0
5
10
15
20
25
30
Time (Second)
Figure 5.21 – The output of the DC linear Hall Effect integrated circuit
As can be seen from Figure 5.21, the IC’s output was 2.96 V with no field applied. This agrees
quite well with what was previously seen from the behaviour of the amplifier’s circuit. When
the magnetic field was applied, the output of the IC increased to 3.35 V. Thus 390 mV change
(3.35 V – 2.96 V) in the output was recorded for a field of 50 mT. According to this experiment,
the measured circuit sensitivity is 7.8 mV/mT (390 mV/50 mT), which is very close to the
expected 8 mV/mT. The total power consumption of the DC linear Hall Effect IC is 6.35 mW
(total of the current source and amplifier circuit).
Commercial vendors such as Allegro, Melexis and Honeywell produce DC linear Hall Effect
ICs based on silicon technology. These ICs include the Si Hall element and multiple
amplifications stages to reach high sensitivities and the use of current spinning techniques to
reduce both the sensor’s DC offset and its noise. Table 5.3 tabulates the sensitivity and power
consumption of these products and compares them with what has been achieved in this work.
105
Table 5.3 – Comparison between the 2DEG GaAs DC linear Hall Effect IC and the silicon
DC linear ICs made by Allegro, Melexis and Honeywell
Product (supplier)
Allegro (A1324)
Melexis (MLX90242)
Honeywell (SS39ET)
2DEG GaAs DC Linear IC
(This Work)
Sensitivity (mV/mT)
50
39
14
Power consumption (mW)
30
34.5
12.5
8
6.35
The sensitivities achieved by the commercial silicon ICs are higher than those achieved in this
work; however, this is at the expense of much higher power consumptions. One of the main
aims of this work was to keep the power consumption as low as possible. If the current source
circuit was designed in such way that a higher current was generated to the Hall sensor, a higher
total sensitivity would have been obtained. Note also that the CMOS technologies used (0.35
µm NODE) also lead to reduced power consumption. The gate length used here (2 µm) are 6
times larger. Table 5.4 shows how the achieved sensitivity here could have been improved if a
higher current was generated in the Hall sensor.
Table 5.4 – The total sensitivity of the DC linear Hall Effect IC Vs the generated current to
the Hall sensor
Input Current to
the Hall sensor
(mA)
0.5
1
2
4
Power consumption
of the current source
circuit (mW)
5
10
20
40
Total IC’s power
consumption (mW)
Total sensitivity
(mV/mT)
5.35
10.35
20.35
40.35
8
16
32
64
As shown in Table 5.4, improved sensitivities could easily be achieved compared to current
silicon technology, however at the expense of increase in power consumption.
5.4.2 GaAs DC digital (unipolar) Hall Effect integrated circuit
The DC unipolar IC consists of a current source, Hall sensor, differential amplifier, level
shifter, comparator and source follower. The final mask discussed in Section 5.3 requires only
three pins, VDD, ground and output. However, for testing purposes, another mask was designed
in which one pad was allocated for each sub-circuit’s output to verify correct operation. The
fabricated version of this mask is depicted in Figure 5.22.
106
Figure 5.22 – DC digital (unipolar) Hall Effect integrated circuit (testing mask)
The measurement setup shown in Figure 5.20 was used to perform DC magnetic measurements
on this integrated circuit. The generated field in the coil (50 mT) was turned on and off in
intervals of 5 seconds. Output results of the differential amplifier, level shifter, comparator and
source follower were measured, recorded and are shown in Figure 5.23.
3.40
1.25
3.35
1.20
Level shifter's output (V)
Amplifier's output (V)
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.95
1.15
1.10
1.05
1.00
0.95
0.90
0.85
2.90
0
5
10
15
20
25
30
0.80
0
Time (Second)
5
10
15
20
Time (Seconds)
Differential Amplifier
Level shifter
107
25
30
1.0
5
Source follower's output (V)
Comparator's outour (V)
0.9
4
3
2
1
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
5
10
15
20
25
30
0
5
10
15
20
25
Time (Seconds)
Time (Seconds)
Comparator
Source follower
Figure 5.23 – The performance of the DC digital integrated sub circuits
As shown in Figure 5.23, the level shifter circuit reduced the output of the amplifier by 2.14 V.
The level shifter output in the absence of magnetic field is 820 mV, and it increased to 1.21 V
at 50 mT DC magnetic field. The overall sensitivity is maintained to be approximately 8
mV/mT. The comparator reference voltage was set to 870 mV. Thus, the level shifter’s output
required a 50 mV increase to reach the reference point of the comparator. This is equivalent to
a 6.25 mT magnetic field (50 mV / 8 mV), that is required to switch the comparator and the IC
high. The reason for allowing an increase of 50 mV for the switching was because the
amplifier’s output had a DC level variation of ±40 mV, so in here, 10 mV extra was allowed
to make sure the circuit operates successfully. It is apparent from Figure 5.23 that the
comparator circuit provides a digital output of approximately 1 V and 4.65 V in the absence
and presence of a 50 mT magnetic field. This was then reduced to 0 V (with 12 mV offset) and
980 mV by the source follower circuit to provide the final digital output of the integrated
circuit. The GaAs 2DEG DC digital (unipolar) Hall Effect integrated circuit functioned
satisfactory, and closely followed what was expected from simulation and measurements of the
sub-circuits. This IC consumes 18 mW of power at 5 V supply voltage.
To the best of the author’s knowledge, this is the first report of a digital (unipolar) Hall Effect
IC using 2DEG III-V semiconductor technology. The most sensitive available commercial Si
ICs are provided by Melexis (US5782), Honeywell (SS345PT) and Allegro (A1101) [102-104]
with switching sensitivities of 12 mT, 18 mT and 10 mT respectively. These are approximately
2, 3 and 1.5 times less sensitive than the 2DEG GaAs IC developed in this work. In terms of
108
30
power consumption, the IC developed in this work is comparable to the most power efficient
Si unipolar Hall IC (Honeywell (SS345PT)), where both ICs consume ~18 mW of power from
5 V of supply.
The final version of this IC was fabricated using the mask shown in section 5.3. Figure 5.24
shows a micrograph of the final fabricated DC unipolar Hall Effect IC.
Figure 5.24 – The final fabricated DC digital Hall Effect IC using the final mask
109
5.5 Summary
In this chapter, the performances of the first reported 2DEG GaAs-InGaAs-AlGaAs monolithic
DC linear and DC unipolar Hall Effect integrated circuits were discussed in detail. Initially
each IC was divided into sub-circuits. These sub-circuits were individually designed,
simulated, fabricated, tested and their performances closely followed their simulated results.
These sub-circuits were then combined, producing the DC linear and DC unipolar Hall Effect
ICs.
The DC linear Hall Effect IC consists of a constant current source, Hall Effect sensor and a
differential amplifier and provides an overall sensitivity of 8 mV/mT. This IC’s power
consumption of 6.35 mW was shown to be at least 2 times more power efficient than equivalent
silicon commercial DC linear Hall ICs. The DC unipolar Hall Effect IC consists of a DC linear
IC, a level shifter, comparator and source follower providing a switching sensitivity of
approximately 6 mT which is at least 50% more sensitive compared with commercial ICs [102104].
The DC linear and unipolar Hall Effect ICs can be used in applications such as automotive and
consumer industrial, solid state switch, wiper motor, Sunroof opener, seat motor adjuster and
electrical power steering. The 2DEG GaAs unipolar IC developed here should be capable of
operating at temperatures above 150 °C, since it makes use of wider band-gap materials
(compared to Si).
110
6
AC Linear Hall Effect Magnetometers using discrete 2DEG Hall sensors
6.1 Introduction
In order to avoid DC offsets and 1/f noise and increase detectability of small fields (in the
Nano-Tesla regime), the next objective was to develop an AC Hall Effect integrated circuit.
For this purpose, and in order to obtain an improved understanding of the required circuitries
for the IC, initially, three prototype AC linear magnetometers were built consisting of off-theshelf components. This included previously packaged and miniaturised 2DEG GaAs-InGaAsAlGaAs Hall Effect sensor, denoted as P2A, and discrete silicon components. The first
magnetometer was developed in order to detect and measure 50 Hz magnetic fields generated
from domestic current flow in conductors. Then, two more circuits were developed to measure
higher frequency fields, one detecting fields in the bandwidth of 1 to 100 kHz, and one
specifically designed for 33 kHz fields. The design details and performance of these circuits
are discussed in this chapter.
6.2 AC linear Hall Effect Magnetometer
Discrete AC linear magnetometers have been used widely in industrial applications. These
magnetometers detect the AC magnetic fields generated from an AC current flowing in a
conductor and provide an output proportional to the detected magnetic field (linear response).
The main example of an AC magnetometer is the Clamp-on Ammeter which is widely used in
many applications that require contact-less current measurements such as in power plant
maintenance and inspection, home electrical system maintenance/repair and industrial
manufacturing applications [112]. The ammeter, shown in Figure 6.1 (a), reads the strength of
the electromagnetic field generated from the current flow in a conductor via a Hall Effect sensor
placed in the jaws of the clamp. The Hall sensor’s output is processed within the internal
circuitries of the meter and the result is displayed. Figure 6.1 (b) shows the general circuitry
used for the clamp-on Ammeters.
111
Current
I (A)
A/D
Display
Converter
Circuit
Source
Unbalanced
voltage
Transformer
(a)
Jaws
Hall
compensating
Sensor
circuit
DC
AC
Rectifying
Amplifier
circuit
(b)
Figure 6.1 – Clamp-on Ammeter (a), the internal circuitry block diagram of the Ammeter (b)
[111-112]
The main advantage of clamp-on Ammeters is that they can measure the electrical current
remotely and without disturbing the circuit or system. However, there are three fundamental
disadvantages with these systems; firstly they are physically large. Secondly, they only have a
limited sensitivity with a minimum current detection of 10 mA [113] (due to the limitation in
the sensitivity of the silicon Hall sensor used), and thirdly, a key requirement for their operation
is that they have to be “wrapped” around the conductor which is a severe limitation.
In this work, a 2DEG GaAs-InGaAs-AlGaAs Hall Effect sensor (P2A) was used as part of
three analogue circuits to detect narrow (50 Hz and 33 kHz) and wide band (1 to 100 kHz) of
magnetic fields. Besides clamp-on ammeters, in this chapter, comparisons are also made
between the results of these circuits and search coils which are most commonly used in very
small field measurement applications. These circuits and their performance and results will be
discussed in details in the following sections.
6.2.1 Epitaxial profile of P2A Hall Effect sensor
The P2A Hall sensor used in the design of the magnetometers was grown in house, by
Molecular Beam Epitaxy in a VG V90H system and commercialised by Advanced Hall Sensors
Ltd in the UK. The design of the structure, shown in Table 6.1 consists of a superlattice of
AlGaAs-GaAs buffer layer, an active layer of strained In0.15Ga0.85As, a 50 Å AlGaAs spacer
layer, a silicon delta doped layer (5 × 1012 cm-2) and a 100 Å thick undoped GaAs cap layer
[59].
112
Table 6.1 – The Epitaxial layer profile of P2A Hall Effect sensor
Layer
100 Å Cap
Supply
δ-doping
50 Å Spacer
2 DEG Channel
Buffer
Semi insulating Substrate
Composition
GaAs
AlXGa(1-X)As
AlXGa(1-X)As
In0.15Ga0.85As
GaAs
GaAs
The P2A Hall sensor is a symmetrical device and has an input/output resistance of ~680  and
a current sensitivity of 0.16 mV/mA.mT. Table 6.2 shows the characteristics of the P2A Hall
sensor.
Table 6.2 – Characteristics of the P2A Hall sensor
Parameter
Input resistance
Output resistance
Current sensitivity
Operating temperature
Current sensitivity drift over temperature
Resistance drift over temperature
Power consumption for Vin = 1 V
Electron mobility (H)
Channel sheet carrier density (n)
P2A
680
680
0.16
-100 to +200
-0.08
0.3
1.4
6500
2×1012
Units


mV/mA.mT
C
%/C
%/C
mW
cm2/V.sec
cm-2
6.2.2 50 Hz Hall Effect Magnetometers
The P2A Hall sensor described above was used as part of a circuit to detect 50 Hz AC magnetic
fields. This circuit was especially designed to measure currents in domestic appliances
remotely. Figure 6.2 shows the block diagram of the 50 Hz Hall Effect AC magnetometer.
113
Current
HS
Amplifier
1
INA128
1µF
Amplifier
2
LM741
Low
Pass
Filter
AC to DC
Converter
Display
Source
Figure 6.2 – The top level design of the Portable Hall Effect 50 Hz Magnetometer
As shown in Figure 6.2, The 50 Hz AC magnetometer consisted of a current source which
generated a constant current of 3 mA to the Hall sensor. A Howland configuration was used
for the current source circuit [114]. This yields an overall sensitivity of the sensor of 0.48 nV/nT
(0.16 nV × 3 mA / nT). The sensor’s output (ΔVout) was then amplified using a low noise
instrumentation amplifier (INA128) with a noise density of 9 nV/√Hz and an amplification
gain of 800. Then, a 1 µF capacitor was used in order to block the DC offset generated from
the Hall sensor and the instrumentation amplifier. The signal was further amplified with a gain
of 44 in order to obtain an overall gain of 35,000 (90dB), which produced an overall circuit
sensitivity of 16 µV/nT (0.48 nV × 35,000 / nT). Since a majority of the circuit noise
performance is determined by the first stage (introduced and proved by Harald Friis in 1944
[115]), the noise of the second stage amplifier is not as critical. Thus, a LM741 op-amp with a
noise density of 20 nV/√Hz was used. A passive low-pass filter was added to eliminate all
frequencies above 50 Hz. The filtered AC signal was converted into DC and then sent to the
final circuitry to provide the final output to the LCD display with a resolution of 10 mV. Figure
6.3 depicts the circuit diagram of the 50 Hz Hall Effect magnetometer. This circuit was
designed and simulated in Multisim [116].
114
Figure 6.3 – Circuit diagram of the 50 Hz Hall Effect Magnetometer simulated in Multisim
[116]
The Bode plot of this circuit is depicted in Figure 6.4.
35000
50 Hz
30000
Gain
25000
20000
15000
10000
5000
0
10
100
1000
Frequency (Hz)
Figure 6.4 – Bode plot of the 50 Hz Hall Effect magnetometer
115
6.2.2.1 Results and discussion
In order to perform tests on this circuit, a variable AC current source was connected to a cable
and the Hall sensor was placed under this cable distance of 0.6 mm (including the distance
between the sensor to the top of its package). This setup is shown in Figure 6.5.
AC Current
generator
2DEG Hall Effect Sensor
(P2A)
+
lay
50 Hz Hall
Effect
Magnetometer
aDisp
1.43
Displ
-
Figure 6.5 – The test setup configuration of 50 Hz Hall Effect magnetometer
Figure 6.6 shows the current in the cable versus the voltage generated by the 50 Hz Hall Effect
magnetometer.
6
Output Voltage V)
5
4
3
2
1
0
0
50
100
150
200
250
300
Measured 50 Hz Current (mA)
Figure 6.6 – The AC current (rms) versus the displayed voltage from the 50 Hz Hall Effect
magnetometer
This circuit was capable of measuring 50 Hz currents as low as 500 µA at a 0.6 mm radial
distance from the wire. This was proportional to a magnetic field of approximately 600 nT. In
this case, this 50 Hz magnetometer was capable of detecting AC currents a factor of 20 smaller
116
(0.5 mA compared to 10 mA) than available commercial clamp-on Ammeters. The relative
magnetic field is calculated from the Biot-Savart [117].
B
0 I
2r
(6.1)
Where B is the magnetic field around the wire, I is the current flowing in the wire (500 µA in
this case), r is the radial distance between the sensor and the conductor (0.6 mm in this case)
and µ0 is the permeability of free space (μo = 4π x 10-7 Hm-1).
The limiting factor from detecting magnetic fields below 600 nT (excluding 1/f noise) is the
display resolution itself. Since the overall sensitivity is 16 mV/µT and the display resolution is
10 mV, the lowest magnetic field that can be displayed is 600 nT (10/16 µT ≈ 600 nT). The
lowest field measurable due to 1/f noise is around 100 nT. Figure 6.7 shows a picture taken
from the final version of the 50 Hz Hall Effect magnetometer and compared with a coil
inductive magnetometer.
P2A Hall
sensor
Inductive
Coil
The Hall Effect Current
Meter
(a)
(b)
Figure 6.7 – The magnetometer with an inductive coil (a), the 50 Hz Hall Effect
magnetometer using P2A Hall sensor (b)
117
The magnetometer shown in Figure 6.7 (a) was capable of detecting fields as low as 10 nT at
50 Hz. This is largely due to the fact that coils are more sensitive than Hall sensors, as discussed
in chapter 3. However, this was at the expense of large dimensions and weight. As is apparent
in Figure 6.7, the dimension of the Hall Effect sensor (P2A) was order of magnitude smaller
than the size of the inductive coil sensor. The sensitivity of these coils was dependent on
magnetic flux which is directly proportional to their dimensions Equation 6.2 and in order to
achieve a high sensitivity, the coils are by necessity large. The flux is given by:
  B A
(6.2)
Where B is the magnetic field strength and A is the area in which the magnetic field is measured
(dimension of the coil).
Figure 6.8 illustrates how the 2DEG magnetometer can detect 50 Hz magnetic field generated
from currents flowing in domestic cables.
Figure 6.8 – 50 Hz Linear Hall Effect Magnetometer detecting 50 Hz magnetic field from
currents flowing in a conductor
In this case, the displayed value is 0.03 which according to the calculations shown above is 1.8
µT (0.6 µT × 3).
118
6.2.3 33 kHz Hall Effect Magnetometer
This magnetometer was specifically designed and built as a replacement for a bulky search
coils used in cable detectors. There are many commercially available solutions that are used to
detect live cables, which usually come in a form of handheld device. EZiCAT i-Series [118]
can be mentioned as the main example of these cable detectors. These handheld cable detectors
are capable of locating generator signals (8 kHz and 33 kHz) at a maximum depth of 3 m, and
radio signals (15 - 60 kHz) at maximum depth of 2 m. Other cable detectors include
Radiodetection SuperC.A.T, Amprobe AT-5000, 3M Dynatel and Utilicom cable locators
[119-123]. These coils provide the benefit of ultra-high sensitivity (detecting magnetic fields
as low as 5 pT) [124], however, suffer from bulky dimensions, heavy weight and high power
consumption. Furthermore, the cable detectors mentioned above cannot be used in areas that
are deemed as unsafe or hazardous to humans.
In order to bring solutions to these issues, the P2A Hall Effect sensor was used as part of a
circuit to detect magnetic fields generated from a 33 kHz current flowing in a cable. As shown
in Figure 6.9, the circuit consists of a current source to supply a constant current to the Hall
sensor, two amplification stages consisting of an instrumentation amplifier (INA217) and an
inverting amplifier (NE5543) and a band-pass filter.
Current
Source
HS
Amplifier
1
0.1µF
Amplifier
2
INA217
NE5534
Band
Pass
Filter
Output
Figure 6.9 – Top level design of the 33 kHz magnetometer
As in the previous circuit, a Howland current source was used here which supplied a constant
current of 1 mA to the Hall sensor. Using this current, the sensitivity of the sensor was 0.16
nV/nT. The reason for selecting the INA217 as the first stage amplifier was due to its very low
noise and high gain-bandwidth product (Noise density = 1.3 nV/√Hz at 1 kHz and BW = 800
kHz at a gain of 100). The importance of a low-noise amplifier for the first stage was discussed
119
in section 6.2.2. The gain of the first stage amplification was 548. In order to achieve a higher
gain, a second stage amplifier with the gain of 68 was used. This provided an overall gain of
36,720 (91dB) and a circuit sensitivity of 6 µV/nT (0.16 × 36720 nV/nT). The noise
performance of the second stage amplifier was not as vital as the first stage, however it was
necessary to ensure the op-amp had a wide bandwidth (roll off frequency above 33 kHz). The
NE5543 with a noise density of 1.3 nV/√Hz at 1 kHz and gain bandwidth of 10 MHz (at unity
gain) was selected for this stage. A band pass filter with a centre frequency of 33 kHz and
bandwidth of 6 kHz (30 kHz to 36 kHz) was then used as the final stage of this circuit. The aim
of this stage was to remove/reduce any unwanted harmonics from the detected 33 kHz signal.
Figure 6.10 illustrates the circuit diagram of the 33 kHz Magnetometer. This circuit was
designed and simulated in Multisim [116].
Instrumentation Amplifier
Band Pass Filter
Current Source
Hall Sensor
2nd Stage Amplifier
Figure 6.10 – Circuit Diagram of the 33 kHz Hall Effect Magnetometer designed in Multisim
[116]
Figure 6.11 shows the Bode plot of this circuit. It is apparent from this figure that the maximum
amplification occurs at 33 kHz as designed.
120
40000
33 kHz
35000
30000
Gain
25000
20000
15000
10000
5000
0
1
10
100
1000
10000
100000 1000000
Frequency (Hz)
Figure 6.11 – The Bode plot of the 33 kHz Hall Effect Magnetometer simulated in Multisim
[116]
6.2.3.1 PCB design and shielding
A PCB was fabricated for the 33 kHz circuit, populated with components and properly shielded
in a grounded steel box. The PCB shown in Figure 6.12 consisted of the components and ICs
described in section 6.2.3 and a protruding arm which connects the Hall sensor to the circuit.
The 4 lines on this arm were initially laid straight. However, this design resulted in Faraday
induced voltages and the final detected signal was much larger than predicted. This signal was
also frequency dependent, and according to Faraday’s law, induced voltage is proportional to
the rate of change of flux lines cutting the conductor [125]. Faraday’s law for a straight line is
given by Equation 6.3.
VL 
d
dt
(6.3)
Where VL is the induced voltage and dɸ/dt is the rate of change of magnetic flux in
Weber/Second. For this reason, the induced voltage was negligible in the 50-Hz magnetometer
circuit and more apparent in the 33 kHz circuit.
In order to cancel/reduce the pickup, the four lines (two inputs and two outputs of the Hall
sensor) were twisted in the final PCB layout. The PCBs were laid out in Altium [126]. This
layout is shown in Figure 6.12.
121
Current Source, Amplifiers and other components
Arm (twisted lines)
Hall Sensor
Figure 6.12 – The PCB layout of the 33 kHz Hall Effect Magnetometer laid out in Altium
[126]
The twisted lines reduced the loop areas and as the result, the pickups using this PCB were
reduced by 75% compared to the results from the PCB using straight lines. In order to reduce
the pickups even further, the PCB arm was fully wrapped with a flexible magnetic shielding
Foil. This foil was made of high-performance Nanocrystalline alloy and was specifically used
for applications that require shielding against high-frequency magnetic fields [127]. Figure
6.13 shows the final populated PCB in the metal steel box supplied by two 9V batteries (PP3)
and fully shielded arm.
Hall Sensor
Arm
Figure 6.13 – 33 kHz Magnetometer PCB arm shielded with Nanocrystalline foil
Using the twisted arm method, steel metal box and the magnetic shielding foil around the arm,
the pickup was reduced by 98%. Figure 6.14 shows the final 33 kHz fully shielded circuit.
122
Figure 6.14 – 33 kHz Magnetometer PCB in Steel box and shielded
6.2.3.2 33 kHz Hall Effect magnetometer testing, results and discussion
A Function generator was used to generate a 33-kHz signal with known amplitudes to a
Helmholtz coil shown in Figure 6.16. The Helmholtz coil was used to generate known magnetic
fields and consisted of two identical circular coils of radius (R) and placed at a distance of R
from each other. When an electric current was driven through the coil, magnetic field was
generated. This magnetic field produced was extremely uniform in the mid-plane between the
two coils and its value is given in Equation 6.4.
B
8 oNI
125 R
(6.4)
Where, N is the number of turns of each coil (in this case N = 10), R is the radius of the coil
(in this case R = 55 mm), I is the driving current in the coil and μ o is the permeability of free
space (μo = 4π x 10-7 Hm-1). If the current in the coil is known, the created magnetic field can
be calculated from Equation 6.5.
B = I × 1.6 × 10-7T
123
(6.5)
Figure 6.15 shows the Helmholtz coil and the magnetic field lines produced. A uniform
magnetic field can be noticed in the mid-plane between the two coils and this is where the
magnetic measurements were performed.
Figure 6.15 – Magnetic field generated using a Helmholtz Coil [128]
Figure 6.16 shows the full setup used for the measurements. The output signal was monitored
using a Hameg Spectrum Analyser.
Figure 6.16 – The full Testing Setup for measurements
The measurements were performed for 33 kHz magnetic field of magnitudes 100 nT, 50 nT
and 25 nT (Peak to Peak). Since the overall circuit sensitivity is known (6 µV/nT), and the
generated magnetic field in the Helmholtz coil is determined, the expected output voltage can
124
be calculated and compared with the measurement results. Both measured and calculated
results for magnetic fields of 100 nT, 50 nT and 25 nT are shown in Table 6.3.
Table 6.3 - Measured and Expected Results
33 kHz Magnetic
field
Measured
Calculated
Deviation
(pick-up)
6 µV × 100 =
+12%
600 µV
6 µV × 50 = 300
B = 50 nT
340 µV
+11.7%
µV
6 µV × 25 = 150
B = 25 nT
Not Detected
-----µV
The minimum magnetic field that was detected (signal larger than noise) was 50 nT. As shown
B = 100 nT
685 µV
in Table 6.3, after shielding the circuit properly, the maximum deviation between the measured
and calculated results was reduced to +12%.
These results are with an input current of only 1 mA to the Hall sensor. The power consumption
of the sensor at this current is 720 µWatts (I2 × R = (1×10-3)2 × 720).
The sensitivity of the Hall sensor and the minimum detectable field can be improved if a larger
current is supplied to the Hall sensor. For example, if an input current of 5 mA was used instead,
using the same circuit gain, the circuit sensitivity would be 30 µV/nT and the minimum
detectable magnetic field would be 10 nT instead of 50 nT. This is, of course, at the expense
of an increase in the sensor power consumption. The sensor power consumption for I = 5 mA
would be 3.5 mW (5 times larger).
6.2.3.3 Noise and limitations
The limiting factor in detecting lower magnetic fields, at 33 kHz of frequency is Thermal noise.
Thermal noise (also called Johnson noise) is produced by the random motion of charge carriers
in the Hall plate resistance (R). The mean square noise voltage (2) is given by:
2 = 4kTRBw
(6.6)
Where, k represents the Boltzmann’s constant (1.3806504×10-23 J/K), T is the ambient
temperature and Bw is the bandwidth of the noise.
Observing the noise level at a fixed frequency per square Root of Hertz (33 kHz in this case),
and for the P2A Hall sensor with resistance of 720 Ω (worst case), the sensor Thermal noise
is:
125
 = √(4×1.38×10-23×273×720) = 3.3 nV/√Hz
According to the above calculation, the sensor thermal noise would be 3.3 nV in a 1 Hz
bandwidth. Therefore, the detectable minimum magnetic field for the sensor on its own and for
I = 1 mA would be:
 = Hall sensor sensitivity (S) × I × B ==> 3.3×10-9 = 160×10-3×B (in T) ==> B ≈ 20 nT
However, the circuit itself involves the INA217 with a noise density of 1.6 nV/√Hz and
resistors to set the gain, filtering etc. Thus, the total noise of the circuit would be considerably
higher. The following graph shows the noise simulation for the entire circuit (including the
Hall Effect sensor). This simulation was performed using Multisim [116].
0.00030
Noise Density (V/Sqrt(Hz))
270µV/√Hz @ 33 KHz
0.00025
0.00020
0.00015
0.00010
0.00005
0.00000
1
10
100
1000
10000 100000 1000000 1E7
Frequency (Hz)
Figure 6.17 – Noise Simulation of the 33 kHz Hall Effect Magnetometer performed in
Multisim [116]
The noise for the entire circuit, according to the simulation is 270 µV/√Hz at 33 kHz (after
gain). This implies the minimum magnetic field that can be detected by this circuit would be:
Vnoise (Circuit output) = Hall Sensor Sensitivity (S) × I × B × Gain ==> 270×10-6 = 160×10-3×
B × 36720 ==> B ≈ 44 nT
126
This result is very close to the 50 nT of the minimum field detected in actual measurements.
Therefore, the measurement results are compliant with the simulation results.
6.2.3.4 Improving the circuit sensitivity using ferrites
As discussed above, using the designed circuit with a gain of 36,720 and input current of 1 mA
to the P2A Hall sensor, the minimum magnetic field that could be detected was 50 nT. In order
to improve the sensitivity of the sensor, flux concentrators or ferrites could be added on/next
to the Hall sensors. These are normally made of Nickel, Zinc and/or Manganese compounds
which have very high permeability and have a great ability to concentrate a magnetic field
within them. This would intensify the detectability if one is added onto the Hall sensor.
Examples of ferrites with very high permeability are Amorphous, Nanocrystalline, Permalloy
and Mu-Metal. Using the ferrite/concentrator along with the Hall sensor will increase the total
sensitivity of the sensor by a factor of G, as shown in Equation 6.7.
BMin = (√4KTR) / (SHall Sensor × I × G)
(6.7)
The concentrators increase the overall footprint of the sensor, but reduce the detected field by
1/G, where G is the concentration factor. The concentration factor of the ferrites is a function
of the relative permeability (µr) of the material used to make the flux concentrators, the ratio
between the length of the concentrator and the size of the air gap [129]. Figure 6.18 shows the
achieved enhancement in detecting magnetic fields using two concentrators along with a Hall
sensor. These concentrators are a flat mu-metal triangle with permeability of 30,000 and a
MnZn ferrite rod with permeability of 60,000 [130].
Figure 6.18 – Enhancement versus the separation of a Ferrite to the Hall sensor in detection
of magnetic field [130]
127
As shown in Figure 6.18, a concentrator with a separation of 1 mm using 5 cm mu-metal, a
factor of twenty improvements in detecting magnetic field can be achieved. The enhancement
is marginally increased with the MnZn Ferrite rods owing to the higher permeability. In
addition, the sensitivity of mu-metal concentrator is limited by its Johnson noise, while the
ferrite concentrators achieve a greater sensitivity largely due to the fact that MnZn has a much
lower electrical conductivity and thus negligible Johnson noise [130].
The magnetic field around the concentrators is almost cylindrical and the magnetic
enhancement is given by:
Magnetic Enhancement = 𝐾𝐿/𝜋x (for x ≥ g/2)
(6.8) [131]
Where L is the length of the concentrator, g is the air gap between the sensor and concentrators
and K is numerical factor dependant on the material permeability (0 < K ≤ 1) [131].
As shown in Equation 6.8, the Length Ferrite / air gap ratio and the permeability of the material
determine the achieved enhancement (G) [131]. For example, with an air gap of 1 mm and
using two very high permeability ferrites (K ≈ 1) with dimensions of 10 mm × 1 mm, an order
of magnitude enhancement can be achieved. This is shown in Figure 6.19.
Air gap = 1 mm
Ferrite
P2A
10mm
3mm
Ferrite
1mm
10mm
Figure 6.19 – Adding the Ferrites on wither sides of the P2A Hall Sensor
Via the Use of two ferrites shown in Figure 6.19, the minimum field for the 33 kHz
magnetometer circuit discussed previously could be reduced from 50 nT to 500 PT. However,
this is at the expense of increased dimension (23 mm × 1 mm). The concentrators also introduce
potential nonlinearity and hysteresis effects, but these issues can essentially be avoided by
working at a specific single frequency (33 kHz in this case).
6.2.4 Wide band (100 kHz) Hall Effect Magnetometer
The P2A Hall Effect sensor was also used as part of a wide-band circuit to detect and measure
magnetic fields up to 100 kHz. The top level diagram of this magnetometer is depicted in Figure
6.20. The same configuration as the 33 kHz circuit was used here except that the overall
128
amplification gain was increased from 36,720 (91dB) to 39,480 (92dB), a higher input current
was supplied to the Hall sensor (2.8 mA) and no filtering was used so that a wide band of
frequencies can be covered.
Current
Source
HS
Amplifier
1
0.1µF
INA217
Amplifier
2
NE5534
Output
Figure 6.20 – Top level design of the wide band Hall Effect magnetometer
Figure 6.21 shows the circuit diagram of this magnetometer.
Current Source
Output
Inverting Amplifier
Instrumentation Amplifier
Figure 6.21 – Circuit diagram of the wide band Hall Effect magnetometer designed in
Multisim [116]
Figure 6.22 shows the Bode plot for this circuit.
129
40000
Gain
30000
20000
10000
0
1
10
100
1000
10000
100000 1000000
Frequency (Hz)
Figure 6.22 – Bode plot of the wide band Hall Effect Magnetometer simulated in Multisim
[116]
The gain of the first stage (INA217) and second stage (NE5534) amplifications were 70 and
564 respectively. Most of the gain here is achieved from the second stage amplification, as the
NE5534 provided an improved gain-bandwidth product. As shown in Figure 6.22, the -3dB
point (corner frequency) occurs at 100 kHz. The overall circuit sensitivity was 18 µV/nT.
The same procedure described in section 6.2.3.1 was used to shield the circuit against field
pick-up. An identical setup (as shown in Figure 6.16) including the Helmholtz coil, spectrum
analyser, and function generator were used to perform magnetic measurements on this circuit.
Since the overall circuit sensitivity (18 µV/nT) and the generated field in the Helmholtz coil
(B = I × 1.6 × 10-10 T) are known, for a known current to the coil, the circuit output can be
calculated. Measurements were conducted on this circuit in a magnetic field of 300 nT and for
the frequency range from 100 Hz to 1 MHz. The measured versus calculated results are
illustrated in Figure 6.23.
130
0.006
Output Voltage (V)
0.005
0.004
0.003
0.002
0.001
Measured
Calculated
0.000
100
1000
10000
100000
1000000
Frequency (Hz)
Figure 6.23 – Measured versus calculated results for the wide band Hall Effect circuit
As can be seen from Figure 6.23, the measured results closely follow the calculated results with
a maximum deviation of 9%.
Moreover, magnetic field measurements were also conducted on this circuit to determine the
minimum field that can be measured over the 100 kHz of frequency. These measurement results
are depicted in Figure 6.24.
Minimum Detectable field (nT)
700
600
500
400
300
200
100
100
1000
10000
100000
Frequency (Hz)
Figure 6.24 – Minimum detectable field measurements on the wide band Hall Effect circuit,
(measurement BW = 10 Hz)
131
As shown in Figure 6.24, the minimum magnetic field that could be detected and measured
with this circuit is approximately 9 nT (at a S/N of 3 dB) from 1 kHz to 100 kHz, in a
measurement bandwidth of 10 Hz. The minimum detectable field at 100 Hz and 200 Hz were
640 nT and 320 nT respectively. The reason for an increase in the minimum detection at
frequencies below 1 kHz is due to the presence of 1/f noise as detailed in chapter 3, section
3.3.6.2.
In this case, a 9 nT magnetic field is proportional to 100 µA current. Note that, this current is
two orders of magnitude smaller than is usually measured using clamp-on Ammeters. The
Ferrites discussed earlier in this chapter could be implemented in order to improve the
sensitivity further, however this would introduce non-linearity into the circuit as previously
discussed.
6.3 Summary
A discrete packaged 2DEG Hall Effect sensor (P2A) was used as part of three circuits in order
to develop ultra-sensitive narrow and wide band magnetometers. The first magnetometer was
designed in order to detect and measure the magnetic fields generated from domestic 50 Hz
current flow in conductors. This circuit was capable of detecting 50 Hz currents as low as 500
µA, proportional to 600 nT magnetic field at a 0.6 mm distance from the conductor. The second
circuit was specifically developed as a replacement for the bulky search coils used in cable
detectors. This circuit provided high sensitivity and low field detectability (50 nT without and
500 pT with Ferrites) using the 2DEG Hall Effect sensor. Furthermore, a 100 kHz bandwidth
magnetometer with the detection capability of ~10 nT was designed and developed. This wide
band magnetometer provided at least two orders of magnitude better detectability of small
currents compared to the commercial Hall Clamp-on Ammeters.
132
7
AC Linear Integrated Hall Effect Circuit
7.1 Introduction
Following the demonstration of the wide and narrow band AC linear magnetometers using
discrete 2DEG Hall Effect sensors, the next step was to design, fabricate and develop an AC
linear integrated Hall Effect circuit. As discussed previously, commercial linear Hall Effect
integrated circuits are all based on silicon. Although, these ICs have been extensively employed
in such diverse applications as automation, medical, electronic and electrical industries [132],
they have limitations in sensitivity, wide operating frequency range and low field detectability
[9-11, 133-136].
Hence, the aim of this part of the work was to develop an all GaAs integrated version of the
low field linear Hall Effect circuits demonstrated previously. The process as described in
chapter 5 was employed to develop the AC linear Hall Effect IC.
7.2 The Linear Hall Effect IC top-level design
The linear Hall IC design was divided into 3 sub-circuits comprising the Hall Effect sensor, a
current source and a differential amplifier. The top-level configuration of this IC is illustrated
in Figure 7.1. Each of these sub-circuits were designed, simulated, fabricated and tested
individually, and they were then combined to form the complete GaAs-InGaAs-AlGaAs 2DEG
AC linear Hall IC.
Figure 7.1 – The top level design of the AC linear Hall Effect integrated circuit
133
7.2.1 The current source design, simulation and testing results
The current source circuit consisted of a single saturated pHEMT whose gate is connected to
its source and two diodes. The transistor with a single finger gate width of 40 µm and the two
diodes with width of 200 µm provided the 1 mA of constant current to the Hall sensor. Figure
7.2 illustrates the circuit layout in the simulation (a), on the mask (b) and after fabrication (c).
A resistor value of 1.75 kΩ (Rin of the XMBE303 Hall sensor) was used in order to represent
the XMBE303 Hall sensor in the simulation.
Supply voltage
(5V)
Diode 1
L = 2 µm
W = 200 µm
Diode 2
L = 2 µm
W = 200 µm
The Hall sensor
(1.75 kΩ)
pHEMT
(222_1×40 µm)
(a)
(b)
(c)
Figure 7.2 – The configuration of the Current Source Circuit in simulation (a), on the mask
(b) and after fabrication (c) – Dimension: 650 × 750 µm2
As discussed in chapter 4.4, XMBE303 drain-source current has shown excellent stability for
a drain-source voltage range of 1 V to 3 V since the pHEMT output conductance for this range
is very low (g0 = 0.4 mS/mm). For this reason, the two Schottky diodes with the width of 200
µm (2 µm gate length) have been used to decrease the 5 V supply voltage down to about ~2.3
V. This would provide a 0.7 V margin to ensure that variations caused during the lithography
have the least possible effect on the generated current by the current source circuit. These
variations can be caused by small difference in the transistor dimensions compared to the
dimensions used in the simulation (due to errors involved in the lithographical process),
variations in the 2DEG mobility and carrier concentration and therefore the transconductance,
the misalignment of gate, mesa and/or ohmics and the thickness of the Ohmic metals (mainly
AuGe and Ni) evaporated onto these transistors in different runs. Despite all these possible
variations and due to the excellent process optimisations developed in this work, this circuit
has shown excellent stability, with variation of less than 3%, over 28 process runs.
134
7.2.2 The differential amplifier design, simulation and testing results
An open loop differential amplifier was designed to amplify the output of the Hall sensor, so
that ultra-low magnetic fields could be easily detected. The aim was to achieve the maximum
gain possible from a single stage amplification so that the overall IC power consumption and
size could be reduced. The following points were considered as the objectives when designing
this circuit:
1.
Circuit with a gain of at least 1000
2. Operating frequencies larger than 10 kHz (the limit of silicon commercial Hall ICs due to
offset cancellation spinning technique)
3. Power consumption below 10 mW
Prior to the design of the differential amplifier circuit, there were two limitations (compared to
CMOS technology) which had to be considered.
1. The major limitation in designing a differential amplifier using GaAs technology is the
absence of complementary devices. Although it is possible to produce p-channel GaAs
transistors, and use them in the same manner as PMOS transistors, this is not very practical
in GaAs. This is mainly because the hole mobility of GaAs is poor [137] and the resulting
cut-off frequency would be lower than silicon devices.
2. The second limitation is the negative rail which was removed. This was mainly to reduce
one pin from the final packaged IC and make it more convenient for users.
Considering the points mentioned above, the differential amplifier circuit was designed. As
shown in Figure 7.3, the differential amplifier circuit consisted of a differential pair (P 1 and
P2), a saturated pair (P3 and P4) and an active load transistor (P5).
135
Supply voltage
(5V)
P3 (222_1×10µm)
P4 (222_1×10 µm)
Output
P1 (222_4×300 µm)
P2 (222_4×300µm)
P5 (222_1×20 µm)
Figure 7.3 – The configuration of the differential amplifier circuit
The amplifier’s power consumption at 5 V was 5.4 mW (1.08 mA × 5 V). In the final IC, the
Hall sensor’s outputs would be connected to the differential pair P 1 and P2, with the four gate
finger widths of 300 µm (1.2 mm width in total). The amplifier’s output was taken from the
drain of P1. If there was no AC magnetic field applied to the sensor, the Hall sensor’s outputs
is a DC signal (as the supplied current to the sensor is DC) and would equally be:
V+ = V- = (0.5 × I × Rin) + VCS
(7.1)
Where VCS is the voltage dropped across the transistor in the current source circuit discussed
in 7.2.1. If no AC magnetic field was detected by the sensor, no AC signal would appear on
the sensor’s outputs and thus at the amplifier’s output. However, if an AC magnetic field was
applied to the sensor, proportional to the strength of the magnetic field, an AC output would
appear at the sensor’s outputs. This signal would be amplified by the gain of the circuit and
would appear at the amplifier’s output. The gain of this circuit is determined by Equation 7.2.
AV 
Gm1  RO
2
(7.2)
Where, Gm1 is the transconductance of P1, RO is the parallel drain-source resistance of P1 and
P3 (RDS1 || RDS3). The simulation, in ADS, showed an AC gain of 1333 (62.5 dB) at a bandwidth
of 200 kHz. Figure 7.4 illustrates the Bode plot of the amplifier circuit obtained from the
simulation.
136
1400
1200
Gain
1000
800
600
400
200
0
100
1000
Frequency (kHz)
Figure 7.4 – Differential amplifier Bode plot obtained from simulation
Note that this amplifier has a DC output of 2.75 V as no negative rail has been used. This DC
signal can easily be removed using an external capacitor. Figure 7.5 depicts the configuration
of the differential amplifier circuit developed here on the mask and after fabrication.
(a)
(b)
Figure 7.5 – Configuration of the differential amplifier circuit (a) on the mask and (b) after
fabrication – Dimension: 525 × 720 µm2
This circuit was fabricated and tested on its own over 28 runs and shown to successfully provide
the expected amplification gain (±3%). The test on this circuit was conducted using two
137
external AC signals, to represent the Hall sensor’s outputs. The circuit was shown to
successfully differentiate the two signals amplitude and multiply the difference by the gain.
Table 7.1 shows the full characteristics of the GaAs-InGaAs-AlGaAs (XMBE303) differential
amplifier.
Table 7.1 – Characteristics of the integrated GaAs-InGaAs-AlGaAs (XMBE303) differential
amplifier
Gain
Power consumption at 5 V of supply
Bandwidth
Number of devices used
1333 (62.5 dB)
5.4 mW
200 kHz
5 pHEMTs
As shown in Table 7.1, the gain, operating frequency range, and power consumption achieved
here fulfilled the initial objectives.
7.2.3 The integration of the linear Hall Effect circuits
Once each of the sub-circuits were individually designed, simulated, fabricated and tested, a
mask for the linear IC with the overall dimension of 0.65 mm × 0.9 mm was laid out. The
graphical representation of each layer mask is illustrated in Figure 7.6.
Mask 1 – Mesa
Mask 2 – Ohmic
138
Mask 4 – Gate
Mask 3 – Bond-pads
Mask 5 – Via
Mask 6 – Bridge (Full IC)
Figure 7.6 – The mask layers of the GaAs 2DEG AC linear Hall Effect IC
The linear Hall Effect IC design was then fabricated. The final fabricated IC is illustrated in
Figure 7.7.
139
Figure 7.7 – Linear Hall integrated circuit layout
The overall sensitivity was 533 mV/mT and was determined by the Hall Effect sensor’s
sensitivity (0.4 mV/mT biased at 1 mA) and the amplifier’s gain of 1333. This is a factor of
10, 13 and 37 higher compared with the commercial Allegro (A1324), Melexis (MLX90242)
and Honeywell (SS39ET) [9-11] devices. In addition to providing very high sensitivity, this IC
has a power consumption of only 10.4 mW. Despite being the most sensitive amongst all
commercial silicon ICs investigated in this study, the power consumption of the Honeywell
SS39ET IC is 30 mW (at 5 V supply), which is a factor of ~3 times larger than the GaAs Hall
IC reported here. The power consumption for the Allegro A1324 and Melexis MLX90242 ICs
are 34.5 mW and 12.5 mW at 5 V supply, respectively. The reason for the high power
consumption of these silicon ICs is due to the complex circuitries for spinning current
technique, circuit protection, signal buffering, offset and 1/f noise cancellation.
7.2.4 Linear Hall Effect integrated circuit magnetic testing and characterisation
In order to test the sensitivity of the IC, and especially its low field detectability, known small
AC fields were generated using a Helmholtz coil. The same Helmholtz coil depicted in Figure
6.16 (with 10 turns) was used to perform the magnetic measurements on the fabricated linear
Hall Effect IC. The generated magnetic field in this coil was B = I × 1.6 × 10 -7 T.
140
As the generated magnetic field can be accurately determined and the overall sensitivity of the
circuit is known (0.4 × amplifier’s gain (at a specific frequency) nV/nT), the expected output
of the integrated circuit, at a specific field, can be calculated. Measurements were carried out
at a magnetic field of 250 nT over the frequency range of 1 to 200 kHz. Figure 7.8 illustrates
the measurement versus the expected (calculated) results.
8E-5
7E-5
Output (V)
6E-5
5E-5
4E-5
Calculated
Measured
3E-5
2E-5
1000
10000
100000
Frequency (Hz)
Figure 7.8 – Measured and calculated output at B = 250 nT
As can be seen, the measured output from the IC closely followed the calculated results
verifying the experimental setup. The maximum deviation here is 8.5%.
Further measurements were then performed on this IC at magnetic fields of 2 µT, 1 µT, 0.5 µT
and 0.25 µT (until the noise floor level of the circuit was reached) for the frequency range from
50 Hz to 200 kHz. The results from these measurements are depicted in Figure 7.9. For
magnetic fields less than 1 µT at frequencies below 500 Hz, the output could not be detected,
due to the effect of 1/f noise.
141
Output (V)
1E-3
1E-4
2 µT
1 µT
0.5 µT
0.25 µT
1E-5
10
100
1000
10000
100000
Frequency (Hz)
Figure 7.9 – Linear Hall IC Output at magnetic fields of 2 µT, 1 µT, 0.5 µT and 0.25 µT for
the frequency range of 50 Hz to 200 kHz
The circuit was thus capable of detecting magnetic fields as low as 177 nT in the frequency
range of 500 Hz to 200 kHz (at a S/N = 2). This was determined in the measurement bandwidth
of 10 Hz. Figure 7.10 shows the minimum detectable magnetic field at frequencies from 50 Hz
to 200 kHz. The smallest detectable magnetic field is seen to increase at frequencies below 1
Minimum Detectable Magnetic Field (nT)
kHz due to 1/f noise, and reaches 700 nT at 50Hz.
700
600
500
400
300
200
100
100
1000
10000
100000
Frequency (Hz)
Figure 7.10 – Minimum detectable field by the Linear Hall Effect IC in the frequency range
of 50 Hz to 200 kHz at S/N of 2 in a measurement bandwidth of 10 Hz
Table 7.2 summarises the key properties of this linear Hall IC.
142
Table 7.2 – Summary of the GaAs-InGaAs-AlGaAs linear Hall IC characteristics
Circuit sensitivity
533 µv/µT
Supply bias current at 5 V
2.08 mA
Minimum detectable field (in BW = 10 Hz)
177nT
Frequency range of operation
500 Hz to 200 kHz
Dimension
0.65 mm × 0.9 mm
Figure 7.11 shows the results of field measurements on the commercial linear Hall ICs as
compared to the GaAs Hall IC. All the measurements here were performed in a 10 Hz
bandwidth. The performances at low frequencies become comparable in part due to the onboard noise cancellation circuitry that the silicon based sensors have in comparison to the
InGaAs-GaAs-AlGaAs IC fabricated here. This technique was not employed here as this would
have made the circuitry complex and more power hungry. However, considerable
improvements are expected if such circuit techniques were used here. At high frequencies, the
Minimum Detectable Magnetic Field (nT)
superiority of the III-V based circuit is seen in both resolution and bandwidth.
10000
1000
GaAs 2DEG
Allegro A1324
Honeywell SS39ET
Melexis MLX90242
100
1
10
100
1000
10000
100000
Frequency (Hz)
Figure 7.11 – Comparison of the GaAs 2DEG linear Hall IC with linear Hall ICs made by
Allegro, Honeywell and Melexis in terms of Minimum detectable field as a function of
frequency at S/N of 2 in a 10 Hz measurement bandwidth
The minimum detectability in Figure 7.11 is defined as the point where the amplitude of the
signal is twice the noise (S/N = 2). The Honeywell SS39ET IC showed the lowest minimum
field detectability of 652 nT. This detectability, in comparison with the GaAs IC, is higher by
a factor of four. Furthermore, the high frequency performance of these silicon ICs are limited
143
to 10 kHz (in the case of Honeywell and Allegro), whereas the GaAs 2DEG IC is capable of
operating up to 200 kHz. The limitation of the operating frequency in these commercial ICs is
largely a result of the on-board current spinning technique used to reduce the Hall element
offset and 1/f noise. Such a technique limits the operating frequency range typically to 10 kHz
because of the use of typical 100 kHz spinning frequency [97-98]. Table 7.3 compares the
performances of the various Hall Effect linear ICs.
Table 7.3 – Linear Silicon Hall Effect ICs (Honeywell, Allegro and Melexis) and comparison
with the GaAs 2DEG Hall IC
Supplier (Product)
Minimum
Detectable Field
Operating Frequency Power Consumption
Range
at 5V of Supply
Honeywell (SS39ET)
652 nT
DC to 10 kHz
30 mW
[9]
Allegro (A1324) [10]
864 nT
DC to 10 kHz
34.5 mW
Melexis (MLX90242)
6500 nT
DC to 2 kHz
12.5 mW
[11]
GaAs 2DEG IC
177 nT
500 Hz to 200 kHz
10.4 mW
The GaAs 2DEG Hall IC is not only capable of detecting lower magnetic fields, but also
enhances the current technology in terms of operating frequency range and power consumption.
7.3 Summary
The design, fabrication and performance of the first GaAs-InGaAs-AlGaAs 2DEG fully
integrated linear Hall Effect integrated circuit were presented. This IC provided a sensitivity of
533 nV/nT which is an order of magnitude larger than that of the most sensitive commercially
available linear Hall IC, Allegro A1324 (S = 50 mV/mT). The GaAs IC was capable of
detecting AC magnetic fields as low as 177 nT in a 10 Hz bandwidth, which is almost a factor
of 4 lower than the best commercially available Si Hall IC. The GaAs 2DEG IC was also
capable of operating at bandwidths greater than 200 kHz compared with bandwidths of around
10 kHz for the commercially available silicon ICs. The GaAs IC had a total power consumption
of 10.4 mW (at 5 V), which is lower than that of silicon ICs (minimum of 12.5 mW) [9-11].
The GaAs-InGaAs-AlGaAs 2DEG linear Hall IC is well suited for a vast number of
applications such as Non Destructive Testing (NDT), linear and rotary position sensing,
contactless current sensing, detection of overcurrent from power lines and for use in harsh
environments.
144
8
Conclusions and Future work
8.1 Conclusion and summary of the thesis
The main objective of this work was to develop the first Hall Effect integrated circuits based
on GaAs-InGaAs-AlGaAs 2DEG technology.
Leading to the accomplishment of this objective, numerous designs, fabrication runs and
characterisations of GaAs-InGaAs-AlGaAs pHEMTs that were suitable for the design of the
Hall ICs were undertaken. Through a careful growth and accurate band-gap engineering, the
fabricated 2 µm pHEMTs showed a threshold voltage of -0.4 V, overall intrinsic gain of 405,
and a cut off frequency of 4.8 GHz. The latter results eliminated the need for a negative rail in
the circuit design and assisted in designing power efficient and sensitive Hall Effect integrated
circuits. Empirical device models were developed and generated in Advanced Design System
(ADS) to accurately predict the performance of the integrated circuits. Using these models,
excellent fits were obtained between the measured and modelled graphs validating the high
precision and accuracy of the obtained models.
Greek cross Hall Effect sensors with L/W of 60/20 µm were also developed and characterised.
These sensors were showed to have a current sensitivity as high as 0.4 mV/mA.mT,
input/output resistance of 1750 Ω and a maximum magnetic DC offset of 0.35 mT at 1 V of
input voltage. This offset was further reduced by 76% when the parallel Hall sensor technique
was employed.
Using the characterised and modelled pHEMTs and its associated Hall sensor, a highly
sensitive and low power DC digital (unipolar) and DC linear Hall Effect integrated circuits
were fully designed and simulated in ADS, then, fabricated, tested, packaged and fully
characterised. The DC linear Hall Effect IC consisted of a constant current source, Hall Effect
sensor and a differential amplifier. This circuit provided an overall sensitivity of 8 mV/mT and
power consumption as low as 6.35 mW which in comparison with commercial DC linear Hall
ICs (based on silicon), is at least a factor of two more power efficient. The DC digital (unipolar)
Hall Effect IC consisted of the DC linear IC along with a level shifter, comparator and source
follower. This circuit displayed a switching sensitivity of ~6 mT which is almost 2, 3 and 1.5
times more sensitive respectively compared to Melexis (US5782), Honeywell (SS345PT) and
Allegro (A1101) [102-104] commercial products. The DC linear and unipolar Hall Effect ICs
145
can be utilised in applications such as automotive and consumer industrial, solid state switch,
wiper motor, sunroof opener, seat motor adjuster and electrical power steering.
In addition, a novel low power GaAs-InGaAs-AlGaAs 2DEG linear Hall Effect integrated
circuit with unprecedented sensitivity and wide dynamic range was designed, simulated,
fabricated and characterised. This IC produced a sensitivity of 533 nV/nT which was an order
of magnitude larger than that of the most sensitive available commercial Si linear Hall IC,
Allegro A1324 (S = 50 mV/mT). The GaAs IC was capable of detecting AC magnetic fields
as low as 177 nT (S/N = 3 dB) in a 10 Hz of bandwidth, which is almost a factor of four lower
than the best commercially available Si linear Hall IC. Furthermore, the GaAs 2DEG linear
Hall IC had operating bandwidths greater than 200 kHz compared with bandwidths of around
10 kHz for the commercially available silicon linear ICs. The GaAs linear IC had a total power
consumption of 10.4 mW (at 5 V), which was at least 20% less than that of silicon ICs (10.4
mW vs. 12.5 mW) [9-11]. These silicon ICs employ current spinning technique, which makes
circuitry complex, power hungry and limits their operating frequency range. The 2DEG GaAs
linear IC is well suited for a vast number of applications such as in linear and rotary position
sensing, contactless current sensing, detection of overcurrent from power lines and for use in
harsh environments.
In parallel with the development of the integrated circuits, a discrete packaged 2DEG GaAsInGaAs-AlGaAs Hall Effect sensor (P2A) [59] was used as part of three circuits made from
off-the-shelf discrete silicon components in order to develop ultra-sensitive narrow and wideband magnetometers. The first magnetometer was designed in order to detect and measure the
magnetic fields generated from 50 Hz current flow in domestic environments. This circuit
showed excellent sensitivity, measuring 50 Hz currents as low as 500 µA non-intrusively,
proportional to 600 nT magnetic field within 0.6 mm of radius distance to the conductor. This
magnetometer demonstrated the first remote sensing of domestic current flow in a conductor
using a Hall Effect sensor.
The second circuit was specifically developed as a replacement for the bulky search coils used
in cable detectors. This circuit provided high sensitivity and low field detectability (50 nT
without, and 500 pT with Ferrites) at 33 kHz using the P2A sensor.
In addition, a 100 kHz bandwidth magnetometer with an outstanding detection capability of 9
nT of magnetic field was designed and developed. This wide band magnetometer provided at
146
least two orders of magnitude improvement in detectability of small currents, smaller
dimensions, compared with commercial Hall Clamp-on Ammeters.
In conclusion, the novel 2DEG GaAs-InGaAs-AlGaAs integrated circuits and the high
sensitivity magnetometers developed in this work provided a number of enhancements
compared to existing technology.
8.2 Future work
In this project, a large emphasis was focused on producing highly sensitive and low power Hall
Effect integrated circuits based on III-V 2DEG technology. As an extension to this work, listed
below are four main areas that can further enhance this new Hall Effect technology.

The DC digital (unipolar) Hall Effect integrated circuit developed in this work operates
with one switching point. This means, this IC only operates with one pole of a magnet,
either south or north. A hysteresis can be added to the comparator in order to form a Schmitt
trigger. The Schmitt trigger would then have two switching points which can be designed
in a way that the IC produces a high output for both south and north poles and produces a
zero when no magnetic field is applied. This would form a bipolar DC Hall Effect integrated
circuit.

Since all the designed ICs in this work are based on III-V technology, and due to their wide
band gap, compared to silicon, using these ICs the operating temperature of the currently
available commercial ICs could be enhanced further. Temperature studies could be
performed on the developed integrated circuits so that they can be characterised at high
temperatures and be used in applications where there are extreme in temperatures. The
commercial Hall ICs have a maximum operating temperature of 150 oC. It is suspected that
the developed ICs in this work would be capable of operating at higher temperatures which
makes them suitable for harsh environments applications.

One of the most common ways employed in many circuits is to use current spinning
technique in order to reduce the DC offset and the 1/f noise generated from the Hall sensor.
An integrated version of this could be designed and developed so that when used along the
AC linear Hall Effect IC, this IC would detect DC magnetic fields as well as high frequency
fields. This technique would also reduce low frequency noise and hence improve
detectability of fields at lower frequencies, however this would add to the complexity and
power consumption to the circuit.
147

An integrated 2-Dimensional array of Hall sensors along with the current source and
amplification circuitries can be developed. This would allow real time magnetic imaging,
presenting enormous advantages over scanning system. This is an emerging field that
should find applications in a wide range of industries. As an example, these can be used in
an array of sensors for magnetic imaging of surface cracks and features, deep cracks, and
cracks initiating from edges of holes on cars and airplanes.
148
Appendix A Scattering Parameters and Parameter Extraction
A.1 High Frequency Measurements [ 138]
An essential understanding of high-frequency data is vital to fully characterise the high-speed
characteristics of devices. In these cases, the use of scattering (S) parameters is especially
critical due to the complications in obtaining precise data at microwave frequencies. This
section discusses the basic concepts that were used to characterise the high-frequency
characteristics of each device.
A.1.1 Scattering parameters
Any circuit with a single input and output is considered a two-port network. This type of device
may be considered and characterised by relationships between input voltages and currents (V1
and I1), and output voltages and currents (V2 and I2) (Figure A.1). Important device features
(such as gain) can be calculated and determined from known relationships amongst these
signals.
V1
2-PORT
I1
V2
I2
Figure A.1 – A “two-port” network characterised by relationships between the input and
output signals
Normally, below microwave frequencies these relationships are specified in terms of H, Y or
Z parameters, and taken from simple measurements:
V1  h11I 1  h12V2
V2  h21I 1  h22V2
I 1  y11V1  y12V2
I 2  y 21V1  y 22V2
V1  z11I 1  z12 I 2
V2  z 21I 1  z 22 I 2
(H-parameters)
(A.1)
(Y-parameters)
(A.2)
(Z-parameters)
(A.3)
149
At microwave frequencies two distinct difficulties occur:
1. High gain microwave devices normally oscillate once their terminals are shorted, and
thus become unstable
2. Obtaining precise shorts or open circuits at microwave frequencies is difficult, since
considerable impedances can result from very small inductances or capacitances
This limits the use of standard H, Y or Z network parameters at microwave frequencies. Sparameters conversely, prevents the stability issue as both the signal source input and output
are connected to transmission lines which are impedance terminated (normally to 50 ). As
the signal source is switched on, there will be incident and reflected voltage waves on the
source side of the two-port (Ei1, and Er1) and incident and reflected waves on the output side
of the two-port (Ei2, and Er2) resulting in a standing wave pattern. This is shown in Figure A.2.
Figure A.2 – A “two-port” connected by transmission lines to a source and load showing the
incident and reflected signals that occur
Defining each of these incident and reflected waves as new variables gives an easy approach
to extracting the required S-parameters:
Source
a1 
Ei1
Output
a2 
Ei 2
Zo
Zo
b1 
E r1
b2 
Er 2
Zo
Zo
(A.4)
(A.5)
Where Z0 is the characteristic impedance of the transmission line, a1 and b1, a2 and b2 represent
normalised complex incident and reflected voltage waves from source and output respectively.
The S-parameters are defined by:
150
b1  S11a1  S12a2
(A.6)
b2  S 21a1  S 22a2
(A.7)
The Sij can be measured by hindering one of the ai to be zero. For example, with a1=0 and by
terminating the transmission line in its characteristic impedance Z0:
S12 
b1
a2
(A.8)
These parameters are called scattering parameters as the reflected b waves can be considered
to be “scattered” by the device from the incoming a waves. The S-parameters have simple
definitions in terms of the normalised voltage waves, ai and bi:
S11 = input reflection coefficient with output matched
S22 = output reflection coefficient with input matched
S21 = forward transmission coefficient with the output matched
S12 = reverse reflection coefficient with input matched
A.1.2 fT and fmax Measurements
As discussed previously in Chapter 4, the quantities used to determine the high frequency
performance of devices are fT and fmax. fT is expressed using H-parameters. The current gain in
this case can be seen to be H21, but as explained in section A.1, H-parameters cannot be directly
used at microwave frequencies. Thus, they have to be converted to S-parameters:
H 21 
 S 21
1  S11 1  S22   S12S21
(A.9)
fmax is defined as the frequency at which the unitary power gain becomes one (or 0 dB). The
two most commonly employed methods of describing the power gain of amplifiers are the
maximum available gain (MAG) and maximum stable gain (MSG). MAG is determined by:
151
MAG 
S 21
k  k 2 1
S12
(A.10)
Where k is the stability factor:
1  S11  S 22  D
2
k
2
2
2 S12 S 21
(A.11)
Where D is the determinant of the scattering matrix, given by:
D  S11S 22  S12 S 21
(A.12)
The amplifier is stable if k>1 and leads to a definition of maximum stable gain:
MSG 
S 21
S12
(A.13)
Although MAG is the maximum power gain that can be achieved using input and output
impedance matching networks, further gain can be added by using an additionally “feedback”
network to neutralise feedback. This is the highest power gain the two port could obtain, and
is called the Mason’s unilateral power gain, U. It is determined from:
U
S 21
1
S12
2
S 
S
2k 21  Re 21 
S12
 S12 
(A.14)
U is used to define the quantity fmax. Assuming a –20 dB/decade frequency dependence of
Masons unilateral gain and current gain, fT and fmax can be extrapolated (depicted in Figure
A.3).
152
Figure A.3 – Extrapolation of U and H21 to provide fT and fmax [73]
153
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