Bang-Bang Digital PLLs at 11 GHz and
20 GHz with sub-200-fs Integrated Jitter
for High Speed Serial Communication
Applications
A. Rylyakov, J. Tierno, H. Ainspan,
J.-O. Plouchart, Z. Toprak Deniz,
J. Bulzacchelli, D. Friedman
IBM T.J. Watson Research Center, Yorktown Heights, NY
1
Motivation
• Goal: demonstrate DPLL adequate for 8- to 11-Gbps and 17to 20-Gbps wireline communication applications:
– jitter (integrated from fc/1667 to fc/2) ~ 0.3 ps rms
– bandwidth: ~ 1 MHz
– integer-N: ~ 40
• A drop-in replacement for analog PLLs, offering:
–
–
–
–
significant area savings
increased programmability
reduced analog content (models, variability, sensitivity)
portability to advanced CMOS technologies
2
Bang-bang DPLL Background
proportional path gain, latency
early/late
KP
Z-D
LC-DCO
ΦREF
BB-PFD
+
KI
ΦFBK
ΦOUT
Z-M
Z-1
÷N
Main design considerations:
• PFD: bang-bang or TDC
• Loop Filter: BB-PLL jitter grows with increase in proportional
path gain (KP ) and latency (D)*
• DCO: tuning range, fine tuning step (KDCO), phase noise
* Walker 1992, Da Dalt 2005, Hanumolu 2007
3
Bang-bang PFD vs TDC
Integer-N LC-DPLL Verilog simulation results
Bang-bang
PFD output
1
0
Feedback
2
phase error 1
ΦREF − ΦFBK 0
-1
[ps]
-2
400
600
800
Time [ns]
• Bang-bang PFD produces same output as 2 ps resolution TDC
• Need sub-1ps resolution TDC to extract significantly more
information than provided by BB-PFD
200
4
Proportional Path Latency and Gain
Phase Noise [dBc/Hz]
KP = 10 MHz, D=2
σ = 3.9 ps
-80
KP = 10 MHz, D=1
σ = 2.6 ps
KP = 10 MHz, D=0
σ = 1.5 ps
-100
-120
KP = 0.5 MHz, D=0
σ = 0.5 ps
-140
105
Verilog sim.:
N = 40
L = -88 dBc/Hz
at 1 MHz from
fc = 11 GHz
106
107
108
Frequency Offset [Hz] noise integration bandwidth
• Latency (D) of the proportional path should be minimized
• Gain of the proportional path (KP) should be reduced
ÖGain of the integral path needs to be significantly reduced
to keep the loop stable
5
BB-DPLL Block Diagram
fractional delay bits
prop path gain, type
4
coarse
8
early/late
∆ΣM
SEL
12
pcap
LC
delay line controls
48
ROW-COL
EN1 … EN7
7
dithered reference
DELAY
BB-PFD
early/late
reference
inc/dec
8
INT
frac
icap
TANK
DCO
1
∆ΣM
output
dither
2
delay range
phold
1/N
clkg
1/4 or 1/16
6
11 GHz, 20 GHz LC DCO Topology
coarse <1:4>
fine tuning steps KDCO
<1:4>
icap <1:48>
<1:48>
varactors with size offsets
dither, pcap<1:5>
metal-metal overlap
<1:6>
<6:12>
<6:12>
pcap<6:12>
VDDA
KP
VDDA
pcap<6:12>
output
IREF
to prescaler
output_b
Main design challenges:
• preserving oscillator Q while meeting tuning range and KDCO requirements
• realizing low-gain KP
7
LC-DCO Coarse Band Tuning Ranges
11 GHz DCO
12
20 GHz DCO
Frequency [GHz]
22
11
20
10
9
18
8
16
1
4
8 12 16
8
12
DCO Coarse Tuning Band Number
KDCO = 6 MHz − 14 MHz
16
KDCO = 16 MHz − 30 MHz
• The oscillators meet tuning range and KDCO requirements
8
20 GHz BB-DPLL Phase Noise
noise integration
bandwidth
• fc = 20.08 GHz, N=80 (251 MHz reference), no reference dithering
• RMS Jitter: 190 fs (12 MHz to 10 GHz)
• Proportional path: switched metal-metal overlap capacitance
9
11 GHz BB-DPLL Phase Noise and Jitter
pcap
noise integration
bandwidth
KP
RMS
[MHz] Jitter
[fs]
6
4.65
1140
7
2.0
664
8
0.83
375
9
0.35
208
10
0.15
152
11
0.15
145
12
0.15
140
• fc = 11 GHz, N=40 (275 MHz reference), no reference dithering
• RMS Jitter: 140 fs (6.5 MHz to 5.5 GHz); 345 fs (1 kHz to 10 GHz)
• Proportional path: switched metal-metal overlap capacitance pcap<12>
(similar results for nFET in nwell varactors with size offsets pcap<1:5>) 10
BB-DPLL Block Diagram
fractional delay bits
prop path gain, type
4
coarse
8
early/late
∆ΣM
SEL
12
pcap
LC
delay line controls
48
ROW-COL
EN1 … EN7
7
dithered reference
DELAY
BB-PFD
early/late
reference
inc/dec
8
INT
frac
icap
TANK
DCO
1
∆ΣM
output
dither
2
delay range
phold
1/N
clkg
1/4 or 1/16
11
BB-PFD Linearization and Gain
Original non-linear transfer function:
ΦREF − ΦFBK
ΦREF
ΦFBK
Linearized transfer function:
1 1
KPFD =
2π σ IN
ΦREF − ΦFBK
Lee 2004
Da Dalt 2006
• BB-PFD gain is inversely proportional to input jitter
• Low-noise BB-DPLL will have non-linear dynamics
12
Variable Delay Line
EN1
EN2
EN3
EN4
EN5
EN6
EN7
original clean
delay-modulated
reference clock
reference clock
ON
delay per stage
delay sim. meas.
range [ps] [ps]
11
1.7
1.4
10
01
00
4.0
7.6
14.1
3.4
6.1
11.4
EN • delay range<1>
EN • delay range<1>
EN • delay range<0>
EN
ON
• Identical delay cells enable high-order ∆Σ modulation
13
Reference Clock Dithering Simulation
Phase Noise [dBc/Hz]
original reference: flat -140 dBc/Hz phase noise floor
dithered reference: 3rd order ∆Σ modulated (10 ps per delay stage)
-80
dithered reference
-100
original reference
-120
-140
104
105
106
107
Frequency Offset [Hz]
108
• High reference jitter achieved without adding in-band noise
• Effective DPLL linearization, loop bandwidth control
14
Measured 11 GHz Phase Noise Plots
Phase Noise [dBc/Hz]
VDDA=1.2V (17mA), VDD=1.1V (9.2mA), N = 40 (275 MHz reference)
-70
-80
σ = 137 fs
-90
-100
-110
-120
-130
no reference dithering
-140
-150
103
•
•
with reference dithering
σ = 140 fs
104
105 106 107
108
Frequency Offset [Hz]
109
1010
DPLL bandwidth control by proportional path gain or by reference dithering
Reference dithering does not degrade the RMS jitter σ (6.5 MHz to 5.5 GHz)
15
11 GHz BB-DPLL Die Photograph
LC-DCO
Digital Core
CMOS Prescaler
Output Driver
pad pitch: 100 µm
• DPLL area can be improved with more efficient layout
16
BB-DPLL Performance Summary
11 GHz
CMOS Technology
65 nm bulk
410 µm × 215 µm
425 µm × 265 µm
Digital Core
1.1 V, 9.1 mA
1.1 V, 4.5 mA
DCO, Prescalers
1.2 V, 17 mA
1.6 V, 37 mA
31 mW
64 mW
8.1 – 11.8 GHz
16.4 – 22.4 GHz
Area
Voltages,
Currents
20 GHz
Total Power Dissipation
Tuning Range
RMS Jitter ( fc/1167 – fc/2 )
RMS Jitter ( 1MHz – 10 GHz )
Phase Noise (at 10 MHz offset)
138 fs
190 fs
1,2
345 fs 3
962 fs
-121 dBc/Hz
-112 dBc/Hz
RMS jitter (6.5 MHz to 5.5 GHz) measured at 14 points across the 10.64
GHz to 11.16 GHz band (in 1 MHz reference steps) was under 178 fs.
1
2
at T = 125°C, 8.4 GHz the RMS jitter (5 MHz to 4.2 GHz) was 205 fs.
n-cycle jitter under 0.8 ps RMS
(from 1-cycle to 1024-cycle; oscilloscope noise floor ~ 450 fs )
3
17
Conclusion
• Integer-N BB-DPLLs at 11 GHz and 20 GHz meet
integrated jitter and bandwidth requirements of highspeed serial communication applications.
• Key design features:
– low-gain low-latency proportional path control is
directly applied to the DCO
– two different implementation types of DCO
proportional controls demonstrated.
• Time-domain reference dithering technique with noise
shaping to effectively control BB-DPLL bandwidth
demonstrated.
18