MICROWAVE DESIGN
WHITEpaper
The RF Power Behind Design Innovation
EXTENSIVE EXPERTISE AND EXPERIENCE IN CHARACTERIZATION, MODELING,
PACKAGING, AND APPLICATIONS SUPPORT BACKS A LONG-TIME LEADER IN
RF POWER DISCRETE AND INTEGRATED-CIRCUIT (IC) DEVICES.
BASIM NOORI
PETER AAEN
DAVE ABDO
PAUL HART
Manager,RF Power Characterization
e-mail:Basim.Noori@freescale.com
Manager,RF Modeling
e-mail:Peter.Aaen@freescale.com
Director of Packaging
e-mail:Dave.Abdo@freescale.com
Manager,World Wide Applications
e-mail: Paul.Hart@freescale.com
Power density in active devices
is increasing according to the
demands of transistor users. Applications in commercial wireless,
avionics, broadcast, industrial, and
medical systems are pushing the
envelope for solid-state power, with
growing requirements for higher
output power levels from fewer output-stage devices. At Freescale Semiconductor, supplying high-performance radio frequency (RF) and
microwave transistors for these
applications is only part of the challenge, as the company backs its
devices with unparalleled capabilities in characterization, packaging,
and applications engineering.
Freescale Semiconductor enjoys a
rich heritage in fabricating and selling
both discrete and integrated RF semiconductors. Last year, the company
introduced its seventh generation of
silicon RF laterally diffused metaloxide-semiconductor (LDMOS) in
the form of the HV7 process, with the
output power and linearity performance through 3.8 GHz needed for
WiMAX infrastructure applications.
They have also announced a highvoltage version of this process, operating at 48 V, for industrial, scientific,
and medical (ISM) applications.
Freescale has also extended its highpower GaAs PHEMT device perform-
ance to 6 GHz, for WiMAX amplifier
applications.
More recently, the company
announced the first two-stage radiofrequency integrated circuits (RF ICs)
capable of delivering 100 W output
power. When driven by Freescale’s
cost-effective MMG3005N generalpurpose amplifier (GPA), the
MWE6IC9100N and MW7IC181
00N RF ICs form a complete 100-W
power-amplifier solution for wireless
base stations operating at 900 and
1800 MHz.
While the performance levels of
these discrete and integrated RF power devices are outstanding, putting
the devices into the hands of their
customers is only the beginning. Each
shipped device is supported by the
company’s “service-in-waiting” personnel with diversified expertise in
testing, modeling, packaging, and
applications support.
RF Power Characterization
Load-pull (LP) measurement techniques have been increasing in popu-
Modeling
• Model generation
• Verification and validation
Applications
• New product introduction
• Customer support
A Supplement to Microwaves & RF/May 2007
Discrete Design
• New product introduction
• Die evaluation
LOAD PULL SERVICES
LP Enhancements
Device Technology
• Finger selection
•
• Lot sensitivity
IC Design
• New product introduction
• Die evaluation
Packaging
• Material sensitivity
• Thermal impact evaluation
1. Freescale Semiconductor’s
load-pull services include measurements, modeling, and applications support.
Sponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
RF Design Innovation
Typical scalar load-pull system set-up
CW random
two-tone
multitone
Scalar reflection
coefficient and Gt
Large signal
input imedance
AM-AM
AM-PM
ACP and
harmonics
Spectrum
analyzer
VNA
Pref
CCDF
EVM
ACP
IQ
VSA
Power
delivered
to the load
R A B
Pavs
Pdel
25-100 W
High-power
load
Source string
source
tuner
Load
tuner
7 mm
7 mm
Drain and gate
bias supply network
7 mm
Load string
2.A typical load-pull measurement setup at Freescale includes programmable power supplies, vector network
analyzer (VNA), vector signal analyzer (VSA), and supporting hardware3.© 2006 IEEE.Reprinted with permission.
A Supplement to Microwaves & RF/May 2007
Impedance location of pulsed,
modulated, and CW signals
CW
Mod_Signal
Pulse_3 dB
functional groups (Fig. 1). Freescale’s
systems are capable of performing
advanced measurements on devices
with impedances of 0.5 Ω and less. To
enable such advancements, the company has developed a series of specialized test fixtures with optimum impedance
transformation
ratios
transitioning a 50-Ω system characteristic impedance to the low impedances
required for load-pull measurements
of high power transistors.
In addition to the fixture-based systems, Freescale also uses on-wafer
load-pull systems based on commercial
wafer-probe equipment which is used
mainly for device research and development, as well as modeling. The onwafer load-pull system features a
unique three dimensional anti-vibration mechanism to minimize the effects
of tuner vibration, thereby minimizing
probe-to-wafer contact damage.
The accuracy of the Freescale Semiconductor load-pull systems typically
shows transducer gain differential,
G t, of less than 0.25 dB at maximum gamma (0.93 to 0.95 or the
edge of the Smith Chart) and less than
0.1 dB inside the measurement
region.1 This level of accuracy is in
part achieved by the use of precision
7-mm coaxial connectors at all meas-
larity in recent years. RF power amplifiers are generally characterized using
such techniques to determine the
parametric values of, for example,
peak output power, gain and efficiency under various complex load conditions presented at the device reference
plane. The use of multiple complex
modulated signals in the same measurement environment is also becoming increasingly commonplace. For a
manufacturer of high power RF semiconductors, the difficulty in characterizing the products accurately is compounded by the fact that the device
development must be carried out on
large periphery devices, typically 60
mm, presenting terminal impedances
in the sub-0.5-Ω region and with quality factors (Qs) in the range of 8 to 10.
For the past several years, the RF
division of Freescale has developed
several accuracy-enhancement
methodologies and a multitude of
automated custom measurement techniques. The division has well equipped
high reflection (high gamma) load-pull
labs capable of covering frequencies
from 250 MHz to 8 GHz and power
levels as high as 100 W CW (500 W
pulsed) which service the company’s
GaAs, GaN and LDMOS device,
modeling, applications, and other
IS95
CW
Pulsed
Frequency 2.140 to 2.140 GHz
3. This plot shows the optimum load impedance
locations on the Smith Chart for CW, IS-95, and
pulsed modulation formats3.© 2006 IEEE.Reprinted
with permission.
urement reference planes. These connectors exhibit typical VSWR of less
than 1.008:1 at 2 GHz. The center
contact resistance of less than 0.1 mΩ
and excellent calibration characteristics, with unit-to-unit impedance
variation of less than 0.1 percent and
phase variation of less than 0.21 deg.
at 18 GHz also contribute to excellent measurement accuracy.
A thru-reflect-line (TRL) calibration is used with the vector network
analyzer (VNA) in conjunction with
the load-pull test system to achieve
source match of better than 45 dB.2 In
contrast to other VNA calibration
approaches, such as the short-openload-thru (SOLT) method, a TRL calibration is not burdened by the parasitic circuit elements (inherent
additional capacitances and inductances) of the calibration load standard at high frequencies.
Typically, 5000 to 6000 impedance
points are characterized for each tuner
to ensure a uniform distribution across
the source and load impedance planes.
A high density of points is required
when evaluating large periphery
unmatched devices, which are very
sensitive to minimal impedance
changes owing to their low terminal
impedances. Such a high density may
not be required in the assessment of
the relatively high impedance production parts containing package matchSponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
broadcast systems, industrial,
ing elements. In this case, a
scientific, and medical applicasparse load-pull evaluation
tions, and the avionics and
may be conducted.
radar markets is a significant
A typical load-pull setup is
challenge. Designers are
shown in Fig. 2 . Load-pull
required to meet goals for
systems at Freescale are used
improved energy efficiency
to evaluate a device’s peak
from the RF PA, while simultapulse power compression,
neously meeting stringent regAM-to-AM conversion, AMulatory requirements (e.g., for
to-PM conversion, frequency
linearity), and demands for
response and large-signal
lower-cost amplifiers.
device input impedance. The
Traditional
amplifier
systems can also be used for
designs based on the Class AB
measurements of complex sigmode of operation are being
nals to ascertain the average
supplanted by design
and peak power, adjacentapproaches to achieve higher
channel power (ACP), for
efficiency, using architectures
two-tone and multi-tone testing of intermodulation distor- 4. This three-dimensional plot shows the PAE performance of a device under such as Doherty and Envelope
tion (IMD), and to assess the Class AB operating conditions (in blue) versus under Class F operating condi- Tracking, and perhaps by
more inherently nonlinear
device behavior under differ- tions (in red).
modes of operation, such as
ent loading conditions with
amplifiers with Class D, E, F, and othEDGE signals. Freescale also conducts
power at 1-dB compression of better
er operating modes. These conflicting
complementary-cumulative-densitythan +53 dBm (200 W) and gain of
demands for higher efficiency, higher
function (CCDF) analysis of device
19.94 dB at 2.14 GHz (Fig. 5). Armed
linearity, and lower cost mean that the
signal power. The CCDF testing is
with this knowledge, the final matchdesigner is faced with making a multicommon to second-generation (2G)
ing network design of the
dimensional compromise. This is an
and third-generation (3G) wireless
MRF7S21170H becomes a straightextremely difficult task to accomplish
measurements. The requirement to
forward exercise: a choice in load and
using empirically based or “cut-andperform measurements of CW,
source impedances is made in order to
try” approaches. The designer must
pulsed, and modulated signals comes
optimize power density, gain, efficienturn to computer-aided-design (CAD)
from the fact that these signals exert
cy, and a synthesizable matching nettechniques and circuit simulation to
different thermal loading on the
work simultaneously.
optimize the design. This increased
device and, consequently, the optiuse of CAD methods for RF powermum load impedance for each moduModeling Power Devices
amplifier design places a greater
lation format is also different, as
The design of RF power amplifiers
reliance on the availability of accurate
shown in Fig. 3.3 In addition to this
(PAs) for modern communications and
transistor models for simulaextensive measurement capation. More and more compability, Freescale has developed
nies are relying on CAD
valuable data import and post
methodologies to reduce
processing tools to enable the
time-to-market dramatically,
user to analyze rapidly the
and to increase the robustness
behavior of the device under
of the design in the face of
test (DUT) in two-dimensional
process and manufacturing
or three-dimensional planes
variations. For semiconduc(Fig. 4).
tor vendors, the ability to
A pulsed VNA load-pull
provide accurate, nonlinear,
technique is used for measurelectro-thermal models in a
ing a wide range of Freescale’s
timely fashion has become an
power transistors, including
important differentiator
the 170-W WCDMA device
between alternate suppliers.
MRF7S21170H. The load- 5. These swept load-pull power contours were made for a 170-W WCDMA
Power-amplifier designers
pull power contours for the device MRF7S21170H. The results show pulsed output power at 1-dB comchoosing from among
device show a pulsed output pression of better than +53 dBm (200 W) and gain of 19.94 dB at 2.14 GHz.
A Supplement to Microwaves & RF/May 2007
Sponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
RF Design Innovation
Ceramic
Freescale’s extensive lineup of highpower RF transistors are supported
by the comprehensive experience of
Freescale’s RF Modeling team, and an
impressive selection of nonlinear electro-thermal transistor models. The
models, which are available online
from the company’s RF High Power
Model
Library
at
www.freescale.com/rf/models support
a wide range of CAD software tools.
For maximum flexibility, Freescale
works with a large number of software suppliers (known as “Model
Partners”) to ensure the portability of
their device models with popular
CAD tools. Supported CAD tools
include Agilent EEsof ’s ADS™,
Microwave Office™ from Advanced
Wave Research (AWR), Analog
Design Tools™ from APLAC (now an
AWR company), Ansoft Designer™
from Ansoft, and Genesys™ from
Eagleware-Elanix tools (now part of
Agilent Technologies).
E
6. A view of a high-power LDMOS transistor, with
the lid removed to show the complexity of the
internal matching networks and the LDMOS die.2
© 2006 IEEE. Reprinted with permission.
A typical discrete RF transistor
with in-package matching networks is
illustrated in Fig. 6 . The matching
networks are included to improve the
ease-of-use of the product, and its performance, by transforming the low
input and output impedances of the
transistor die to more practical levels.
These matching networks are con-
Lm1
G1
G2
Lm2
G3
Shunt-L
Package
drain
side
MOS1
Package
gate side
Lm1
G1
G2
Lm2
G3
Shunt-L
MOS1
Lm1
G1
G2
Gate
extrinsic
network
Extrinsic shell
Shunt-L
MOS1
Integrated
capacitor
Gate manifold/
Bond-pad
Lm2
G3
Intrinsic
model
Qg
Ig
Drain manifold/
Bond-pad
I
Source
Extrinsic
network
d
Drain
Extrinsic
network
Thermal P
sub-network diss
A Supplement to Microwaves & RF/May 2007
Rth
th
7. An illustration of the
segmented approach to
model development, in
which a packaged transistor is considered as a
system that can be broken down into smaller
components.
structed with small diameter bonding
wires and metal–oxide–semiconductor (MOS) capacitors; in the largest
RF/microwave power transistors
there are between 100 to 200 bondwires and several MOS capacitors all
densely packed into the package cavity. For high-power RF IC products,
the matching networks are constructed using on-chip spiral inductors,
capacitors, and transmission lines.
The matching networks introduce
very high-Q resonances that provide
the necessary impedance transformation. Slight changes to the bond-wire
arrays can result in frequency shifts of
these resonances that may adversely
alter the characteristics of the matching network. In many applications,
bond-wires are considered to be parasitic elements as they only serve as a
means to provide a conductive interconnection between the leads of the
package and the semiconductor
devices contained within it. However,
within RF power transistors they are
not parasitic elements, they are an
integral part of the design and they
must be modeled accurately.
High-power RF and microwave
semiconductor transistors are generally enclosed in air-cavity or overmolded plastic packages. These
packages protect the internal circuitry from the external environment,
and they aid in the removal of heat
generated in the active area of the
transistor. In addition, these packages also serve as components of the
low-loss matching network. Transistors used for wireless infrastructure
applications generate some of the
largest heat fluxes amongst all semiconductor devices and it is important
that the effects of this self-heating are
incorporated into the nonlinear transistor model.
The development of nonlinear electro-thermal models for these packaged transistors taxes the most sophisticated measurement and simulation
techniques available.4 The number of
issues that must be addressed in a successful realization of a model include
Sponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
A Supplement to Microwaves & RF/May 2007
IMD3—dBc
Transducer gain—dB
PAE—percentage
Output power—
r dBm
Imaginary part of impedance—Ω
model for the package and
the electromagnetic (EM)
2.5
Measured
heatsink is found from measinteractions between the eleModel
2.0
urements using high precision
ments of the matching netinfrared (IR) microscopy
works, and between the bond1.5
measurements,7 in which the
wire arrays in the package;
1.0
thermal management; the selftemperature of the transistor
0.5
consistent integration of the
die can be determined while
thermal model with the electriunder RF drive.
0
cal model of the device; and
After a model has been gen–0.5
the construction of the nonlinerated, the final process of valear model of the transistor
idating the model begins, by
–1.0
itself.
comparing the model predic–1.5
Freescale has adopted a segtions against an independent
–2.0
mented approach to model
set of measurements that have
development, 5, 6 in which a
not been used in the model
–2.5
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
generation. Freescale has
packaged transistor is consid—Ω
developed a proven method
ered as a system that can be
for validating its large-signal
broken down into smaller
components, as shown in Fig. 8. Power-added efficiency contours of the power transistor under single-tone models, based on its load-pull
7. Each of the components is pulsed excitation at 865 MHz. © 2007 Cambridge University Press. Reprinted measurement capabilities.
Essentially, CAD tools are
modeled separately, and then with permission.
used to simulate the environthe separate model contribument seen by a high-power device durnents in the in-package matching nettions are integrated into a single moding load-pull testing. Measured loadworks are determined from linear Sel representing the packaged device.
pull S-parameter data for a DUT at
parameter measurements and electroThis approach eases the computationfundamental and harmonic frequenmagnetic simulations.5 The thermal
al load and reduces the complexity of
the modeling task, and features characterization of inter-component cou50
pling, which is included in the final
–20
model for improved accuracy.
45
At the heart of the packaged transistor model is the nonlinear model of
–40
40
the intrinsic transistor. This is extracted from bias-dependent S-parameter
–60
measurements that are made under
35
Measured
Measured
pulsed conditions to create an isotherModel
Model
–80
mal environment. Sophisticated de30
1
10
102
20
25
15
embedding techniques are used to
Output
power
PEP—W
Input
power—
r
dBm
(a)
(b)
describe and remove the manifold and
extrinsic components, enabling the
Measured
nonlinear model to be extracted.
60
Model
Freescale uses both the Root model
25
and the MET (‘Motorola Electro40
Thermal’) model for the nonlinear
6
model description. The thermal com20
ponent for the MET model is deter20
mined from measurements made over
Measured
a range of die temperatures, and it is
Model
0
15
coupled self-consistently with the
35
40
45
50
35
40
45
50
nonlinear electrical model. The MET
(c)
(d)
Output power—
r dBm
Input power—
r dBm
model is the de facto standard nonlinear model for RF power transistors in
9. Measurement and simulations at 865 MHz of output power (a), IM3 (b), PAE (c), and Gt (d) when the source
the common CAD tools.
is matched and the impedance presented to the load is set of maximum PAE. © 2007 Cambridge University
The models for the passive compoPress. Reprinted with permission.
Sponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
RF Design Innovation
10. Several example photographs of air-cavity and over-molded plastic packages are shown on the left and
right halves of the figure.
cies are synchronized to present load
impedances during a nonlinear harmonic balance simulation. The coordination of measurement and modeling
capabilities helps optimize the model
to match the measured results.
An example of the model validation
is shown in Figs. 8 and 9 for a silicon
LDMOS transistor similar to that in
Fig. 6.4 This device has been designed
for N-CDMA, GSM, and GSMEDGE base-station applications in the
860- and 960-MHz bands, and in a
typical GSM application with 28 V
supply and a quiescent drain current of
1200 mA, this transistor is capable of
delivering 160 W CW power at 1 dB
compression. The transistor comprises
three active die, with a total gate
periphery of about 270 mm. An input
matching network is included in the
package: this is a T-network using 78
bond-wires and MOS capacitors.
Models of the constituent components
are derived as described earlier, and a
complete model is then constructed
from these parts. The validation consists of large-signal one- and two-tone
simulations, performed under pulsed
conditions to provide an isothermal
environment. Load-pull measurements using the same thermal conditions and input and output loads are
performed, and compared against the
simulations. Measurements and simulations of the output power, thirdorder intermodulation distortion
(IM3), power-added efficiency (PAE),
and transducer gain are shown in Figs.
8 and 9. These power sweep or driveup measurements were performed
with the packaged transistor tuned at
the output for maximum power-added
efficiency, and maximum output power, respectively. The measured and simulated results are in good agreement
over range of the test conditions.
Packed In Plastic
High-power RF and microwave
semiconductor transistors are generally enclosed within over-molded plastic
(OMP) or air-cavity packages. Transistors used for high-power RF and
microwave applications dissipate substantial amounts of power and consequently operate at high junction temperatures. During the design of a
package, stringent thermal-mechanical design practices are followed to
ensure that the package can dissipate
the substantial heat-flux generated by
the transistor while not degrading its
electrical performance. In addition,
the package must be rugged and have
high mechanical strength to operate
reliably within, for example, cellular
base stations and broadcast systems.
Photographs of typical air-cavity
and OMP packages are shown in Fig.
10. The internal components of the
transistor within the plastic package
are over-molded with a low-loss plastic material. The majority of high
power transistor packages generally
have two or four leads, although new
multi-stage high power RF ICs that
incorporate higher functionality have
more leads. The packages are
designed for the leads to rest on top of
the microstrip transmission lines on a
printed-circuit board (PCB). The
A Supplement to Microwaves & RF/May 2007
back side of the flange contacts the
heatsink of the power amplifier forming a conductive electrical connection
to the bottom conductor of the
microstrip and a conductive thermal
connection to the heatsink, which
enables heat to flow away from the
packaged transistor.
The air-cavity package is the most
expensive component of an assembled
power transistor, attributable to the
materials used in its construction.
Since the power transistor is one of
the most expensive components in a
RF power amplifier, these air-cavity
packages are often a target for cost
reduction through design and material developments.
Over the past six years, Freescale
has systematically re-engineered aircavity package designs with new
materials to improve performance
and decrease the package cost. In
2004, Freescale made a change to the
heatsink materials in their packages,
resulting in 15-to-35-percent
improvement in thermal performance.
With this improvement, the industry
quickly adopted this improved package design.8
Freescale has driven further cost
reductions in the package with the
innovative development of plasticpackaging techniques for high-power
RF transistors. Using an OMP package solution, Freescale is able to offer
RF transistors with power levels of
over 130 W at 2.1 GHz, with performance rivaling that of a metalceramic air-cavity product. To date,
over 30 million RF power transistors
have been delivered in over-molded
packages. Further, Freescale offers
more than a dozen different package
outlines and lead configurations in the
OMP package technology, enabling a
variety of power RF IC products.
These OMP transistors are fully
compatible with traditional highpower RF applications. The fundamental design of the package, its
materials, and the manufacturing
process derive from Freescale’s legacy
of innovations in high-power automoSponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
tive and industrial packages designed
for the most demanding environmental conditions. These are packages
designed to achieve mean time
between failures (MTBF) in excess of
1900 years. The OMP housings feature tighter mechanical tolerances
with significant tolerance improvements (as much as 50 percent) over
traditional air-cavity packages. The
tight dimensional tolerances and
excellent moisture-sensitivity-level
(MSL) rating make these packages
ideally suited for automated PCB
manufacturing at the amplifier subassembly level.
As with the air-cavity housings, the
OMP packages can operate reliably at
device junction temperatures above
+200ºC. An integrated copper heat
sink provides excellent thermal resistance and heat dissipation, and the
packages support lead-free (RoHS)
interconnect processing, with an MSL
rating of 3 or better in a +260ºC
reflow solder process. For those concerned with standards compliance, the OMP packages
are registered with JEDEC.
Freescale evaluates the
performance of its different
package types in a specially
configured thermal-analysis
lab. The thermal performance of a packaged transistor
is a major factor in the system-level
cooling required for a complete wireless base transceiver station (BTS). The
ability of the package to dissipate heat
is determined by its thermal resistance—the temperature difference
between two points due to the power
that is being dissipated.
To obtain the thermal resistance of
a packaged transistor, Freescale has
developed a rigorous methodology,9
using an infrared (IR) microscopy is
used to measure the temperature on
the transistor die while it is operating
under realistic termination impedances and signal excitation. With this
microscope, the temperature distribution across the die can be viewed as a
function of power level, bias level,
matching condition, frequency, and
even by the selected modulation
scheme, such as WCDMA or IS–95. A
photograph of an IR image of a transistor dissipating 60 W power is
shown in Fig. 11.
Using IR microscopy, the maximum
die surface temperature in the measurement field can be located. During
the thermal measurements the temperature at the bottom of the packaged transistor can be determined and
easily monitored by a thermocouple
located directly beneath the transistor’s active cell, or heat-generating
area, as illustrated in Fig. 12. A hole is
drilled in the ceramic lid of the transistor, or the lid is removed to allow an
unimpeded view of the surface of the
die. For OMP packages, the mold
compound can be etched away until
the surface of the die is exposed.
Applications Engineering
Freescale’s four-tiered support
structure for its high-power RF
11. Thermal imaging of an RF transistor dissipating 60 W is illustrated.
Temperature variation across the die
is indicated by changing colors. ©
2007 Cambridge University Press.
Reprinted with permission.
Plastic clamp
Transistor
Ceramic lid
Heatsink
Thermocouple
12. An illustration of the test-fixture used to determine the thermal resistance of a packaged transistor. The opening in the clamp and ceramic lid allow
the IR microscope to have an unimpeded view of
the die. The thermocouple is machined into the
heatsink and positioned to be beneath the active
device heat-generation area. © 2007 Cambridge
University Press. Reprinted with permission.
A Supplement to Microwaves & RF/May 2007
13. This GSM demonstration circuit features the
model MMG3005 GPA driving the MW71C18100N
high-power RF IC.
devices includes inventive and experienced applications engineers who
assist customers with circuit design
and troubleshooting for a wide range
of requirements in commercial industrial, medical, avionics, broadcast,
and cellular infrastructure applications. This role has become a necessity
as the system-level complexity of
modern RF power amplifiers has
increased while the typical design
cycle times have decreased dramatically. Freescale’s RF applications team
focuses closely on these complexities
and how devices are used in customer
applications to facilitate a rapid and
seamless integration of Freescale’s
transistors into customer designs.
To facilitate faster customer design
cycles, Freescale’s applications team
has recently begun developing demonstration circuits of optimized RF
device line-ups for specific, high-volume applications, such as GSM,
CDMA, WCDMA, TD-SCDMA, and
WiMAX. These system-level circuits
are designed to demonstrate the performance of the entire RF line-up
using realistic space constraints, common and economical RF components,
and typical assembly procedures such
as solder reflow, surface-mount, or
device-clamping methods. Additionally, circuit-level efficiency and linearity
enhancement techniques such as
Doherty-combining and analog predistortion (APD) approaches are
incorporated when possible for customers to understand the benefits of
different design methods. The goal is
to create RF line-up demonstrators for
Sponsored by Freescale Semiconductor
MICROWAVE DESIGN
WHITEpaper
RF Design Innovation
20
–40
15
–45
10
–50
5
–55
Gain
45
1805 MHz
1840 MHz
1880 MHz
40
4
(Demo Fixture) MW61C2215N Driving MRF6S21100H
6-Carrier TD-SCDMA 2017.5 MHz 28 V/95 mA 28 V/170 mA 28 V/600 mA
50
–40
3
45
2
40
1
35
(Demo-Fixture) MMG3005N driving MW71C 18100N
GSM-Edge 5 V/500 mA 28 V/215 mA 28 V/800 mA
(Demo-Fixture) MMG3005N driving MW71C 18100N
GSM-Edge 5 V/500 mA 28 V/215 mA 28 V/800 mA
50
35
1805 MHz
1840 MHz
1880 MHz
Gain
EVM
0
–60
0
30
25
–5
–65
–1
25
20
–10
–70
–2
20
15
–15
–75
–3
15
–20
–80
–4
10
–5
5
–6
0
30
P.A.E.
A
Gain (dB)
PAE (%)
S-RR Alt 1
IRL
10
400 kHz
–50
S-R Alt 2
–55
600 kHz
–25
5
0
–30
28
30
32
34
36
38 40 42
Pout—dBm
–45
Alt2_L (dBc)
Alt2_U (dBc)
Alt 1_L (dBc)
Alt1_U (dBc)
44
46
48
50
PAE
–85
–90
28
30
32
34
36
38 40 42
Pout—dBm
44
46
48
50
14. These curves show the performance of the GSM
demonstration board at 1805, 1840, and 1880
MHz.
15. These curves plot the measured spectral
regrowth and EVM performance of the GSM demonstration board.
common applications that can be easily incorporated into customer systems.
One example of a line-up demonstration circuit is shown in Fig. 13.
This circuit was created to demonstrate a complete 1800-MHz GSM
lineup consisting of the MMG3005
GPA driving the MW7IC18100N
high-power RF IC. The MMG3005 is
a Class A biased InGaP HBT with +30
dBm-rated output power at 1 dB compression. The MW7IC18100N is an
HV7 LDMOS two-stage RF IC with
100 W (+50 dBm) rated output power
at 1 dB compression. Together, these
two devices create a high-performance
1800 MHz GSM line-up with nearly
50 dB of gain, 37 percent line-up efficiency, and 1.5 percent EVM performance at +46 dBm output power, as
shown in Figs. 14 and 15. The lowcost plastic packaging, compact circuit
layout, and minimal use of RF components make this applications line-up an
ideal solution for the cost-sensitive
GSM market.
Figure 16 shows the typical performance of an RF line-up demonstration circuit that was created for
the emerging TD-SCDMA market in
The People’s Republic of China. This
circuit consists of the MW6IC2215N
RF IC driving the MRF6S21100H
discrete transistor. The MW6
IC2215N is an HV6 LDMOS twostage RF IC and the MRF6S21100H
is an HV6 LDMOS discrete ceramic
transistor. These devices have rated
output power at 1 dB compression of
15 W and 100 W, respectively. While
neither of these devices was targeted
specifically for the TD-SCDMA market, when evaluated together they
demonstrate excellent six-carrier
TD-SCDMA performance. At +38
dBm output power, the line-up gain
is 43 dB, the uncorrected adjacent
channel power is –51.4 dBc, and the
uncorrected alternate-channel power
is –52.3 dBc. These performance levels are achieved with an industryleading line-up efficiency of nearly
15 percent.
In addition to line-up demonstration circuits, circuit-design assistance,
and system troubleshooting,
Freescale’s applications engineering
group works closely with the modeling and measurement teams to fully
characterize the large-signal behavior
of Freescale’s RF power products.
With these four groups in RF characterization, modeling, packaging and
applications engineering, Freescale is
much more than a device supplier—
it’s a company that offers a comprehensive set of tools to aid in the success of its customers.
A Supplement to Microwaves & RF/May 2007
–60
28 29
30
31
32
33
34
35 36
—dBm
37
38
39
40
16. Although the individual parts were not originally designed for TD-SCDMA performance, they
combine for this demonstrator circuit to provide
this gain, efficiency, and spectral-regrowth
performance.
REFERENCES
1. J. Sevic, “Basic Verification of Power Loadpull Systems,” Maury Microwave Corp.,
Ontario, CA, Application Note 5C-055.
2. G.F. Engen and C. Hoer, “Thru-Reflect-Line:
An improved Technique for Calibrating the Dual
Six-Port Automatic Network Analyzer,” IEEE
Transactions on Microwave Theory & Techniques, Vol. MTT-27, No. 12, December 1979.
3. Noori et al., “Load-Pull Measurements Using
Modulated Signals,” 36th European Microwave
Conference, 2006.
4. P.H. Aaen, J.A. Pla, and J. Wood, Modeling
and Characterization of RF and Microwave
Power FETs, Cambridge University Press: UK,
2007.
5. P.H. Aaen, J.A. Pla, and C.A. Balanis, “Modeling techniques suitable for CAD-based design of
internal matching networks of high-power
RF/microwave transistors,” IEEE Trans.
Microwave Theory and Tech., Vol. 54 (7), pp.
3052-3059, July 2006.
6. W.R. Curtice, J.A. Pla, D. Bridges, T. Liang,
and E.E. Shumate, “A new dynamic electro-thermal nonlinear model for silicon RF LDMOS
FETs”, in IEEE International Microwave Symposium Digest, Anaheim, CA, pp 419-422, June
1999.
7. M. Mahalingam and E. Mares, Thermal Measurement Methodology of RF Power Amplifiers,
Freescale Semiconductor, Inc., 2004.
www.freescale.com/files/rfif/doc/appnote/AN19
55.pdf
8. M. Mahalingam, M. McCloskey, V.
Viswanathan, “Low Rth Device Packaging for
High Power RF LDMOS Transistors for Cellular
and 3G Base Station Use,” in Microwave Product Digest, p. 18, May 2003.
9. M. Mahalingam and E. Mares, “Infrared Temperature Characterization of High Power RF
Devices,” Proceedings of IEEE MTT-S International Microwave Symposium, May 2001.
www.freescale.com/rfpower
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