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# 2003 Kluwer Academic Publishers. Manufactured in The Netherlands.
Response Time Driven Scheduling for
Programmable Logic Controllers With
Network-Based I/O Systems
SEUNGKWEON JEONG
R&D Division, Woori Tech. Inc., 1595-1, Bongchun-7dong, Seoul, 151-835, Korea
skjeong@wooritg.com
NAEHYUCK CHANG
naehyuck@snu.ac.kr
School of Computer Science and Engineering, Seoul National University, Seoul, 151-742, Korea
WOOK HYUN KWON
School of Electrical Engineering, Seoul National University, Seoul, 151-742, Korea
whkwon@cisl.snu.ac.kr
Abstract. This paper introduces a scheduling method for a programmable logic controller (PLC) working under
a multi-tasking, multi-processor and network-based I/O subsystem environment. We construct a generic
architectural and behavioral model of a PLC and extract precise timing constraints. A heuristic algorithm is
developed to satisfy the two objectives, timing constraints and low resource occupation at the same time. A
synchronization scheme between program execution and data transmission is also developed, which enables the
developed algorithm to accommodate multi-processor PLCs. We analyze the performance and implement the
proposed method to demonstrate feasibility.
Keywords: programmable logic controller, network-based I/O, scheduling algorithm, response time
1.
Introduction
Programmable logic controllers (PLC) are sequence control devices that are developed to
replace electro-mechanical relay hard-wired controllers. PLCs are equipped with
microprocessors and control the plant by periodic actions such as sensing the state of
the plant, executing the control task, and updating actuators. They are widely used in
¯exible manufacturing systems, chemical processes, transportation systems, etc.
(Warnock, 1988; Simpson, 1994). As factories progress in automation, PLCs
accommodate more sensors and actuators distributed in the vast area, which results in
high wiring cost. Recently, local I/O subsystems get connected over ®eld networks to
replace wire bundles. At the same time, PLCs support multi-tasking facilities to handle
multiple sequence control programs (GE Fanuc Automation, 1992; ABAS, 1994;
SIMATIC, 1994). Consequently, we have scheduling problems in PLCs including
networked I/Os, as in general purpose multi processing computers. This paper introduces
a scheduling method for PLCs, which is associated with timing constraints in the control
context.
A popular performance metric of the PLC has been the speed of a processing unit, I/O
subsystems and a network. However, the more accurate metric is the worst-case response
time that guarantees timely control actions. The response time of a PLC is a control
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context and different from the conventional response time in scheduling. We name it, in
this paper, the controller response time. The worst-case controller response time is the
worst-case delay between the state change of the plant and the corresponding action of
the PLC (Bonfatti et al., 1977). A PLC detects the state change of the plant on periodic
execution, so the worst-case controller response time is the sum of the period of
execution and the worst-case processing delay of the PLC. The worst-case controller
response time has been shorten by reducing the worst-case processing delay while the
period of execution remains ®xed as a given term. The system bus performing bit-wise
operation was introduced for a multi-processor architecture to reduce the worst-case
processing delay by shortening the I/O update time (Kwon et al., 1994). A multiprocessor architecture based on the data ¯ow architecture was suggested for the
instruction-level multi-processing to reduce the worst-case processing delay (Park et al.,
1993). The network contention was resolved in loosely coupled multi-processor PLCs to
reduce the worst-case processing delay (Park et al., 1997).
As PLCs become complex, the worst-case controller response time depends on various
factors. A sequence control program for a large-scale plant consists of many subprograms, which have precedence relations and contend for the shared resources such as a
common memory, a system bus, and a network. This may results in the increased worstcase controller response time due to the discontinuous execution of the related subprograms and contention of shared resources (Jeong et al., 1997). Thus, the proper
schedule of sub-programs can reduce the worst-case controller response time. Almost all
conventional scheduling methods premise a ®xed given period of execution. In the
control context, we have the worst-case controller response time as a given constraint
while others are design parameters. In this paper, we propose a scheduling method to
adjust both the period of execution and the worst-case processing delay so that we may
directly handle the worst-case controller response time.
In scheduling tasks of a PLC, another scheduling objective, ef®ciency is required in
addition to the original objective, schedulability. Ef®ciency is achieved by lowering the
required resources for guaranteeing the speci®ed worst-case controller response time. As
the PLC executes the task more ef®ciently, it affords to execute more other tasks, thus
ef®ciency is a practical requirement. When we adjust the period of execution and the
worst-case processing delay, there is a trade-off relation between schedulability and
ef®ciency. Provided the speci®ed worst-case controller response time is guaranteed, a
schedule with the longest period of execution is the most ef®cient one because the tasks
occupy the smallest portion of resources. But the long period of execution results in a
short worst-case processing delay under the speci®ed worst-case controller response time.
We have to pay more cost for the processing power to schedule tasks under the short
worst-case processing delay. In scheduling tasks of a PLC, we have to consider other
timing parameters such as a jitter, a control idle time and precedence relations as the
required timing constraints. The schedule need to be found with a reasonable
computational complexity. Finally, for adopting the schedule the PLC has to support a
synchronization mechanism that works properly among multi-processor execution units.
This paper consists of six sections. Section 2 states the scheduling problem of PLCs.
The timing constraints of PLCs such as the speci®ed worst-case controller response time,
and the speci®ed control idle time, the task precedence relations, and jitter avoidance are
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also analyzed. Section 3 proposes a scheduling method that generates periods and has
acceptable computational complexity. Section 4 evaluates the performance of the
scheduling method. Section 5 introduces a synchronization scheme and demonstrates an
implementation technique. The conclusion is given in Section 6.
2.
Problem Statements
In conventional scheduling, we have deadlines and periods of tasks as given scheduling
constraints. The response time is determined by the latency from the arrival time to the
completion time of a task (Audsley et al., 1993). In contrast, the control text regards the
response time as the controller response time and lets the worst case controller response
time …R† be a given term as a scheduling constraint. R is the worst-case latency between
the instant that the plant gets its state changed and the instant that it receives the control
action appropriate to the changed state. Since an asynchronous event changes the state of
the plant and the PLC detects the the state change by periodic sensing, it tasks maximally
a period of the task …T† for the PLC detecting the state change. The delay between the
state detection and the completion of the corresponding control task is termed as the
processing delay. By the de®nitions, R is the sum of T and the worst-case processing
delay …D†. It is the key problem to determine T and D for a given R in scheduling. Once T
and D are determined, the scheduling problem become similar to conventional scheduling
methods. However, besides of the proper determination of T and D, the irregular interval
of actuation, which is originated from the release jitter of the output data transmission,
should be strictly prohibited in scheduling tasks of a PLC because every actuation can be
a timebase of the sequence control. A control idle time and task precedence relations
should be also considered as scheduling constraints. In scheduling, task-speci®c timing
constraints, which represent the bounds of the initiation time and the completion time of
PLC tasks, are necessary. We need architectural and behavioral models of PLCs to drive
the task-speci®c timing constraints from R, the control idle time, task precedence
relations and the jitter avoidance constraint.
2.1.
Building a PLC Model
The primary functions of a PLC are reading sensors, executing sequence control
programs, and updating actuators. PLCs generally interact with target plants by a timedriven approach. That is, PLCs capture the state change of the target plants and drive
actuators by a cyclic scan. The period of the cyclic scan is generally called by a scan time
T†.
PLCs are commonly composed of execution subsystems (ESs) and I/O subsystems
(IOSs). While IOSs are interconnected over a system-area bus in small-scale PLCs, they
are interconnected over a local-area network in large-scale PLCs. Figure 1 shows a
common architecture of PLCs that have network-based IOSs. To provide enough
bandwidth and low latency for data communication, the ES consists of a program
execution unit (PEU) and data transmission unit (DTU) powered by separate processors.
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The PEU refers to data in the I/O data memory (IODM) that contains mirror images of
the actual values of the sensors and actuators. The DTUs keep data coherency between
the IODM in the ES and sensors/actuators in the IOSs. The PEU executes the program
and the DTUs transmits the data with the period, T. The execution order of the I/O
instructions of the sequence control programs is not the same as the transmission order of
the corresponding I/O data because the I/O data is packetized by the location of the IOSs
and the data type. In computing the PLC-processing delay of a task, the execution time of
the task and the data transmission time of the task should be counted independently. The
delay of the data transfer between the DTU in the ES and the DTU in the IOS must be
bounded. Recently, ®eld bus networks have become suitable solutions for this purpose.
2.2.
Required Timing Constraints
Since the PLC operates synchronous to the periodic time tick but handles asynchronous
events of a plant, a shorter T enables PLCs to accommodate higher-speed plant dynamics.
Although the allowable minimum T often has accounted for a performance measure of
PLCs, R indicates the performance more accurately. Generally, the state of the plant may
Figure 1. Architecture of a PLC with network based I/O systems.
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Figure 2. Timing parameters in a PLC.
change by both internal events and external stimuli (Chang et al., 1995). Sensing the plant
state, the PLC computes the appropriate command to send to the plant within D. After the
plant receives the controller command, it does not respond to the command immediately.
There is a delay in the change of the plant state. We denote the largest plant delay by P. L
is the minimum control idle time, which is the minimum latency of a PLC from the
control update to the next input sensing.
The relation among the timing parameters is shown in Figure 2, where the upward
arrow represents the time instance that the PLC senses the plant state, and the downward
arrow represents the time instance that the PLC actuates the output to the plant. The
meaning of symbols are described in Table 1. The operation of the PLC is visualized on
the upper time axis. The sensing operation repeats by the period of T. Sensing the plant
state, the PLC computes the appropriate command and actuates it to the plant in di . After
the actuating operation, the PLC enters an idle state during li until the next sensing
operation. So, the sum of d i and li equals to T. Qm 1 , Qm and Qm ‡ 1 on the lower time
axis in Figure 2 represent the state of the plant. The plant state may be changed by the
actuation of the PLC such as from Qm 1 to Qm . The latency from the actuation of the
PLC to the change of the plant state is pi . r m is the duration between the beginning of Qm
and the actuation following the ®rst sensing of Qm . By de®nition, Vi D ˆ max…di †,
Vi L ˆ min…li †, Vi P ˆ max…pi †, and Vm R ˆ max…r m †. The relation di ‡ li ˆ T induces that
D ‡ L ˆT. Since the operation of the PLC and the change of the plant state are
asynchronous, it takes T for the PLC detecting the change of the plant state in the worst
case like the case of r m ‡ 1 in Figure 2. Thus, R is the sum of T and D.
PLCs often form the feedback control loops with the plant; it checks how the previous
actuation in¯uences the plant and determines the next actuation value. The proper
feedback control can be accomplished provided that P 5 L. P is a given constant that
depends on the plant dynamics. L is a design parameter that depends on the scheduling.
The in¯uence of L is demonstrated in Figures 3 and 4. Let us assume that the control rules
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Table 1. Nomenclature.
Single-tasking environment
T
di
li
pi
Qm
rm
D
L
P
R
scan time, period of execution
processing delay in ith scan
control idle time in ith scan
plant delay in ith scan
mth plant state
controller response time for Qm
worst-case processing delay
minimum control idle time
worst-case plant delay
worst-case controller response time
Multi-tasking environment
tn
Tn
Dn
Ln
Pn
Rn
Xn , Xn;k
In , In;k
On , On;k
nth sequence control program task
scan time of tn
worst case processing delay of tn
minimum control idle time for tn
plant delay associated with tn
worst case controller response time of tn
execution of tn , execution of tn in Kth scan
input data transmission of tn , input data transmission of tn in Kth scan
output data transmission of tn , output data transmission of tn in Kth scan
E
s
c
NT
K
hp
a[b
O
N…E, s†
SX
SIO
the worst-case execution/transmission time of start time of completion time of number of tasks
the tick scheduler polling period
hyperperiod of t1 ; . . . ; tNT
b refers to the result of a
the most dominant term of normal distribution with mean E and variance s
scaling factor of resource occupation on CPU
scaling factor of resource occupation on network
are (1) increase the output for one degree if the plant state is less than the desired state,
and (2) decrease the output for one degree if the plant state is greater than the desired
state. The plant initial state and the desired state are shown at left side of the ®gures. A
proper feedback control is shown in Figure 3. At the beginning, the PLC senses the plant
state. Since the sensed value is less than the desired one, the PLC actuates the output to
make the plant state increase by one degree according to the control rule within the time
bound D. The plant state increases following the PLC actuation in P. In Figure 4, T is
shortened in order to achieve a short R. In this case, the plant state comes to the desired
state fast. However, the plant becomes marginally unstable due to L 5 P that is caused by
the short T. The PLC cannot control the plant to be stationary at the desired value because
it computes the actuation value from the plant state that has not yet re¯ected the previous
PLC actuation. L 5 P does not induce instability in logic control, so most PLCs ignore L.
When these PLCs are applied to analog control, an additional compensation of P should
be adopted in order to predict the plant dynamics. Since the prediction is dif®cult, P 5 L
should be kept in analog control.
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Figure 3. Effect of L …P 5 L†.
Once R is less than the given speci®cation, a long T is desirable for executing a task
with the low resource occupation. Since R ˆ T ‡ D, D should be reduced for making T
long. D can be reduced depending on hardware performance such as the processor
computing power, the network bandwidth, and the delay of I/O devices. In addition, D
can also be reduced by the task scheduling and the synchronization between the PEU and
the DTU. The traditional operation of PLCs, which does not take scheduling into account,
is shown in Figure 5. At the i-th scan, the program execution …X1;i † starts before the
completion of the input data transmission …I1;i †. The output data transmission …O1;i † also
starts before the completion of X1;i . X1;i is executed with the input data from I1;i 1 . The
output data of X1;i is transmitted over the network at O1;i ‡ 1 . Thus, D ˆ 3T in the case of
Figure 5. Here P L cannot be guaranteed because there is not a non-zero interval
between adjacent control jobs such as fI1;i 1 ; X1;i ; O1;i ‡ 1 g and fI1;i X1;i ‡ 1 O1;i ‡ 2 g. When
the PLC provides a multi-tasking environment, control jobs can be arranged for a short D.
Figure 6 shows an example of scheduled processing, where three sequence programs are
executed in parallel, showing D 5 T and the non-zero L that can be possibly made greater
than P. I;i , E;i and O;i are scheduled to execute on the PEU and the DTU one after
another showing pipelined processing. Thus, the smaller D can be achieved in Figure 6
than in Figure 5.
In the conventional scheduling, the execution of a task has to begin only after the
arrival time and ®nish by the deadline. So there exists a variance of the task execution
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Figure 4. Effect of L …P 4 L†.
Figure 5. D under traditional pipelined operation.
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Figure 6. D under a ideally scheduled multi-tasking environment.
interval, which is denoted by a schedule jitter. The schedule jitter degrades the
performance of the PLC. If the PLC has only the objective of capturing plant events and
actuating the corresponding commands, the performance can be fully represented by R.
However, not all output is generated from the scan input. For instance, some output may
be generated from an internal counter clocked by each scan. If an output port is
programmed to toggle between ON and OFF every scan, the programmer would expect a
rectangle-waveform output whose high-level and low-level are asserted equally. So, the
schedule jitter is not allowed in PLCs.
Finally, the scheduling problem is summarized as the determination of timing
parameters such as s…In;k †, s…Xn;k †, s…On;k †, and the largest Tn with given Rn , Ln , E…In;k †,
E…Xn;k †, and E…On;k † considering the jitter avoidance and the precedence relation.
2.3.
Scheduling Constraints
Without loss of generality, the following conditions are assumed. First, there is no
sporadic task that has the higher priority than periodic tasks. In effect, PLCs have
initialization, diagnosis and system management tasks besides sequence control tasks. If
these kinds of sporadic tasks are more urgent than the sequence control tasks, it is better
to convert the sporadic tasks to periodic tasks. Second, the bound of E…Xn †, E…In † and
E…On † can be computed. The program execution time, E…Xn †, can be estimated as a rough
bound by summing all instruction execution time. For the tight estimation, some
estimation methods were proposed for the general computing systems (Shaw, 1989; Park
and Shaw, 1991; Park, 1993; Puschner and Koza, 1989) and for PLCs (Koo and Kwon,
1996a; 1996b). The size of the I/O data can be obtained by the static measurement of
sequence programs. In ®eldbus networks, the data transmission time, E…In † and E…On †,
can be estimated from the data size and the period of the transmission (Pleinevaux and
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Decotignie, 1988; Tindell et al., 1995; Kim et al., 1998) because the data is transferred in
every scan regardless of the value change.
To schedule the tasks in PLCs, the utilization of the PEU and the DTU is less than 1.
That is
NT
X
E…Xn †
E…In † ‡ E…On †
n ˆ 1 NT
51
T
Tn
n
nˆ1
1†
The requirements described in Section 2.2 yield the following task-speci®c timing
constraints, when Rn and Ln are given parameters as the required speci®cation of the
control task. The meaning of symbols are described in Table 1.
a.
The controller response time of tn should be less than the given Rn , that is,
Tn ‡ c…On;k †
b.
s…In;k † Rn
The latency from the completion of tn to the next scan beginning of tn should be
greater than the given Ln , that is,
Ln s…In;k ‡ 1 †
c.
c…On;k †
The input data transmission should be ®nished before the beginning of the program
execution, that is,
c…In;k † s…Xn;k †
d.
The output data transmission should be started after the program execution is
®nished, that is,
c…Xn;k † s…On;k †
e.
The interval between output data transmissions of tn should be constant, that is,
s…On;k ‡ 1 † ˆ s…On;k † ‡ Tn and c…On;k ‡ 1 † ˆ c…On;k † ‡ Tn
f.
If tn [tm , the task arrangement such that c…Xn †5 c…Xm †5 c…Om †5 c…On † should be
avoided because of the precedence fault.
Constraints a and b are necessary to guarantee the end-to-end timing requirements: Rn
and Ln . Constraints c and d prohibit In , Xn , and On from overlapping with each other.
As long as constraints c and d hold, the given Rn can be guaranteed by the constraint a.
The constraint e enforces the elimination of a schedule jitter. The constraint f is a
necessary condition for keeping data coherency between an IODM and IOSs. When tm
uses the data computed by tn as the input data, the DTU may transmit the output data
from tm prior to that of tn without the constraint f. For example, Figure 7 illustrates a
precedence fault; although Y3 is driven by Y4, Y3 is effective on an actuator earlier
than Y4.
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Figure 7. Task precedence relations.
2.4.
Synchronization
To apply the scheduling method to multi-processor PLCs, a well-behaved synchronization mechanism should be supported. Otherwise, related tasks are executed
discontinuously on different processors, resulting in D longer than the bound. Since
PLCs usually have limited hardware resources as an embedded system, general
synchronization schemes are dif®cult to be implemented. Consequently, we need a new
synchronization scheme that works with limited hardware resources.
3.
3.1.
Task Scheduling Method
Scheduling Algorithm
Generally, a pre-run time scheduling algorithm is preferable when hard real-time
deadlines and precedence relations are speci®ed and the schedule jitter must be avoided
for deterministic responses (Baker and Shaw, 1989; Locke, 1992). Although many
scheduling algorithms have been proposed for the general purpose, they are inadequate
for PLCs because their underlying timing constraints are the periods of tasks, rather than
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the controller response times of tasks. In the PLC scheduling, there is an objective to
reduce the resource occupation by adjusting the period of tasks. Thus, a new scheduling
strategy is necessary to arrange program execution in the PEU and data transmission in
the DTU with a low resource occupation under constraints a to f.
To ®nd a valid schedule with a low resource occupation, we need to determine
fT1 ; . . . ; TNT g earlier than other parameters. Since Dn can be reduced to
E…Xn † ‡ E…In † ‡ E…On †, the maximum Tn becomes Rn E…Xn † E…In † E…On †. As
long as the given speci®cation Rn is guaranteed, making Tn long reduces the resource
occupation. However, a short Dn leads to a tight deadline for program execution and data
transmission, which lowers schedulability. Figure 8 illustrates an example that a feasible
schedule cannot be found due to the tight deadlines. In the ®rst case, Tn is determined as
the longest by minimizing Dn to E…Xn † ‡ E…In † ‡ E…On †. By the scheduling constraints b,
c, and d in Section 2.3, In , Xn , and On are scheduled as c…In † ˆ s…Xn † and c…Xn † ˆ s…On †.
So scheduling is arranging the shaded box. Though the PEU and the DTU are not fully
utilized, no feasible schedule can be found in the ®rst case of Figure 8. If T2 and T3 are
shortened and D2 , D3 are lengthened as in the second case of Figure 8, a valid schedule is
found though the resource occupation of the PEU and the DTU is high.
An optimal schedule can be justi®ed by guaranteeing every Rn and Ln while consuming
the lowest possible resources. In effect, it is dif®cult to ®nd a correlation between Tn and
a feasible schedule. Consequently, a brute-force algorithm, which inspects the feasible
schedule over all the possible combinations of fT1 ; . . . ; TNT g, is required to ®nd an
optimal schedule. It is an NP-complete problem to ®nd the optimal schedule (Garey and
Johnson, 1979).
Figure 8. Schedulability versus T.
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3.1.1.
Brute-Force Algorithm
For the maximum degree of freedom in ®nding the schedule that meets the minimum
resource occupation objective, fT1 ; . . . ; TNT g are necessary to be determined before In , Xn
and On . Since schedule jitter of output data transfers is not allowed, s…On;k † is better to be
found prior to s…In;k † and s…Xn;k † to meet the constraint, s…On;k ‡ 1 † ˆ s…On;k † ‡ Tn . Once
the schedule of On is determined, Xn and In can be scheduled over hp. The arrival times
and the deadlines of Xn and In are derived from the scheduling constraint a±d in Section
2.3.
Tn is bounded as (2) because Dn ‡ Ln ˆ Tn , Tn ‡ Dn ˆ Rn , and E…Xn † ‡ E…In † ‡ E…On †
is the low bound of Dn .
E…Xn † ‡ E…In † ‡ E…On † ‡ Ln Tn Rn
E…Xn †
E…In †
E…On †
2†
Overall combination of fT1 ; T2 ; . . . ; TNT g, the optimal schedule should be inspected. If
the polling interval of the tick scheduler is denoted by K, Tn is an integer multiple of K.
So the number of combination of fT1 ; T2 ; . . . ; TNT g is
NT
Y
Rn
Ln
nˆ1
2…E…In † ‡ E…Xn † ‡ E…On ††
K
The sum of the resource occupation of tn is less than 1 as (1), which induces E 6
Xn † ‡ E…In † ‡ E…On † 5 Rn when NT is large. The number of combination is
approximated as
NT
Y
Rn
nˆ1
K
Ln
For each combination of fT1 ; T2 ; . . . ; TNT g, s…On † can be decided as the one from Tn =K
number of the sample space due to the constraint s…On;k ‡ 1 † ˆ s…On;k † ‡ Tn . To decide
s…On †, hp=Tn investigation loops are necessary because On should not overlap with
O1 ; . . . ; On 1 , On ‡ 1 ; . . . ; ONT within hp. So the scheduling of On must investigate hp/K
number of cases. In scheduling Xn and In , the investigation repeats hp=Tn times
respectively since Xn and In appear hp=Tn times in hp. Thus, the total number of the
investigation for obtaining the optimal solution is given by
NT
hp3NT Y
Rn L n
K 2NT n ˆ 1 Tn2
3†
N
The worst-case complexity to ®nd the optimal schedule becomes O……hp=K† T †. An
investigation of all the possible combinations will lead to an optimal solution. However,
the computation time may be impractical even though it is a pre-run time algorithm.
Therefore, a practical heuristic is required to make the idea applicable.
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Table 2. Input and output parameters for the suggested heuristic scheduling algorithm.
Input parameter:
R1 ; R2 ; . . . ; RNT /*Given worst-case controller response time*/
L1 ; L2 ; . . . ; LNT /*Given minimum control idle time*/
E…X1 †; E…X2 †; . . . ; E…XNT † /*Program execution time*/
E…I1 †; E…I2 †; . . . ; E…INT † /*Input data transmission time*/
E…O1 †; E…O2 †; . . . ; E…ONT † /*Output data transmission time*/
Output parameter:
T1 ; T2 ; . . . ; TNT /*Period of Xn , In and On */
DE1 ; DE2 ; . . . ; DENT /*Xn is executed in ftjt%Tn [ DEn g*/
DI1 ; DI2 ; . . . ; DINT /*In is executed in ftjt%Tn [ DIn g*/
DO1 ; DO2 ; . . . ; DONT /*On is executed in ftjt%Tn [ DOn g*/
/*% represents modulus operator to get the remainder of a division*/
Variables:
ex
Aex
cr , Apv /*Laxity in PEU*/
io
Aio
cr , Apv /*Laxity in DTU*/
Bex , Bio /*Temporary laxity for checking the schedulability allowing the tasks across the boundary of Tn */
si , ci , ce , co /*Temporary variables*/
3.1.2.
Heuristic Algorithm
This paper suggests each Tn to be an integer multiple of Tn 1 if Rn 1 Rn . The integer
multiple constraint easily guarantees s…In;k † ˆ s…In;k 1 † ‡ Tn , s…Xn;k † ˆ s…Xn;k 1 † ‡ Tn
and s…On;k † ˆ s…On;k 1 † ‡ Tn . Thus, the parameters in Table 2 are independent of the
index variable K that numbers the scan cycle. So the investigation domain of scheduling
becomes Tn , not hp. The feasible schedule can be found with acceptable computation and
the schedule jitter can be avoided due to the integer multiple relation.
While the optimal algorithm tries to allocate all tasks concurrently, the heuristic
algorithm does not readjust t1 ; . . . ; tn 1 which have been already scheduled in
scheduling tn . The suggested heuristic sorts ft1 ; t2 ; . . . ; tNT g ®rstly so that
R1 R2 RNT , and then it determines T1 ; . . . ; TNT in increasing order of the
index. This implies that Tm Tn if 1 m n NT . For a tn , the algorithm schedules In ,
Xn and On so that In , Xn and On may occupy the slack of t1 ; t2 ; . . . ; tn 1 in sequence such
as c…In † ˆ s…Xn † and c…Xn † ˆ s…On †. If c…On † s…In † Dn cannot be met for any s…In †,
Tn is changed to Tn Tn 1 to increase Dn by Tn 1. Then In , Xn and On are tried to
schedule again. Unless In , Xn and On are schedulable, reduction of Tn repeats while
E…In † ‡ E…Xn † ‡ E…On † ‡ Ln Tn .
Table 3 shows a pseudo code of the suggested heuristic algorithm. Figure 9 illustrates
an example consisting of three task sets such that fI1 ; X1 ; O1 jE…I1 † ˆ 10;
E…X1 † ˆ 10; E…O1 † ˆ 10g, fI2 ; X2 ; O2 jE…I2 † ˆ 20; E…X2 † ˆ 30; E…O2 † ˆ 25g and
fI3 ; X3 ; O3 jE…I3 † ˆ 30; E…X3 † ˆ 60; E…O3 † ˆ 45g. The given constraints are R1 ˆ 90,
L1 ˆ 10, R2 ˆ 300, L2 ˆ 60, R3 ˆ 700 and L3 ˆ 60. First T1 is determined as the largest
possible value. It is 60 by R1 …E…I1 † ‡ E…X1 † ‡ E…O1 ††. Then I1 , X1 and O1 are
arranged such that c…I1 † ˆ s…X1 † and c…X1 † ˆ s…O1 †. Since there is no previously
scheduled task, I1 , X1 and O1 are arranged one after another from the beginning of T1
such as bold rimmed rectangles in Figure 9. Since s…I1 † ˆ 0 and c…O1 † ˆ 30,
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Table 3. Suggested heuristic scheduling algorithm for t1 ; t2 ; . . . ; tNT .
Scheduler(){
T1 ˆ R1 E…X1 † E…I1 † E…O1 †;
if(T1 5E…X1 † ‡ E…I1 † ‡ E…O1 † ‡ L1 ) return SCHEDULE_NO;
DI1 ˆ ftj0 t E…I1 †g;
DE1 ˆ ftjE…I1 † t E…I1 † ‡ E…X1 †g;
DO1 ˆ ftjE…I1 † ‡ E…X1 † t E…I1 † ‡ E…X1 † ‡ E…O1 †g;
Aex
DE1 ;
pv ˆ ftj0 t T1 g
io
Aio
DI1 DO1 ; /*Aex
pv ˆ ftj0 t T1 g
pv and Apv show the laxity*/
for …n ˆ 2; n NT ; ‡ ‡ n†{
j
k
M ˆ Rn E…Xn † T E…In † E…On † ;
n 1
/*®nd the maximum integer multiple between Tn 1 and Tn */
Fg ˆ DOING;
while(Fg ˆ ˆ DOING){
Tn ˆ M Tn 1 ; /*Integer multiple relation between Ts*/
if…Tn 5E…Xn † ‡ E…In † ‡ E…On † ‡ Ln ) return SCHEDULE_NO;
Dn ˆ Rn Tn ;
n
j k
o
t
ex
Bex ˆ tj0 t 2Tn ; t
Tn 1 [ Apv ;
n
j k
o
t
io
Bio ˆ tj0 t 2Tn ; t
Tn 1 [ Apv ;
/*Laxity is represented over 0 t 2Tn to allow the tasks crossing the boundary of Tn */
for…si ˆ 0; si 5Tn ; sRi ‡ ˆ K){/*investigation for all possible s…In †*/
i
i
®nd ci such that RDIni dt ˆ E…In †, where DIn ˆ ftjt [ Aio
cr ; s t c g;
i
®nd ce such that RDEin dt ˆ E…Xn †, where DEn ˆ ftjt [ Aex
;
c
t
ce g;
cr
o
io e
®nd c such that DOin dt ˆ E…On †, where DOn ˆ ftjt [ Acr ; c t co g;
/*Schedule In , Xn , On */
for…m ˆ 0; m 5 n; ‡ ‡ m†if(…tn [tm † and …ce 5ce 5co 5co †) break;
if…m=n† continue; /*Jump to for(si if a precedence fault occurs.*/
if…co si Dn †f
Bex ˆ Bex DEn ;
Bio ˆ Bio DIn DOn ; /*Update laxity*/
ex
ex
Aex
cr ˆ ftj0 t Tn ; t [ B and t ‡ Tn [ B g;
io
io
io
Acr ˆ ftj0 t Tn ; t [ B and t ‡ Tn [ B g;
/*Laxity is represented over 0 t Tn */
if(n ˆˆ NT ) return SCHEDULE_OK;
Fg ˆ INITIAL; /*Enforce breaking out of the while-loop for the next task to be scheduled*/
break;
} /*if*/
} /*for-loop: checks schedulability with changing si */
± ±M;
} /*while-loop: checks schedulability with reducing Tn */
ex
Aex
pv ˆ Acr ;
io
Apv ˆ Aio
cr ;
} /*for-loop: schedules tasks one by one*/
} /*Scheduler*/
c…O1 † s…I1 † ‡ T1 1 and L1 1 …c…O1 † s…I1 ††. The schedule of I1 , X1 and O1 meets the
given constraints of R1 and L1 . T2 is determined to be 3T1 , which is the largest integer
multiple bounded by R2 …E…I2 † ‡ E…X2 † ‡ E…O2 ††. I2 , X2 and O2 are located in the
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Figure 9. Scheduling example using the suggested heuristic algorithm.
laxity while c…I2 † ˆ s…X2 † and c…X2 † ˆ s…O2 † such as horizontal-lined rectangles in
Figure 9. If s…I2 † is assigned to the ®rst vacant time slot, the constraints of R2 and L2 are
con®rmed. If T3 is determined to be the largest integer multiple of T2 (that is, 3T2 ),
c…O3 † s…I3 † ‡ T3 3 cannot be met whatever value is assigned to s…I3 †. Thus, T3 is
determined to be 2T2 , which yields a valid schedule by the above procedure. The
scheduled I3 , X3 and O3 are shown as the slash-lined rectangles in Figure 9.
4.
Performance Evaluation
Since constraints b and c in Subsection 2.3 are violated in most traditional PLCs, Dn can
be three times as large as Tn as shown in Figure 5. In this case, Tn should be determined
subject to (4) in order to guarantee the given Rn because Tn ‡ Dn ˆ Rn .
Tn Rn
4
4†
As long as the suggested heuristic algorithm is applied to PLCs, the schedule guarantees
Dn ‡ Ln ˆ Tn . Because Tn ‡ Dn ˆ Rn and Dn Tn , the given Rn can be satis®ed only if
Tn is determined such that Tn Rn =2. In addition, Tn is determined to be the largest
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83
possible value subject to (2) by the heuristic algorithm. As the number of task, NT
becomes larger,
E…Xn † ‡ E…In † ‡ E…On †
Rn
becomes smaller because resource occupation of the PEU and the DTU must be bounded
like (1). In this case, Dn can be determined as a much smaller value, so Tn can be as large
as Rn . Thus, in best case, the heuristic guarantees the given Rn and Ln occupying one
fourth of the resources in comparison with traditional approaches. Schedulability of the
suggested heuristic algorithm is shown in Figure 10 and that of the traditional algorithm
is shown in Figure 11. The given task set does not specify Tn as a given parameter, but
lower and upper bounds can be computed such as (2) from the other given parameters, Rn ,
Ln , E…Xn †, E…In † and E…On †. Thus, schedulability is measured for the lowest possible
resource occupation (LPRO) of the PEU and the LPRO of the network for each given
task. The LPRO is computed regarding all Tn as the largest values.
PEU LPRO ˆ
NT
X
nˆ1
Network LPRO ˆ
Rn
E…Xn †
E…Xn † E…In †
Rn
E…In † ‡ E…ON †
E…Xn † E…In † E…On †
NT
X
nˆ1
E…On †
We assume that the resource occupation of every tn is similar because
Tn ! E…Xn † ‡ E…In † ‡ E…On †. This originates from that most PLCs simply repeat the
scan loop with a best-effort scheme and most existing PLC applications still obey
Figure 10. Schedulability of the suggested heuristic algorithm.
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Figure 11. Schedulability in the traditional PLC.
Tn ! E…Xn † ‡ E…In † ‡ E…On †. This assumption reduces the simulation complexity. The
simulation of exploiting schedulability is conducted by various PEU LPRO and network
LPRO. Taking practical applications into account, it is assumed that K of a PLC is 1 ms
and Rn ranges from 50 to 1000 ms with a uniform distribution. For simplicity, P is
regarded as the sum of the sensor delay and the actuator delay, thus ranging from 10 to
50 ms. It is better to minimize the difference between Ln and P, thus 5Ln ˆ Rn is assumed
in the simulation. E…Xn †, E…In † and E…On † are generated such that E…Xn † ˆ SXn E…Xn † ,
IO
E…In † ˆ SIO
n E…In † , E…On † ˆ Sn E…On † , where E…In † and E…On † are sampled from
X
IO
N…E…Xn † , E…Xn † =2†. Sn and Sn are determined so that
Ri
E…Xi †
E…Xi † E…Ii †
E…Oi †
ˆ
Rj
E…Xj †
E…Xj † E…Ij †
5†
E…Oj †
where 1 i, j NT . PEU LPRO and network LPRO range from 0 to 1, respectively,
by adjusting SXn and SIO
n . In the traditional PLC, (4) and (6) should be met to
guarantee Rn and Ln .
E…Xn † Tn ; E…In † ‡ E…On † ‡ Ln Tn
6†
Since (4) and (6) are tighter constraints than (2), traditional PLCs cannot schedule task
sets that can be scheduled by the heuristic algorithm. In Figure 12, the schedulability of
the heuristic is demonstrated for various NT . When NT is small, the probability that a task
set violates (2) is high. Thus, schedulability becomes higher as NT becomes larger.
Due to the integer multiple relation for all Tn , the schedule generated by the heuristic
algorithm may occupy more resources than the optimal schedule. However, the heuristic
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Figure 12. Schedulability versus the number of tasks.
algorithm has linear complexity in computation. Since Tn is an integer multiple of Tn
and determined to be the largest possible under (2), it can be selected from
Rn
E…Xn † ‡ E…In † ‡ E…On ††
Tn 1
Tn
1
number of sample space. When Tn is substituted by the minimum in (2), the worst case
number of the sample space is given by
$
R n Ln
2
E…Xn † ‡ E…In † ‡ E…On ††
Rn
1 ‡Ln
2
%
1
Since E…Xn † ‡ E…In † ‡ E…On † 5 Rn when NT is large, the worst case number of the trial
in determining Tn is less than Rn =Rn 1 . We need Tn =K times of investigations to schedule
In , Xn and On because In , Xn and On are adjacent in the free time slot within Tn . Thus, the
number of investigations for obtaining the heuristic schedule is less than
NT
X
Rn Tn
R
K
nˆ2 n 1
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Since
TN
Rn
T
T
& n ‡ 1 and n ‡ 1 5 T
Rn 1
Tn
Tn
Tn
the worst-case complexity becomes O…NT …TNT † =K†, which is practical in comparison with
that of the optimal schedule, O……hp=K†NT †.
5.
5.1.
Implementation
Network for I/O Data Transmission
In order to implement the suggested pre-run time schedule on a PLC, the program
execution and the data transmission must be reserved on the CPU and the network and
must be synchronized. Thus, a network protocol and an interface mechanism between the
CPU and the network are required to support such requirements. Among many different
kinds of networks, ®eldbuses are suitable because they mostly guarantee the worst-case
transmission delay. The factory instrumentation protocol (FIP) is a good candidate. It
supports a real-time transmission by reserving the required bandwidth in advance. A
centralized FIP controller manages transmission by the pre-run time scheduling.
5.2.
Synchronization in the Execution Subsystem
Although the FIP guarantees the worst-case transmission delay, this is only true for the
physical layer and the data link layer. Thus, the implementation should achieve the
synchronization between the application layer and the data link layer. Accurate
synchronization requires additional hardware support, because the application layer
runs on the PEU and the data link layer runs on the DTU. FULLFIP2, an FIP controller,
supports the special function, ``indication'', that generates hardware-level interrupt
requests to application processors when tagged data is transmitted (General Purpose Field
Communication System, 1995).
As shown in Figure 13, the scheduler is implemented to generate a list of initiation
times for the program execution and the I/O data transmission of each task. The code
generator builds a native code of the sequence control program and an FIP scheduling
table. The FIP scheduling table speci®es the packetization of I/O data and the
transmission time. It also includes the table of the tagged packets whose transmission
time is the same as the initiation time of the program execution. The FIP scheduling table
and the tagged packet table are downloaded to the DTU. The DTU transmits the packets
according to the FIP scheduling table. The DTU also generates an interrupt request to the
PEU when it transmits the tagged packet. The PEU dispatches the associated sequence
control program on receiving an interrupt request.
An example of packet scheduling in the ES and the one of IOSs are visualized in
Figure 14. FIP packets, which are represented by W and Z, are grouped according to the
task and the type of I/O. W and Z on the time axes show the packet updating time at the
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87
Figure 13. Implementation of the scheduler.
packet buffer in the DTU of the ES, the DTU of the IOS, and I/O devices. Packets W4 and
W17 are tagged as the indication packets. When they are transmitted, the FIP controller
indicates the corresponding task execution by an interrupt request. Thus, after all packets
of In are transmitted, the FIP controller interrupts the PEU to invoke execution of the
program of Xn . After execution of Xn , the packets of On are transmitted. The duration
between the invocation of the execution and the initiation of the output data transmission
is guaranteed to be greater than the worst-case execution time of the invoked program by
the generated schedule.
5.3.
Synchronization in the I/O Subsystems
An IOS consists of a DTU and I/O devices. The DTU of the IOS exchanges data packets
in the data buffer with the DTU of the ES. The DTU of the IOS makes the data in the
buffer same to the current value of its I/O devices by the continual polling. Since the data
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packet transmission is ordered according to the sequence program, the order of the packet
transmission may not be in accordance with that of the I/O device access. However, the
polling interval is relatively short in comparison with T because the amount of the data is
small in each IOS and the required operation is only the data movement. So the polling
interval is negligible in scheduling and the Rn can be asserted to be Tn ‡ Dn in most
cases. If the transmission delay in the IOS is not negligible, Rn should be Tn ‡ Dn ‡
2T IOP ‡ Es ‡ Ea where T IOP is the I/O polling interval, Es is the sensor delay, and Ea is
the actuator delay. As shown in Figure 14, it takes Es for the sensor detecting the plant
state change. Sensed data is transferred to the DTU of the IOS after T IOP in the worst
case. Likewise, the actuation data sent to the IOS may be pended in the buffer for T IOP
before the transmission to the actuators. It tasks Ea for transmitting from the DTU of the
IOS to the actuators. The suggested scheduler does not count in the transmission delay of
the IOS. When we need to consider the transmission delay of the IOS, the suggested
scheduler can be made to guarantee Rn by regarding the input parameter Rn as Rn
2T IOP ‡ Es ‡ Ea † because 2T IOP ‡ Es ‡ Ea is the constant that can be determined by the
characteristics of the PLC device.
Figure 14. Schedule in the ES and the IOS.
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6.
89
Conclusions
This paper introduces a response time driven scheduling method that guarantees the given
worst-case controller response time while minimizing the resource occupation, under a
multi-tasking, multi-processor and network based I/O subsystem environment. We build a
precise timing model by analyzing the speci®c behavior of a PLC as an embedded
controller. Based on the timing model, task-speci®c scheduling constraints are extracted
from the response time, the control idle time, and the precedence relation among
sequence programs. This paper suggests a sub-optimal resource-occupation scheduling
algorithm with far less computational complexity than the optimal brute-force scheduling
algorithm. A simulation study validates the signi®cant enhancement in schedulability. We
also construct a synchronization scheme, which guarantees the punctual execution of
tasks on a multi-processor PLC, for a real implementation.
As of today, most PLCs rely on the scan time (the period of a control task execution)
instead of the worst-case controller response time as a performance metric because the
behavior of PLCs and timing constraints have not been fully analyzed. They try to make
the scan time much short to guarantee the required performance, which results in a
needless waste of resources. In this paper, a real-world plant and a PLC are modeled
determinately, and the timing constraints are derived from the models. The suggested
scheduling algorithm determines the period without trial-and-error in guaranteeing the
worst-case response time. In addition, it generates a schedule that requires low resources,
which is suitable for embedded controllers. The proposed implementation technique
enables the tasks to be synchronized precisely for multi-processor PLCs with a popular
®eldbus network, the Field Instrumentation Protocol, thus demonstrating the feasibility.
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Seungkweon Jeong received B.S. and M.S. degrees
in Control and Instrumentation Engineering from
Seoul National University, Korea in 1993 and 1995.
He received a Ph.D. degree in Electrical Engineering
from Seoul National University, Korea in 2000. From
1997 to 2000 he joined the project of developing the
middleware architecture of an open controller and
designing the programmable logic controllers in
Engineering Research Center for Advanced Control
and Instrumentation. He is currently working in R&D
Division of Woori Tech. Inc. His research interests
include real-time control systems, their hardware
architecture, and embedded operating systems.
Naehyuck Chang received B.S., M.S., and Ph.D.
degrees in Control and Instrumentation Engineering,
all from Seoul National University, Korea in 1989,
1992, and 1996. He performed many industrial
research projects such as nuclear power plant control
systems, train control and monitoring systems, steel
plant control systems, and programmable logic
controllers. He joined the University of Michigan in
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Ann Arbor as a Research Fellow in 1997. Since 1997,
he has been with the School of Computer Science and
Engineering at Seoul National University as a faculty
member, and he is currently an Assistant Professor.
His research interests include digital system design
and implementation, system-level power measurement, characterization and reduction, embedded
system design and implementation
Wook Hyun Kwon was born in Korea in 1943. He
received B.S. and M.S. degrees all in Electrical
Engineering from Seoul National University, Korea,
in 1966 and 1972, respectively. He received his Ph.D.
degree in Control from Brown University in 1975.
From 1975 to 1976 he was a research associate at
Brown University, and from 1976 to 1977 he was an
adjunct assistant professor at University of Iowa.
Since 1977, he has been with Seoul National
University, now as a professor. From January 1981
to January 1982 he was a visiting professor at
Stanford University. His current research interests
include robust and predictive controls, time-delay
systems, network analysis, and computer application
for factory automation. Dr. Kwon is the founding
director of Engineering Research Center for
Advanced Control and Instrumentation established
by the Korea Science and Engineering Foundation,
and he also serves President of the Korean Institute of
Electrical Engineers (KIEE) and Vice-President of
International Federation of Automatic Control
(IFAC).
M10766 Kluwer Academic Publishers
Journal of Real Time Systems (TIME)
Tradespools, Frome, Somerset