1
Modeling and Control of a Full-Bridge Modular
Multilevel STATCOM
Wei Li, Member, IEEE, L.-A. Grégoire, Member, IEEE, and J. Bélanger Member, IEEE
Abstract--Due to its unique topology, the Modular Multilevel
STATCOM has many advantages but requires a sophisticated
controller and puts higher requirements on simulation tools. To
simulate the STATCOM in real-time is preferable because it
enables hardware-in-the-loop test of the system in various
scenarios including extreme fault conditions, which cannot be
tested on a real STATCOM. This paper presents a model of fullbridge sub-module which enables fast offline and real-time
simulation of the STATCOM. A control scheme with a new submodule capacitor voltage balancing method is also proposed in
this paper. The model and the controller are investigated for
different operating conditions. Implemented in a real-time
simulator, the model can be simulated in real time at a time step
of 20 µs, 131 times faster than its reference model. As
demonstrated by the results, the proposed control scheme is
effective and robust.
Index Terms-- converter control, FACTS, modeling,
Multilevel Converter, real-time simulation, STATCOM, Voltage
Source Converter (VSC).
T
I. INTRODUCTION
HE modular multilevel converter (MMC), as a recently
emerging converter topology introduced in 2003 by
Marquardt et al, is becoming a promising technology of
medium to high power converter for various applications,
such as renewable energy, smart grid, FACTS, and HVDC
systems [1-6]. In 2010, MMC STATCOM was already
installed in England and New Zealand, and many other similar
projects were under development [7].
A MMC consists of multiple cascaded sub-modules (SM),
the internal structure of which can be a half-bridge, a fullbridge, or a clamp-double SM [8]. This paper studies the
modular multilevel STATCOM using full-bridge SM. Due to
its topology, MMC offers some advantages and unique
features:
1. Its AC voltage and current have low harmonics. A passive
filter becomes unnecessary.
2. MMC arm currents are continuous, and there is no longer a
single bulky capacitor in a DC link.
3. The PWM carrier frequency is low, and consequently the
losses are reduced.
4. Short-circuit of one sub-modules (SM) capacitor has little
effect on others, and the system has fast recovery.
5. The modular structure provides redundancy to temporarily
tolerate breakdown of some SM.
As MMC STATCOM has advantages compared to other
topologies, its controller is more sophisticated to satisfy
additional control requirements, such as SM capacitor voltage
balancing. Also, it places higher requirements on modeling
and simulation tools
Modeling and Hardware-in-the-Loop (HIL) testing of the
MMC and its controller in a real time simulator is preferred,
since it is able to study various scenarios including extreme
fault conditions, which cannot be tested on a real STATCOM.
In [7], even having a STATCOM, to validate the controller
behavior in fault conditions, the converter is modeled by
specialized processor equipment and the grid and the fault is
simulated in a real time simulator. HIL tests can also speed up
development cycles and lower overall costs.
However, simulating a MMC STATCOM in real time is
difficult for to the following reasons.
1. It has a large number of power electronic switches which
force re-computation of the state-space matrix to solve the
system;
2. High frequency switching events may occur between
simulation steps of the fixed-step solvers, which could
cause simulation inaccuracy. Especially in a closed-loop
control, this inaccuracy could be amplified and induce
false controller behaviors.
3. HIL test of a MMC STATCOM requires a large number of
I/O since each SM will exchange capacitor voltage and
gating signals with the controller.
This paper presents a model of full-bridge sub-module,
which is optimized for fast offline simulation and real-time
simulation. A modular multilevel STATCOM, based on this
full-bridge SM block, is modeled and studied. A control
scheme with a new SM capacitor voltage balancing method is
proposed in this paper. The model is tested in a study system
under different operating conditions and the STATCOM
behaviors are presented in the paper. The model performance
in real time simulation, e.g. the time step and accelerating
factor, is also provided.
II. MODELING OF FULL-BRIDGE SM
Wei Li, Luc-André Grégoire, and Jean Bélanger are with Opal-RT
Technologies, Montréal, Canada (e-mail: wei.li@opal-rt.com, lucandre.gregoire@opal-rt.com, jean.belanger@opal-rt.com)
Each SM is a two-terminal device. A full-bridge SM
consists of a dc capacitor and four power electronic switches.
Each switch includes an IGBT, an anti-parallel diode, and an
2
R-C snubber, as in Fig. 1.
Fig. 1 Electrical schematic of full-bridge Sub-Module
The SM terminal voltage is determined by the states of the
four switches. For a SM, there are three operating modes,
namely PWM mode, natural rectifying mode, and forbidden
mode. In the PWM mode, four IGBT, T1 to T4 receive PWM
gating signals. The pair of T1 and T2 has complementary
signals, as well as the pair of T3 and T4. The SM terminal
voltage is either equal to its capacitor voltage, or the negative
of capacitor voltage, or zero.
When there is at least one pair of IGBT being blocked, the
SM is in the natural rectifying mode. The terminal voltage is
determined by the current direction which forces certain antiparallel diodes to conduct. When there is no current, the SM
has high impedance and the terminal voltage is determined by
the external circuit.
Two IGBT in one pair cannot have ON signals at same
time. This mode will short circuit the capacitor and damage
the device and therefore is forbidden.
The possible combination of switch states, the
corresponding operating mode, and the SM terminal voltage
are summarized in TABLE I.
TABLE I
SM SWITCH STATES, OPERATING MODE, AND TERMINAL VOLTAGE
IGBT States
ISM
VAB
Operating Mode
T1
T2
T3
T4
1
0
1
0
**
0
1
0
0
1
**
Vc
PWM mode
0
1
1
0
**
-Vc
0
1
0
1
**
0
1
0
0
0
>0
Vc
1
0
0
0
<0
0
0
1
0
0
>0
-Vc
0
1
0
0
<0
0
0
0
1
0
>0
0
0
0
1
0
<0
-Vc
Natural
rectifying mode
0
0
0
1
>0
Vc
0
0
0
1
<0
0
0
0
0
0
>0
Vc
0
0
0
0
<0
-Vc
0
0
*
*
=0
High impedance
*
*
0
0
=0
High impedance
1
1
*
*
**
Error
Forbidden mode
*
*
1
1
**
Error
*: IGBT is either "1" or "0"; **: ISM is either positive or negative or zero.
This SM block model only allows the PWM and natural
rectifying modes. An R-C snubber is necessary to ensure
numerical stability when the SM becomes of high impedance
in the natural rectifying mode. The R-L value of the snubber is
determined by the model sampling step time and the
STATCOM arm inductor value. This RC snubber is greater
than real value and thus slightly increases the resistive losses
only when the STATCOM is charging through the diodes. In
the PWM mode, this snubber is omitted and therefore has no
effect on the circuit.
From TABLE I, when the STATCOM is in the PWM mode,
the terminal voltage of individual SM is given in (1), where
Vsm-i, N1i, N2i, and Vcap-i are terminal voltage, gating signal of
T1 and T3, and capacitor voltage of i-th SM respectively. N1i
and N2i take the value of either 1 or 0. To simplify the
analyses, conducting voltage drop on IGBT and diode, and
dead-time between ON gating-signals on the upper and lower
gates are ignored here.
(1)
Vsm-i = (N1i- N2i)/2*Vcap-i
III. STATCOM MODEL AND MULTICARRIER PWM
In a MMC STATCOM, multiple SM are connected in
cascade in arms, Fig. 2. In each arm, the SM share the same
current and the total voltage across equals the sum of the
terminal voltage of each individual SM.
Vt-a
Ia
Vt-a
Ib
Ls
Vt-a
Ic
Ls
Sub-module
(SM)
Ls
SM1
SM1
SM1
SM2
SM2
SM2
SMk
SMk
SMk
Vn
Fig. 2 cascaded Full-bridge multilevel STATCOM
The MMC arm current is determined by the voltage
difference across the arm inductor, Ls, as in (2), where Vt-u is
the phase-u voltage, Vn is the STATCOM natural voltage. The
SM capacitor voltage is governed by (3), where Ccap is
capacitance of the SM capacitor.
iu = 1/Ls*∫( Vt-u−Vn−Σ((N1i- N2i)/2*Vcap-i))
Vcap-i=1/Ccap*∫(it-u*(N1i- N2i)/2),
(2)
(3)
The SM gating signals are control variables to regulate arm
currents and capacitor voltages. Increasing (N1i- N2i) will lead
to a negative variation on arm current if capacitor voltages are
fixed in (2) and a positive variation on SM capacitor voltage if
arm current is fixed in (3). However, the arm current and SM
capacitor voltage are coupled in both equations, which makes
control difficult.
In MMC, multicarrier pulse width modulation (PWM) is
used to generate gating signal for multiple SM. The two
commonly used multicarrier PWM techniques are the carrier
disposition method and sub-harmonic method. The former
method shifts the carrier signals in magnitude while the latter
method shifts the carrier in phase. Generally, the sub-
3
harmonic method has the advantage of lower harmonic in AC
voltage and current [9].
In this paper, the phase-shifted multicarrier is used to
generate SM gating signals. For an MMC with k number of
SM in an arm, the triangle carrier signals are evenly
interleaved over a half cycle, i.e. a (π/k) phase shift between
every two consecutive carriers. In steady states, the outcome
PWM signals Ni have the fundamental components of the
reference signal, ni, as well as harmonics. The first harmonic
band is around the carrier frequency.
In one arm, the total PWM signals have the same
fundamental components as the reference, ni, in pu. The
majority harmonics are cancelled and the first harmonic band
is pushed to k times the carrier frequency.
IV. MMC CONTROL SCHEME
The MMC STATCOM control is based on a commonly
used control scheme of 2-level voltage source converter
(VSC), which was originally proposed in [10]. Furthermore,
the MMC controller has to balance the power among the SM
capacitors.
In this paper, a two-control-loop scheme is proposed. One
control loop is used to balance capacitor energy among three
phases, and a separate control loop is used to balance
capacitor voltage within each arm. The overall control scheme
is given in Fig. 3.
Vcap-i
abc
iabc
vabc
Vdcref
Vdc +
Vac +
Vacref -
dq id,iq
abc
dq
PI
Idref
PI I
qref
among within
phases each arm
∆θabc
vd,vq
V. STUDY SYSTEM AND SIMULATION RESULTS
A. Study System
The MMC STATCOM is studied in a test system as in Fig.
4. The test system parameters are given in TABLE II. There is
100 MVA load at the bus of point of common coupling (PCC)
with a power factor of 0.95. The short circuit ratio (SCR) at
PCC is approximately 4, which means the STATCOM has a
weak connection to the grid.
PCC
Source
bus
bus
Lx
Rx
Grid
Load
MMC
STATCOM
sign(iabc)
Cap. Vol. balancing
θabc
reference signal and therefore has minimum impact on the
harmonic contents. However, this scheme will inject small
negative sequence current to the grid due to the phase shift in
its terminal voltage. When the phase shift is limited to a very
small value (0.015 rad or 0.86 deg), the negative sequence
component is limited to minimum.
Signal
reordering
command
θ'abc
Eabc
dq
E
,
d
Decoupled
PWM
E
abc
q
PI control
Carrier
Fig. 3 STATCOM control scheme
To have equal capacitor energy in three phases, a slightly
different phase shift is added to the STATCOM terminal
voltage when the controller transforms the voltage reference
from dq frame to abc frame. With a different power angle, the
powers exchanged between each STATCOM phase with the
grid are slightly different. With proper PI parameters, the
control loop equalizes the capacitor energy, i.e. the capacitor
voltage, among three phases.
To balance the capacitor voltage within an arm, the
capacitor voltages are sorted. According to the arm current
direction, the SM with either the highest or the lowest
capacitor voltage is selected once a switch on or off event is
required by the PWM generator.
The advantage of this scheme is that it has a very fast
response. Also it does not add distortion to the PWM
Fig. 4 A test system with MMC STATCOM
The STATCOM parameter is given in TABLE III. The
carrier signal has a low frequency, i.e. 5 times the line
frequency. The arm inductor has a value of 0.1 pu.
Four scenarios, i.e., the steady state, voltage sag, 3-phaseground ac fault, and SM capacitor dc fault, are studied and the
results are presented in this paper.
TABLE II
TEST SYSTEM PARAMETERS
Description of Parameters
System frequency
Voltage rms at source bus
Voltage rms at PCC bus
Load at PCC bus
Impedance between source
and PCC bus (Lx and Rx)
Value
60 Hz
77 kV
77 kV
95 + j0.3122 MVA
39.3 mH and 2.117 Ohm
TABLE III
MMC STATCOM PARAMETERS
Description of Parameters
Number of SM per Arm
PWM carrier frequency
Arm inductor (Ls)
Arm inductor resistance
SM capacitance
Apparent power rating
Value
20
300 Hz
15.7 mH
0.5929 Ohm
3 mF
100 MVA
4
B. STATCOM Performance at Steady State
In steady state, the STATCOM performance is given in
Fig. 6. All SM capacitor voltages are well balanced and
regulated around 1 pu. The capacitor energy is evenly
distributed among three arms due to the control loop
introduced in the previous section. The good waveforms of
voltage and STATCOM current at the PCC bus show that
passive filter becomes unnecessary, even when the MMC
STATCOM has a weak connection to the grid (SCR = 4). The
voltage and current sequence components are given in TABLE
IV, and their total harmonic distortion (THD) values are listed
in Table V. The negative sequence voltage and current are less
than 0.005 pu and therefore negligible. THD values are less
than 0.5% and a big part of harmonics is at very high
frequency (more than 150th harmonic). The harmonic
spectrum of phase-A voltage and current is given in Fig. 5.
TABLE IV
VOLTAGE AND STATCOM CURRENT SEQUENCE AT PCC BUS
Voltage (pu)
Current (pu)
Positive
sequence
1.00015
0.58579
Negative
sequence
0.00416
0.00226
Zero
sequence
0
0
Fig. 5 Harmonic spectrum of phase-A voltage (above) and STATCOM current
(below) at PCC.
Table V
VOLTAGE AND STATCOM CURRENT THD AT PPC BUS
Voltage
Current
Phase-A
0.22%
0.50%
Phase-B
0.21%
0.47%
Phase-C
0.19%
0.38%
C. STATCOM Performance at Voltage Sag
In this scenario, the source bus voltage drops from 1 pu to
0.9 pu to represent heavy load or fault conditions in the grid.
The STATCOM responses to the voltage sag quickly and the
PCC bus voltage restores to 1 pu within 0.1 s, Fig. 7. The
recovery speed is actually limited by the ramp of Q reference
inside the control to avoid current distortion at the transient.
When the STATCOM reactive power and current
magnitude increases, the SM capacitor voltage ripple
increases. Nevertheless, the capacitor voltages are well
regulated and balanced throughout the voltage sag transient.
D. STATCOM Performance at AC Fault
A three-phase solid grounding fault is applied at PCC and
cleared 0.05 s, or 3 cycles, later. The solid three-phase-ground
fault is selected because it represents the worst ac fault
scenario outside the STATCOM. The STATCOM response is
given in Fig. 8. It is observed that the STATCOM is able to
survive this kind of faults and recover to pre-fault working
conditions very fast (less than 0.1 s) once the fault is cleared.
E. STATCOM Performance at SM Capacitor Fault
A dc short-circuit fault is applied to one SM capacitor and
lasts for 0.05 s, or 3 cycles. During the fault, the capacitor
voltage at that fault SM drops to zero. For a 20-SM-per-arm
STATCOM, the terminal voltage at the fault phase has up to
5% error. Consequently the STATCOM current are affected
depending on the value of the arm inductor.
Once the short-circuit fault is cleared, the capacitor voltage
of the fault SM restores to 1 pu and all capacitor voltages are
well regulated and balanced within a very short period (less
than 2 cycles) due to the proposed capacitor voltage regulating
scheme, Fig. 9.
Even in this study, the controller has no fault detection and
protection circuit, this control scheme shows its effectiveness
and robustness in the ac and dc fault scenarios. If equipped
with protections, the MMC controller can have advanced
performances during fault conditions.
.
5
(a) Maximum (red), minimum (blue), average (green) and one of SM (pink)
capacitor voltage (pu)
(a) Maximum (red), minimum (blue), average (green) and one of SM (pink)
capacitor voltage (pu)
(b) Arm average SM capacitor voltage (pu),phase-A (red), phase-B (blue), and
phase-C (green)
(b) Voltages at PCC bus (pu), phase-A (red), phase-B (blue), and phase-C
(green)
(c) Voltages at PCC bus (pu), phase-A (red), phase-B (blue), and phase-C
(green)
(c) AC voltages magnitude (pu, average value) at PCC bus (red) and source
bus (blue)
(d) STATCOM currents at PCC bus (pu), phase-A (red), phase-B (blue), and
phase-C (green)
(d) STATCOM currents at PCC bus (pu), phase-A (red), phase-B (blue), and
phase-C (green)
(e) STATCOM powers (pu), P (red), and Q (blue)
(e) STATCOM powers (pu), P (red), and Q (blue)
Fig. 6 MMC STATCOM performances at steady states
Fig. 7 MMC STATCOM performances at voltage sag
6
(a) Maximum (red), minimum (blue), average (green) and one of SM (pink)
capacitor voltage (pu)
(a) Maximum (red), minimum (blue), average (green) and the fault SM (pink)
capacitor voltage (pu)
(b) Voltages at PCC bus (pu), phase-A (red), phase-B (blue), and phase-C
(green)
(b) Voltages at PCC bus (pu), phase-A (red), phase-B (blue), and phase-C
(green)
(c) STATCOM currents at PCC bus (pu), phase-A (red), phase-B (blue), and
phase-C (green)
(c) STATCOM currents at PCC bus (pu), phase-A (red), phase-B (blue), and
phase-C (green)
Fig. 8 MMC STATCOM performances at solid 3-phase-ground fault at PCC
bus
Fig. 9 MMC STATCOM performances at dc short-circuit fault on one SM
capacitor
VI. REAL TIME SIMULATION PERFORMANCE
With a real-time digital simulator, eMEGAsim by OPALRT Technologies, this MMC STATCOM model is simulated
in real time with a time step of 20 µs. This model is also able
to simulate offline with a faster speed. The model
performance is compared to a reference model that has the
same devices and parameters but is modeled in Simulink with
SimPowerSystems (SPS) library, TABLE VI. The
Simulink/SPS model is not suitable for real time simulation
since it cannot be solved within the given time step. The
accelerating factor is a ratio of the model simulation speed
compared to the reference model at offline. It can see the
proposed STATCOM model is 2 times faster at offline and
131 faster in real time compared to the reference.
TABLE VI
MODEL PERFORMANCE COMPARISON
Simulation
Accelerating
Simulation Simulation
time for 1 s
factor
mode
time step
model time
1
Simulink/
Offline
20 µs
131.66 s
(reference)
SPS model
Simulink/
Real-time
20 µs
N.A.
N.A.
SPS model
Proposed
Offline
20 µs
63.83 s
2.06
model
Proposed
Real-time
20 µs
1s
131.66
model
Model
7
VII. CONCLUSIONS
This paper introduced a full-bridge modular multilevel
STATCOM model to be implemented in a real-time
simulation platform for fast offline simulation and real-time
simulation. Also this paper proposed a control scheme for
MMC STATCOM. In this scheme, the SM capacitor voltages
are balanced by two control loops, one equalizes the capacitor
energy among three phases, and the other balances the
capacitor voltage within each arm. This scheme has fast
response and minimum impact on the STATCOM voltage and
current harmonics.
The MMC STATCOM and its controller are validated in a
test system for four scenarios, i.e. the steady state, voltage sag,
3-phase-ground ac fault, and SM capacitor dc fault. Results
show the proposed control scheme is effective and robust. In
steady state, the STATCOM voltage and current at PCC has
very low THD (<0.5%) and negative or zero sequence
(<0.005 pu) even in a weak connection with the grid (SCR =
4) without any passive filter. The STATCOM has fast
response to voltage sag, and fast recovery after ac or dc faults,
even without protections circuits.
The model is implemented in a real-time simulator,
eMEGAsim, and is simulated in real time with a time step of
20 µs. Further work will be to include hardware I/O in the
model to enable HIL test of the STATCOM model with an
external controller.
VIII. REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
H.P. Mohammadi,; M.T. Bina,; “A Transformerless Medium-Voltage
STATCOM Topology Based on Extended Modular Multilevel
Converters,” IEEE Trans. Power Electronics, vol. 26 , no. 5, pp. 1534 –
1545, 2011.
U. N. Gnanarathna, A. M. Gole, R. P. Jayasinghe, “Efficient modeling of
modular multilevel HVDC converters (MMC) on electromagnetic
transient simulation programs,” IEEE Trans. Power Delivery, vol. 26 ,
no. 1, pp. 316 – 324, 2011.
M. Saeedifard, R. Iravani, “Dynamic Performance of a Modular
Multilevel Back-to-Back HVDC System,” IEEE Trans. Power Delivery,
vol. 25, no. 4, pp. 2903 – 2912, 2010.
Xiaofeng Yang, Jianghong Li, Wenbao Fan, Xiaopeng Wang, T.Q.
Zheng, “Research on modular multilevel converter based STATCOM,”
6th IEEE Conference on Industrial Electronics and Applications
(ICIEA), 2011, pp.: 2569 – 2574.
Wei Li, Luc-André Gregoire, Jean Bélanger, “Control and Performance
of a Modular Multilevel Converter System,” CIGRÉ Canada,
Conference on Power Systems,Halifax, Sept., 2011, 8 pp.
Y. Zhao; X. Hu; G. Tang; Z. He, “A study on MMC model and its
current control strategies,” in IEEE 2nd International Symposium on
Power Electronics for Distributed Generation Systems (PEDG), 2010,
pp. 259 – 264.
[7]
M. Pereira, D.vRetzmann, J.cLottes, M. Wiesinger, G. Wong, “SVC
PLUS: An MMC STATCOM for network and grid access applications,”
2011 IEEE Trondheim PowerTech, pp. 1 – 5.
[8] R. Marquardt, “Modular Multilevel Converter topologies with DC-Short
circuit current limitation,” IEEE 8th International Conference on Power
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[9] G.S. Konstantinou, V.G. Agelidis, “Performance Evaluation of HalfBridge Cascaded Multilevel Converters Operated with Multicarrier
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[10] C. Schauder and H. Mehta “Vector analysis and control of advanced
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IX. BIOGRAPHIES
Wei Li (M’06) was born in Hangzhou, China.
He received the B.Eng. degree from Zhejiang
University, Hangzhou, in 1996, the M.Eng.
degree from the National University of
Singapore, Singapore, in 2003, and the Ph.D.
degree from McGill University, Montréal, in
2010. He has been working with OPALRT since
2007 as a power system simulation specialist.
His research interests include power electronics,
renewable energy, and distributed generation.
Luc-André Grégoire was born in Joliette,
Canada, on December 8 1981. He received a
B.Ing degree (2008) from École de Technologie
Supérieure (ETS), Montréal, Qc, Canada. He has
also received a M.Ing degree (2010) under the
supervision of professor Al-Haddad at Groupe
de Recherche en Électronique de Puissance et
Commande Industrielle (GREPCI-ETS). In
2009,
Mr.
Grégoire
joined
Opal-RT
Technologies as a Simulation Specialist. His
main fields of interest are renewable energy,
power converters and energy efficiency.
Jean Bélanger (M’87) received his Electrical
Engineering degree in 1971 in Laval University,
in Quebec City, and his Master degree from the
école Polytectnique de Montreal.
Jean Bélanger is the president, CEO and founder
of Opal-RT Technologies, Inc. He is a specialist
in real-time simulation, with more than 25 years
of experience in the field, including many years
as part of the simulation division of HydroQuebec. Mr. Bélanger became a fellow of the
Canadian Academy of Engineering in 2001.